1.Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Ministry of Education, School of Microelectronics, Xidian University, Xi’an 710071, China 2.Xi’an Microelectronics Technology Institute, Xi’an 710071, China
Fund Project:Project supported by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project, China (Grant No. B12026)
Received Date:06 December 2020
Accepted Date:03 March 2021
Available Online:09 July 2021
Published Online:20 July 2021
Abstract:With the rapid development of the traditional inorganic semiconductor industry, the improvement of its electrical performance is gradually approaching to the limit. It is difficult to continue to improve the performance, lessen the size, and reduce the cost. Therefore, organic semiconductor materials and devices with simple process and low cost have been found and gradually become a new research hotspot. Although organic semiconductor materials and devices are developing rapidly, their electrical properties, such as carrier mobility, are considerably inferior to those of inorganic semiconductors, and their research direction and application prospect are relatively fixed and single. They are developed only in display, sensing, photoelectric conversion and other fields, but the researches on switching power devices, integrated circuits and other fields are still relatively blank. At the same time, power devices are used only in the field of inorganic semiconductors. Therefore, in order to expand the research direction of organic semiconductors and power devices at the same time, a novelsilicon on insulator lateral double-diffused metal oxide semiconductor (SOI LDMOS)power device is reported in this paper. Unlike the SOI LDMOS power devices in traditional inorganic semiconductors, this novel device can be used in the field of organic semiconductors by combining with insulated flexible substrates, which provides a new possibility for the research direction of organic semiconductors. In this paper, both simulation and experiment verify that specific on-resistance (RON,sp) and threshold voltage (VTH) do not change significantly when the conventional SOI LDMOS lacks the substrate electrode, but the breakdown voltage decreases by about 15% due to the absence of the substrate electrode or the longitudinal electric field. In response to this phenomenon, in this paper proposed is a novel SOI LDMOS power device that possesses surface substrate electrodes and drift zone oxide trenches. This novel device can provide electrodes for the substrate again, optimize the horizontal and vertical electric field, and significantly change neither of the RON,sp and the VTH. At the same time, the breakdown voltage (BV) of conventional SOI LDMOS is increased by 57.54%, which alleviates the adverse effects caused by the application in the field of organic semiconductors. This novel SOI LDMOS power device provides the possibility of applying traditional power semiconductors to the research of organic semiconductors, and has innovative significance for expanding the organic semiconductor research. Keywords:silicon on insulator/ substrate electrodes/ breakdown voltage/ oxidation groove
表1常规SOI LDMOS与衬底浮空SOI LDMOS器件仿真最优参数 Table1.Simulation optimal parameters of conventional SOI LDMOS/ substrate floating SOI LDMOS devices.
图 2 实验结果 (a) 8 in晶片; 电子扫描显微镜下的SOI LDMOS结构截面图(b)和俯视图(c) Figure2. Experimental results: (a) 8-inch wafer; (b) sectional view and (c) vertical view of SOI LDMOS under an electron scanning microscope.
借助中国航空工业集团公司的下属公司江苏七维测试技术有限公司的测试平台完成了8 in晶圆测试. 测试设备为测试仪T862和探针台JC8001; 测试温度为20—24 ℃; 测试湿度为(45% +/–10%) RH; 测试间洁净度为10000级. 下面通过仿真和流片实验及其测试来对比分析具有RESURF技术常规SOI LDMOS在衬底浮空前后的性能变化. 图3所示为常规且带有RESURF技术的SOI LDMOS在结构参数和掺杂浓度相同时, 衬底浮空前后的表面电场和纵向电场仿真结果对比图. 如图3(a)所示, 在衬底浮空前, 器件耐压主要取决于栅边缘的P阱和漂移区构成的PN结与漏端N+N结, 在表面电场图中表现为表面有两个峰值, 一个位于栅电极附近, 另一个位于漏极附近. 在衬底浮空后, 由于衬底对表面电场的调制作用变差, 表面耐压主要取决于P阱和漂移区构成的PN结, 因此表面电场分布逐渐不均匀, 趋于三角电场, 此时器件更容易击穿. 如图3(b)所示, 衬底浮空前SOI LDMOS因为埋氧层的调制, 能够在较薄衬底时实现较好耐压. 在衬底浮空后, 器件的纵向电场分布明显变差, 埋氧层的调制作用变差, 电场峰值会下降25%左右. 图 3 衬底厚度Tsub = 15 μm, 漂移区长度LD = 4 μm的SOI LDMOS电场分布图 (a) 表面电场分布图; (b) 纵向电场分布图 Figure3. Electric field distribution graph for SOI LDMOS with substrate thickness of 15 μm (Tsub = 15 μm) and drift zone length of 4 μm (LD = 4 μm): (a) Surface electric field distribution graph; (b) longitudinal electric field distribution graph.
图4所示为常规且带有RESURF技术的SOI LDMOS在衬底浮空前后的输出和转移特性仿真与实验结果对比图. 仿真和实验均基于衬底厚度为15 μm和漂移区长度为4 μm的SOI LDMOS. 由于使用ISE-TCAD进行器件仿真时, 虽然考虑了诸如载流子运输模型、载流子产生-复合模型、迁移率模型等影响因素, 还考虑了载流子散射、能带变窄等非理想因素, 但相较于实验所得器件而言, 还是处于较理想状态. 工艺过程中, 由于仪器的精密程度、外延层生长环境和退火条件等因素的影响, 使得实验所得器件性能略差于仿真所得器件, 因此实验所得器件的电流会低于仿真所得结果. 从图4还可以看出, 不论是仿真结果还是实验结果, 衬底浮空对SOI LDMOS转移和输出特性的仿真与实验结果均无明显影响. 其中如图4(b)所示, 因为在衬底浮空后, 衬底对漂移区电场调制效果减弱, 表面电场变弱, 漂移区中载流子速度变慢, 器件准饱和漏电流变小. 因为器件栅极结构和基区掺杂没有变化, 所以在仿真和实验结果中器件的阈值电压均不变. 图 4 衬底厚度Tsub = 15 μm, 漂移区长度LD = 4 μm的SOI LDMOS仿真和实验结果对比 (a) VGS = 5 V时的输出特性曲线; (b) VDS = 10 V时的转移特性曲线 Figure4. Comparison of simulation and experimental results for SOI LDMOS with substrate thickness of 15 μm (Tsub = 15 μm) and drift zone length of 4 μm (LD = 4 μm): (a) Output characteristic curve when VGS = 5 V; (b) transfer characteristic curve when VDS = 10 V.
图5所示为常规且带有RESURF技术的SOI LDMOS在衬底浮空前后的击穿特性仿真与实验结果对比图. 从图5中的仿真结果可以看出, 在相同结构参数和掺杂浓度时, 衬底浮空后, 击穿电压从87.28 V降低到72.13 V, 下降了17.4%. 导致常规SOI LDMOS衬底浮空后击穿电压降低的主要原因如图6所示, 图6为上述两种结构在掺杂浓度相同时仿真击穿电压与漂移区掺杂浓度的关系曲线. 由于衬底浮空后, 缺失衬底电极使得原器件失去RESURF技术, 电场分布也会变化, 从而使得器件最优击穿电压对应的漂移区浓度发生变化, 因此常规SOI LDMOS在衬底浮空后击穿电压会降低. 两种结构的比导通电阻(specific on-resistance, RON,sp)均为2.21 mΩ·cm2, 没有明显变化. 并且由于埋氧层的优势, 零栅压下器件的漏电流均为5 × 10–14 A/μm左右. 从图5中实验结果可以看到, 在衬底浮空后, 器件的击穿电压从80 V下降到60 V. 虽然性能有所下降, 但是仍然可以驱动10个LED灯. 图 5 SOI LDMOS击穿特性的仿真和实验结果对比图 Figure5. SOI LDMOS comparison of simulation and experimental results of breakdown characteristics.
图 6 漂移区掺杂浓度对SOI LDMOS两种结构对应的击穿电压的影响 Figure6. Effect of doping concentration in drift region on breakdown voltage of two SOI LDMOS structures.
4.新型SOI LDMOS的仿真与优化常规且带有RESURF技术的SOI LDMOS在应用于有机半导体领域时会使其衬底浮空, 进而缺失衬底电极和RESURF技术, 性能就会有所降低. 因此提出具有P+多晶硅作表面衬底电极和漂移区氧化槽的新型SOI LDMOS结构. 该新型结构的工艺相较于第3节不同的部分如下: 1)在N阱和P阱工艺完成后, 在器件左端刻蚀一个窗口, 淀积多晶硅并进行P型重掺杂, 从而获得表面衬底电极; 2)器件表面生长钝化层, 在N阱表面刻蚀出一个窗口, 通过干氧工艺生长氧化槽. 该新型结构可以通过转印工艺与柔性衬底结合, 作为开关电源、功率放大器等设备应用于有机集成电路, 从而实现其在研究领域、应用前景等方面的拓展. 下面将针对常规SOI LDMOS、衬底浮空的SOI LDMOS、增加表面衬底电极和衬底浮空的SOI LDMOS以及同时具有P+多晶硅作表面衬底电极和漂移区氧化槽的SOI LDMOS这几种器件的性能进行分析比较. 图7所示为四种器件的表面电场和纵向电场的对比图. 如图7(a)所示, 在衬底浮空后, 漂移区不能完全耗尽, 表面电场分布趋于三角电场. 加上表面衬底电极后, 曲线和有衬底浮空前重合, 器件性能得到优化. 再在漂移区加上氧化槽以后, 漂移区有效长度增加, 器件的表面拓展到槽表面, 能够达到对表面电场的优化效果. 器件的表面电场增加一个新的电场峰, 达到优化表面电场的目的. 如图7(b)所示, 常规SOI LDMOS因为埋氧层的调制, 能够在较薄衬底时实现较好耐压. 当衬底浮空后, 器件的纵向电场分布明显变差, 经过表面衬底电极和漂移区氧化槽的横纵向电场的同时优化, 器件的纵向电场耐压提升. 图 7 几种SOI LDMOS的电场分布图 (a) 表面电场分布图; (b) 纵向电场分布图 Figure7. Electric field distribution of several SOI LDMOS: (a) Surface electric field distribution; (b) longitudinal electric field distribution diagram.
图8和图9所示为几种器件的击穿、转移、输出特性曲线. 由图8可知, 在衬底浮空后, SOI LDMOS的击穿电压从87.28 V降低到72.13 V, 下降了17.4%, 加上表面衬底电极后, 击穿电压恢复到常规SOI LDMOS的击穿电压. 比导通电阻都为2.21 mΩ·cm2, 没有明显变化. 在漂移区加上氧化槽以后, 横纵向电场得到同时优化, 击穿电压提高到137.5 V, 相比于常规SOI LDMOS增加了57.54%. 由图9可知, 增加漂移区氧化槽之前的几种器件阈值电压为0.87 V, 衬底浮空对阈值电压没有明显影响. 在加了漂移区氧化槽后, 阈值电压(threshold voltage, VTH)增加到1.63 V. 与此同时, 衬底浮空对器件的电流、比导通电阻均没有明显影响. 通过上述分析可知, 该新型SOI LDMOS能够较好地缓解衬底浮空后的不良影响, 并且还能在比导通电阻变化不大的情况下提高其击穿电压. 图 8 几种SOI LDMOS的击穿特性图 Figure8. Breakdown characteristics of several SOI LDMOS.
图 9 几种SOI LDMOS的仿真结果 (a) 输出特性曲线; (b) 转移特性曲线 Figure9. Simulation results of several SOI LDMOS: (a) Output characteristic curve; (b) transfer characteristic curve.
图10所示为该新型SOI LDMOS结构中漂移区浓度ND、氧化槽宽度DOX和厚度TOX等参数对击穿电压BV和比导通电阻RON,sp的影响曲线. 如图10(a)所示, BV随ND的增加呈现出先上升后下降的变化趋势, 而RON,sp则呈现出下降的趋势, 因此综合考虑漂移区浓度最终选取5 × 1016—6 × 1016 cm–3. 如图10(b)所示, BV随DOX的增加先迅速上升后变化不大, 而RON,sp变化趋势则与BV相反, 因此选取DOX为3—4 μm. 如图10(c)所示, BV随TOX的增加先上升后下降, 而RON,sp则随之增加呈现持续上升的趋势, 因此最终选取TOX为0.5—0.6 μm, 表2所列为该新型器件优化后对应的结构参数. 最终该新型SOI LDMOS的击穿电压为137.5 V, 比导通电阻为1.96 mΩ·cm2, 能够实现在RON,sp基本不变的情况下将常规SOI LDMOS的BV增加57.54%, 从而实现常规SOI LDMOS在应用于有机半导体领域后衬底浮空时的性能优化, 也实现了将功率开关器件与有机半导体领域的新的突破与创新. 图 10 新型SOI LDMOS的几种参数对BV和RON, sp的影响 (a) ND的影响曲线; (b) DOX的影响曲线; (c) TOX的影响曲线 Figure10. Influence of several parameters of new SOI LDMOS on BV, RON,sp: (a) Influence curve of ND; (b) influence curve of DOX; (c) influence curve of TOX.
器件最优参数(仿真)
新型SOI LDMOS
漂移区厚度TD/μm
2
埋氧层厚度TOX/μm
2
衬底厚度Tsub/μm
15
氧化槽宽度WT/μm
3
氧化槽深度DT/μm
0.6
漂移区N型掺杂浓度ND/(1014 cm–3)
5
衬底P型掺杂浓度Psub/(1014 cm–3)
4
阱区P型掺杂浓度Pwell/(1016 cm–3)
6
表2新型SOI LDMOS器件仿真最优参数 Table2.Simulation optimal parameters for novel SOI LDMOS devices.