1.School of Physics and Electronics, Central South University, Changsha 410083, China 2.Hunan Province Engineering Technology Research Center in Novel Chip Inductance and Advanced Manufacturing Equipment, Huaihua 419600, China
Fund Project:Project supported by the National Key Research and Development Program of China (Grant No. 2017YFA0204600), the National Natural Science Foundation of China (Grant No. 61404002), and the Fundamental Research Funds for the Central Universities of Central South University, China (Grant No. 2018zzts344).
Received Date:25 November 2018
Accepted Date:24 January 2019
Available Online:01 March 2019
Published Online:05 March 2019
Abstract:In recent years, amorphous InGaZnO thin-film transistor (InGaZnO TFT) has attracted intensive attention. Due to its high mobility, low off-state current, and excellent uniformity over large fabrication area, the InGaZnO TFTs promise to replace silicon-based TFTs in flat panel displays, optical image sensors, touch sensing and fingerprint sensing area. The on-state performances of InGaZnO TFT are used in thin film transistor liquid crystal display, active-matrix organic light emitting display, etc. Consequently, numerous on-current models have been proposed previously. However, for lots of the emerging sensing applications such as optical image sensors, the leakage current of InGaZnO TFTs is critical.Previous literature has shown that the leakage current generation mechanisms in TFTs include trap-assisted thermal emission, trap-assisted field emission, inter-band tunneling, and auxiliary thermal electron field emission containing Poole-Frenkel effect. However, up to now, there has been few reports on the leakage current model of InGaZnO TFT, which hinders further the development of emerging applications in InGaZnO TFTs for sensor and imagers integrated in display panels.In this paper, the leakage current model of InGaZnO TFT is established on the basis of carrier generation recombination rate. The feasibility of the proposed model is proved by comparing the TCAD simulations with the measured results. In addition, the influences of geometrical parameters on the leakage current of InGaZnO TFT, i.e. the channel width, the active layer thickness, and the gate dielectric thickness, are analyzed in detail. This research gives insightful results for designing the sensors and circuits by using the InGaZnO TFTs. Keywords:InGaZnO/ leakage current/ thin-film transistor/ device model
图4给出了不同沟道宽度情况下的InGaZnO TFT的TCAD模拟结果和模型计算结果的对比. TFT的沟道宽度W从200 ${\text{μ}}{\rm{m}}$增大至500 ${\text{μ}}{\rm{m}}$, 泄漏电流随TFT的沟道宽度线性增大. 这与(19)式描述的情况较为符合. 这是因为TFT的沟道宽度W增大导致耗尽区的面积和体积增大, 从而沟道内的感应载流子增多, 致使泄漏电流增大. 由于(19)式中的Lov是指栅漏交叠区域的长度, 因此, TFT的沟道长度与泄漏电流的大小并无关系[29]. 由图5可知, TFT的沟道长度L从50 ${\text{μ}}{\rm{m}}$增大至90 ${\text{μ}}{\rm{m}}$, 在关断区域内漏电流大小增长幅度仅为0.6%. 然而, 在导通区域, 漏电流随着TFT沟道长度L的增大而减小. 该模拟结果表明TFT的沟道长度L对关断区泄漏电流几乎无影响. 图 4 InGaZnO TFT在不同宽度(W = 200, 300, 400, 500 ${\text{μ}}{\rm{m}}$)下泄漏电流与栅源电压的关系 Figure4. Relationship between leakage current and gate-source voltage under different widths of InGaZnO TFT (W = 200, 300, 400, 500 ${\text{μ}}{\rm{m}}$).
图 5 InGaZnO TFT在不同沟道长度 (L = 50, 60, 70, 80, 90 ${\text{μ}}{\rm{m}}$)下泄漏电流与栅源电压的关系 Figure5. Relationship between leakage current and gate-source voltage for different lengths of InGaZnO TFT (L = 50, 60, 70, 80, 90 ${\text{μ}}{\rm{m}}$).
图6为InGaZnO TFT不同栅氧化层厚度$ t_{{\rm SiO}_x}$下模型计算和TCAD模拟的泄漏电流对比图. 可见, 泄漏电流随着栅氧化层厚度$ t_{{\rm SiO}_x} $的增大而减小, 栅氧化层厚度$ t_{{\rm SiO}_x} $从150 nm增大至250 nm过程中, 泄漏电流的值减小了20%. 这与(21)式和(23)式描述的情况一致, 栅氧化层厚度$ t_{{\rm SiO}_x}$增加导致电场强度F减弱, 陷阱态内电子无法获得足够的动力挣脱束缚, 沟道内自由载流子减少, 载流子复合产生率减小. 且在高电场作用下, 栅氧化层厚度$ t_{{\rm SiO}_x} $的增加也会导致器件内隧穿电流减小, 最终亦会导致泄漏电流减小. 图 6 InGaZnO TFT在不同栅氧化层厚度(tSiOx = 150, 200, 250 nm)下泄漏电流与栅源电压的关系 Figure6. Relationship between leakage current and gate-source voltage of InGaZnO TFT with different gate oxide thickness (tSiOx = 150, 200, 250 nm).