1.
Introduction
With the development of CMOS technology, the device is scaling down to sub 20 nm but faces more and more challenges, especially the short-channel effect. Fully depleted silicon on an insulator with an ultra-thin body and buried oxide (FDSOI UTBB) is a viable candidate to continue CMOS scaling especially for the low power application[1]. The channel of UTBB transistors is typically undoped to eliminate random dopant fluctuation (RDF) while achieving superior short-channel control and suppressing the threshold voltage variability[2–4] or altering the channel material improves device performance[5, 6]. Another advantage of UTBB is the possibility of modulating the threshold voltage by using the back biasing. Because of body biasing UTBB MOSFETs, Vt can be adjusted easily. Multi-Vt devices can be achieved and reduce the active and standby power. Due to its ability of adjustment of Vt, low power consumption, less parasitic effects, and more stable performance, the UTBB FDSOI device is receiving increasing attention for application in memory and internet of things (IoT) applications[7–9].
In order to pursue the scalability of thin film devices for future technological generations and to reduce further the coupling effect between source and drain, the use of a thin BOX will become mandatory. So as to be more effective, the thin BOX should be combined with a well implantation that allows the suppression of the depletion extending under the buried oxide and offers an easy way to adjust the threshold voltage by using back biasing[10]. The research shows that the specific well structure can adjust the threshold voltage and DIBL of the device. And in combination with the back biasing, the regulation effect is more effective[11–13]. However, the research on the influence of well structure on the device is not yet complete, especially the influence of well concentration. In this work we focus on the impact of different wells on the device characteristics, and achieve a substantial adjustment of the threshold voltage of the device by optimizing the well structure and the back biasing.
2.
Device structures and simulation method
The structure of devices in this work are shown in Fig. 1. The device parameters are listed in Table 1. Well structure is divided into N and P types, and the well is doped with different concentrations.
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Figure1.
(Color online) Schematics of the different studied architectures.
| Parameter | PMOS | NMOS |
| Length of gate (nm) | 26 | 26 |
| Silicon film thickness (nm) | 6.5 | 6.5 |
| Effect oxide thickness (nm) | 1.4 | 1.4 |
| Concentration of S/D (1020 cm?3) | 1 | 3 |
| Concentration of channel (1016 cm?3) | 5 | 6 |
| Concentration of substrate (1014 cm?3) | 1 (P) | 1 (P) |
Table1.
The parameters of devices.
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| Parameter | PMOS | NMOS |
| Length of gate (nm) | 26 | 26 |
| Silicon film thickness (nm) | 6.5 | 6.5 |
| Effect oxide thickness (nm) | 1.4 | 1.4 |
| Concentration of S/D (1020 cm?3) | 1 | 3 |
| Concentration of channel (1016 cm?3) | 5 | 6 |
| Concentration of substrate (1014 cm?3) | 1 (P) | 1 (P) |
Six types of P and N channel device with different types of well doping are simulated to evaluate the influence of well type on the performance of devices. Then we focus on the ability of threshold voltage adjustment of well concentration and back biasing. The Sentaurus TCAD tools[14] are used to evaluate the devices performance. The gate voltage is directly applied to the upper gate oxide material and the barriers are set to ?0.13 and 0.17 eV for N and P channel MOSFETs respectively to balance the off current. A drift-diffusion model, Oldslotboom bandgap narrowing model, Philips unified mobility model, high field saturation models, and Shockley– Read–Hall (SRH) generation recombination model are used in the simulation. The quantum effect is included by the density gradient method.
3.
Result and discussion
3.1
Influence of well type
The impact of well doping on the performance of UTBB MOSFETs is simulated. Six types of cases are evaluated both for N and P channels including without well, P well, and N well as shown in Table 2. The Ids–Vgs curves of six types of UTBB MOSFETs are shown in Fig. 2. The subthreshold swing (SS) and drain induced barrier lowering (DIBL) are shown in Fig. 3.
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Figure2.
(Color online) Id–Vg characteristics of NMOS and PMOS with different types of well and without well.
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Figure3.
SS and DIBL for NMOS and PMOS with wells and without well.
It can be seen from Figs. 2 and 3 that the impact on different types of devices is different for different types of well. The Vth of N channel MOSFETs with a P well is much higher than the Vth of N channel MOSFETs without a well, and the Vth of N channel MOSFETs with an N well is the lowest of the three types of N channel MOSFETs. In general, when the well doping type is opposite to the channel doping type, the Vth is higher while the opposite is lower. The trend also applies to P channel MOSFETs. The well doping has not caused the degradation of DIBL and SS even certain well doping improves that while changing the Vth. The Vth shift comparing the Vth of devices without well for the six types of devices is shown in the following Table 2.
| Type of device | NMOS w/o well | NMOS with Pwell | NMOS with Nwell | PMOS w/o well | PMOS with Pwell | PMOS with Nwell |
| Vth variation (mV) | 0 | 95 | ?7 | 0 | 6 | ?107 |
Table2.
Threshold voltage shift for the six types of devices.
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| Type of device | NMOS w/o well | NMOS with Pwell | NMOS with Nwell | PMOS w/o well | PMOS with Pwell | PMOS with Nwell |
| Vth variation (mV) | 0 | 95 | ?7 | 0 | 6 | ?107 |
The potential distribution at Vgs = 1.1 V, Vds = Vdd = 0.8 V of the N channel devices (w/o well, with P well, with N well) are shown in Fig. 4. It can be seen that the channel potential of N channel devices with P well is significantly lower than the other two types of N channel devices.
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Figure4.
(Color online) Potential distribution of three type of N channel MOSFETs at Vd = 0.8 V.
The electron density of an N well is about 1018 cm?3 while the hole concentration of a P well is about 1017 cm?3. The hole of the P well is a depletion and leaves the impurity ion, but the N well is not a depletion. Thus the P well’s potential is much lower than the N well’s potential in N channel devices. The well potential is coupled to the channel due to the ultra thin buried oxide. In order to turn on the devices, the impact of the well on the channel potential needs to be overcome by gate voltage so the P well increase the Vth and the N well decreases the Vth for N channel MOSFETs. Because of the BOX the potential of the well, adjust the Vth via the γ[15] as follows:
$gamma = frac{{{ m {EOT}} + displaystylefrac{{{varepsilon _{{ m{SiO}}_{_2}}}}}{{{varepsilon _{{ m{si}}}}}}left( {{X_ { m{bar}}}} ight)}}{{{T_ { m{BOX}}} + displaystylefrac{{{varepsilon _{{ m{SiO}}_{_2}}}}}{{{varepsilon _ { m{si}}}}}left( {{T_ { m{si}}} - {X_ { m{bar}}} + {T_ { m{dep}}}} ight)}}.$  | (1) |
Xbar is the position of the largest carrier density in the silicon film. EOT is the effect of oxide thickness and TBOX is buried oxide thickness. Tdep is the thickness of the depletion layer under the buried oxide. The main reasons for the difference of the γ of devices with different wells are that the well can influence the distribution of channel carriers and the difference of thickness of well depletion. In this work, however, for N channel devices with different wells, the γ does not have much difference. The potential of NMOS with a P well is much lower the potential of NMOS without a well, but the potential of NMOS with an N well is just the same as the potential of NMOS without a well, hence the Vth shift of NMOS with a P well is much higher than for NMOS with an N well. Because of the lower channel potential of N channel MOSFETs with a P well the leakage is reduced. The SS of devices is much lower than for other types of devices. The DIBL is controlled well by a P well. For the influence of a well on P channel MOSFETs, the trend is opposite. For UTBB MOSFETs adding a high doping well contrary to the channel type is the effective method to increase the Vth without the degradation of DIBL and SS.
3.2
Influence well doping concentration
The influence of well doping concentration of a well is evaluated. The simulation results of devices with different concentration wells are shown in Fig. 5.
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Figure5.
(Color online) DIBL, SS, and Vth for NMOS and PMOS with different concentration of well.
It can be seen from Fig. 5 that the characteristics of the devices are mainly influenced by doping polarity. For the MOSFETs with the same type of channel and well doping, the device characteristics are almost the same as the well concentration changes. The ΔSS is about 2 mV/dec while the ΔVth is about 10 mV. The ΔDIBL is about 4 mV/V when the N well concentration is from 1015 cm?3 to 1020 cm?3. But for MOSFETs with the opposite type of channel and well doping, the result is different. When the well is lightly doped, the device characteristics change little; while the well is heavily doped, the device characteristics change a lot. The ΔSS is about 7 mV/dec while the ΔVth is about 110 mV. The ΔDIBL is about 15 mV/V when the well concentration is higher than 1018 cm?3. Taking the N channel MOSFETs for example, because the electrons in the N well are depleted less, the potential of the channel is less affected by the impurity ions in the well and the device characteristics change little with the increasing of N well concentration. However, the holes of the P well are much depleted so that impurity ions can show more quantity of electric charge with increasing of P well concentration. When the P well concentration is 1017 cm?3, the DIBL is increased sharply as Fig. 5(a) shows; this is the reason why a heavily dope P well can obviously influence the channel potential of the channel and the characteristics of N channel MOSFETs. For P channel MOSFETs, the heavily doped N well has the same effect. Only when the well is doped with a high concentration will the well's ability to adjust the threshold voltage be displayed.
3.3
Impact of body biasing
In comparison to classical bulk technology, the UTBB MOSFETs offer a wide and effective range of back basing due to the presence of the BOX layer[16]. As the well of devices can act as a second gate the back basing can adjust the Vth of devices further[4]. The effect of the combination of well doping type and back biasing on the device characteristics is investigated in this part, and the simulation results are shown in Figs. 6 and 7.
As Figs. 6(a) and 7(a) show, the range of back biasing on devices with a well is much wider than the range of back biasing on devices without a well. The Vth of devices with the well varies linearly with the back biasing. The rates of threshold voltage of devices with wells over back biasing are about ?135 mV/V. For NMOS, when the devices were placed in positive back biasing, the threshold voltage of devices without wells keeps unchanged while the threshold voltage of devices with wells is significantly decreased with positive biasing. For PMOS, the result is flipped. That is to say, well structures play a key role in forward body biasing. When the devices were set in back biasing, the impact of the well on the device and the effect of the body bias on the devices are simply overlaid. However, the effect of back biasing would not be shown completely if the devices are used without a well.
Due to the presence of the BOX layer, the back biasing makes the device equivalent to a double-gate structure. The body-biasing is equivalent to the back-gate biasing. This is an effective way to adjust the characteristics of the device by changing the body effect coefficient γ just as Eq. (1). For NMOS with a well, the well type is inversion or accumulation when body-biasing is placed hence the thickness of BOX is equal to the effective thickness of BOX. However, for NMOS without a well, the substrate type is depletion and accumulation respectively when back biasing is positive and negative, so the thickness of BOX is far thicker than the effective thickness of BOX. The γ of NMOS without well are different while the γ of NMOS with well are the same when body-biasing are positive and negative. For PMOS, the effect of the well and back biasing on the devices Vth is the same. As Figs. 6(b), 6(c), 7(b), and 7(c) show, the trend of SS and DIBL is the same. They are affected by the channel potential distribution. For N channel MOSFETs with a well, the channel potential increases linearly by the back biasing increasing, so the DIBL is increased with the increasing of back biasing. However, the leakage current increases exponentially with the potential, so the SS increases rapidly with the increasing of back biasing. For an N channel without a well, when the back biasing is negative the thickness of BOX is equal to effective thickness of BOX. In this situation the device is just the same as the devices with a well, so the SS and DIBL are increasing with the back biasing increasing. However, when back biasing is positive the effective thickness of BOX is much thicker than the thickness of BOX, so the devices are just like UTB MOSFETs. For P channel MOSFETs the effect is opposite. The combination of well doping and back biasing can provide a commendable way to adjust the Vth but change the DIBL and SS.
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Figure6.
(Color online) Vth, DIBL, and SS for N channel MOSFETs with well and without well.
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Figure7.
(Color online) Vth, DIBL, and SS for P channel MOSFETs with well and without well.
4.
Conclusion
The influence of well doping and back biasing on the performance of UTBB MOSFETs devices has been evaluated. For the MOSFETs with heavily well doping that is opposite to channel doping, the threshold voltage of devices with heavy doping is increased by 100 mV compared to devices without a well. The effect of the back biasing on the Vth of devices with a heavily doped well is 100–140 mV/V. The effects of the well on the device and the back biasing on the device are additive. For the MOSFETs with light well doping or well doping opposite to channel doping, the device characteristics change little. However, in the situation where N channel MOSFETS have negative back biasing and P channel MOSFETs have positive back biasing, the back biasing can also show the regulatory role of the devices. Adding a well structure and back biasing is an effective way to adjust the Vth of UTBB FDSOI devices.
