1.
Introduction
Switching power supplies with low power consumption, high efficiency, and miniaturization are ubiquitous in many kinds of adapters currently employed in consumer electronic products[1–3]. Energy Star is a voluntary program that is affiliated with the U.S. Environmental Protection Agency, and it assists businesses and individuals to save money and protect our climate through superior energy efficiency. In July 2013, the U.S. Department of Energy (DoE) elevated the Standards for External Power Supplies (EPS) to a state-of-the-art level, named Energy Star VI, which requires that the average efficiency of such devices exceed 85%, and that the standby power consumption be less than 100 mW. Over the past few years, several well-known international semiconductor companies, including TI, ADI, LTC, ST and Grenergy, have designed related products which can meet the Energy Star VI standard. However, these products have high prices which are similar to those of other ICs imported for the domestic market. At the same time, many semiconductor companies in China have attempted to adopt the bipolar, CMOS and double-diffused MOS (DMOS) (BCD) process to improve the conversion efficiency of switching power supply, which is a trade-off with the production cost.
This paper proposes a high-performance PWM AC/DC controller with a novel UVLO circuit according to the Energy Star VI standard, which is based on a 40-V 0.8-μm 1P2M CMOS technology[4]. The chip area is 1410 × 730 μm2, which is smaller, and costs less than the mainstream products at home and abroad. This work has been mass produced on an industrial scale, and is used in power adapters of portable electronic devices.
UVLO circuits are essential to the operations of modern switching power supplies, and play an important role in achieving high-stability and low standby power consumption. UVLO circuits can monitor power-voltage fluctuations to ensure that a system starts up normally and works steadily[5, 6]. Traditional UVLO circuits require a reference voltage source and a comparator, which makes the structure too complicated and the start-up current too large[7]. In order to overcome the shortcomings of traditional UVLO circuits, this work employs a novel UVLO structure which does not require any additional reference voltage source or comparator. It is realized with the reverse-stability characteristic of a Zener diode. The UVLO circuit has advantages of simple structure, low standby power consumption, high start-up speed, good hysteresis effect and excellent stability.
In Section 2, the architecture of the proposed AC/DC controller is briefly introduced. Section 3 illustrates the design of the novel UVLO circuit, while Section 4 introduces the test results obtained for the overall chip. Section 5 concludes by explaining how the application of the proposed AC/DC controller meets the Energy Star VI standard.
2.
Architecture of the proposed AC/DC controller
Owing to the application of a high voltage and large current, power MOSFETs are mostly fabricated based on the BCD process[8]. Further, for convenience, the controller is also integrated with a power MOSFET[9]. The cost of the BCD process is much higher than that of the standard CMOS process. Therefore, the proposed PWM AC/DC controller was designed individually using an HV CMOS process, which can drive a high-voltage 650-V power MOSFET off chip. By packing the controller and the power MOSFET together, the performance of the system is as good as a fully integrated one. These features make it an ideal design for low-cost applications. It enables the functions of low start-up current, green-mode power-saving operation, supply voltage over-voltage protection and other kinds of protection to prevent the circuit from being damaged owing to the abnormal conditions. Besides, an on-chip 5-V low dropout (LDO), which powers the blocks in the controller, is also integrated. These required functions are achieved on chip, significantly reducing the number of discrete devices in the overall system.
Fig. 1 shows the architecture of the proposed AC/DC controller.
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Figure1.
(Color online) Architecture of the proposed AC/DC controller.
3.
Improved UVLO design
When the switching power supply is powered on, the power capacitor is charged until VDD is equivalent to the turn-on threshold (vddon), and then the controller begins to work. Instantaneously, the VDD voltage may decrease because of the load current, and fall below vddon. If the turn-off threshold (vddoff) is equal to vddon, the controller must be repeatedly turned on and off. In order to ensure the normal operation at the start up moment, vddoff must be much smaller than vddon. The UVLO circuit usually uses a hysteresis comparator to achieve this function. The hysteresis voltage across vddon and vddoff also affects the minimum value of the charging capacitor of the power supply. In practical applications, a large hysteresis voltage can support a small-bulk capacitor to charge the VDD voltage, which costs less than a large-bulk one. Furthermore, UVLO ensures that fluctuations in VDD do not cause damage to the entire system. UVLO shuts down other modules in the system when the VDD voltage drops below vddoff[10, 11].
3.1
Traditional UVLO designs
Many conventional UVLO circuits employ a bandgap to generate a reference voltage, and a hysteresis comparator to compare the reference voltage with a sampled voltage of the supply[12]. The simplified diagram of a traditional UVLO is depicted in Fig. 2[13]. The circuit is composed of sampling resistors, a hysteresis comparator, a feedback loop and an output buffer. VDD is the supply voltage sampled by R1 and R2, which is compared with the external reference voltage (Vref). Then, the UVLO circuit estimates whether VDD reaches the turn-on threshold, and outputs results through the comparator. INV1 and INV2 shape and buffer the output curve of the comparator to increase the drivability of the circuit. The use of MOSFET MP1 as a switch generates a positive feedback loop, which engenders the hysteresis range between two threshold voltages to improve system stability.
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Figure2.
Simplified diagram of traditional UVLO.
Fig. 1 shows that the traditional UVLO circuit requires a reference voltage and a hysteresis comparator. The circuit has characteristics of high-power consumption and a larger start-up current owing to its complicated structure. When the traditional UVLO circuit is applied to the PWM switching power supply, the typical efficiency is only 65% to 70%[13].
3.2
Improved low-power UVLO design
The structure shown in Fig. 3(a) is an improved, simple-structure and low-power UVLO circuit with a single supply from 9 to 30 V. The sampled voltage of VDD was obtained using resistors and Zener diodes. Fig. 3(b) shows the Schmitt trigger in Fig. 3(a), which replaces the hysteresis comparator with a simple digital logic circuit[14]. It can be observed that the threshold voltage (Vth) of MOSFET M3 is utilized instead of the external reference voltage.
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Figure3.
(a) Circuit diagram of improved UVLO. (b) Schmitt trigger.
Fig. 4 is a series of transient voltage waveforms of the UVLO circuit. The supply voltage VDD is a 0–22–0 V triangular curve, which is similar to the chip power-up and power-down processes. When the sampled voltage of VDD (uvlo_det) is less than Vth, M3 is off and uvlo_hys follows VDD. VDD keeps rising until uvlo_det equals to Vth. Then, M3 turns on, resulting in uvlo_hys decreasing to VSS. As the flag signal, the UVLO circuit outputs a low level to make the system start to work. At this time, the value of VDD is the so-called vddon of the UVLO. Simultaneously, M1 is turned on and M4 is turned off, so that the uvlo_det voltage has a 10-V step rise. This process is a commendable method to guarantee the stability of the whole system. As a result, the voltage uvlo_det can still be much higher than Vth, even with VDD depressed by a large load current after system start-up. Therefore, the output of UVLO is not influenced by the fluctuations in VDD. When the triangular curve of VDD decreases continuously, the voltage uvlo_det should be less than Vth again. In addition to M3 turning off, the uvlo_hys voltage increases to VDD. Furthermore, the UVLO circuit should output a high level and turn off the system. This value of VDD is Vddoff during the declining slope of the triangular curve. Utilizing the hysteresis function of the Schmitt trigger in Fig. 4(b), the designed turnover voltage (uvlo_det) corresponding to vddon is higher than Vth and corresponding to Vddoff is lower than Vth, which were named Vth_on and Vth_off, respectively.
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Figure4.
(Color online) Transient simulation of UVLO circuit.
The circuit was designed such that R1 = 2 kΩ, R2 = 522 kΩ, R3 = 2088 kΩ and R4 = 783 kΩ. By ignoring the turn-on resistance (Ron_M1 and Ron_M4) of the switches (M1 and M4), vddon and vddoff are respectively expressed by:
$$begin{split} {v_{{text{ddon}}}}& = frac{{{V_{{text{th}}_{text{on}}}}}}{{R3,, + ,,{R_{{text{on}}_{text{M}}4}}}}({R_1} + {R_2} + {R_3}) + 3U{text{z}} & approx frac{{3.14 times left( {2k, + ,522k, + ,2088k} ight)}}{{2088k}}{text{ + 3}}, times ,5.8 approx 21.328,,left( { m V} ight),end{split}$$  | (1) |
$$begin{split}v_{ m{ddoff}} &= frac{{{V_{{ m{th}}_{ m{off}}}}}}{{R3 + R4}} ({R_{{ m{on}}_{ m{M}}1}} + R_2 + R_3 + R_4) + U{ m{z}}& approx frac{{1.07 , times, left( {522k + 208{ m{8}}k ,+, 783k} ight)}}{{{ m{2088}}k ,+, 78{ m{3}}k}} ,+, 5.8 approx 7.06{ m{5}}left( { m V} ight).end{split}$$  | (2) |
where Uz = 5.8 V, which is set by the reverse stability voltage of the Zener diode, Vth_on = 3.14 V and Vth_off = 1.07 V.
In Fig. 4, the simulation results of vddon and vddoff are 19.8 and 8.09 V, respectively, which have some difference with the calculated values by Eqs. (1) and (2). Furthermore，the proposed UVLO circuit has a larger hysteresis voltage of 11.71 V between vddon and vddoff compared to the traditional one. In theory, the structure of the UVLO circuit is insensitive to the matching performance of R1–R4. The most important error source is the effect of the lot variation on Uz, Vth_on and Vth_off. Taking 10% variation of these parameters into consideration, the hysteresis voltage should vary from 10.5 to 12.9 V approximately.
Given that large bulk resistors cannot be integrated on chip, it has always been challenging to reduce the start-up current. Zener diodes have been proven to be a good alternative. In general, there is only a very small current in the reverse-biased PN junction. This leakage current remains constant until the reverse voltage exceeds a particular value, and then the PN junction suddenly begins to have conduction with large current, which is called breakdown. However, if appropriate precautions are taken to limit the current, the reverse-stability voltage can be used as a very stable reference voltage. Particularly, the reverse-biased current can be fixed at an extremely small value. In the novel UVLO circuit, the small reverse-biased current of Zener diodes limits the maximum value of the start-up current. In the simulation results shown in Fig. 4, the start-up current is measured when VDD = vddon ? 1. The much smaller value of 1.3 μA of the start-up current results in a larger start-up resistor, which can reduce the standby power dissipation. R1, R2 and R3 not only play the role of sampling, but also limit the Zener diodes’ current in order to avoid breakdown.
Fig. 5 is a simulation of the temperature characteristics of vddon and vddoff under different corners of the process. The vertical axis represents VDD in volts, and the horizontal axis represents the normalized temperature with the range from ?40 to 155 oC, where 1 is 25 oC. Because the UVLO circuit has no external reference source, it is difficult for the values of vddon and vddoff to remain constant under varying temperature. It is necessary to make a trade-off between precision and simplification. However, the UVLO circuit is just a start-up circuit which protects the system from destruction owing to fluctuations in VDD. Actually, it is reasonable to reduce the accuracy to realize a better overall system performance. The values of vddon and vddoff shown in Fig. 5 vary around 0.4 V with temperature, and are negligible in high-voltage applications[15].
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Figure5.
(Color online) The temperature characteristics of vddon and vddoff.
3.3
Layout of improved low-power UVLO
The PWM AC/DC controller with the proposed UVLO circuit was fabricated based on a 0.8-μm 40-V 1P2M HV CMOS process. The chip area is 1410 × 730 μm2. Fig. 6 is a microphotograph which shows the position and relative size of the UVLO circuit in the overall layout.
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Figure6.
(Color online) Layout of driver chip.
4.
Test results of proposed AC/DC controller
The PWM AC/DC controller chip employs a system-on-package (SOP-8) package. A simplified 12 V/2 A flyback topology for quick-charge application as the test circuit is depicted in Fig. 7[16].
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Figure7.
Test topology of AC/DC controller.
In Table 1, the system turn-on voltage and turn-off voltage are 19.318 and 8.01 V, respectively, with a hysteresis range of 11.308 V. The start-up current is 2.302 μA. As predicted in Section 3.2, the test result of the hysteresis voltage is 0.402-V lower than the simulation one owing to the lot variation of parameters. Nevertheless, the 11.308-V hysteresis voltage is large enough to support a 1-μF power-charging capacitor (Cvdd in Fig. 7), which is cheaper compared with a 10-μF capacitor in most adapter applications.
Table 1 also summarizes the key indicators of this work compared to commercially available switching power supply products with similar energy efficiency or with similar applications. It can be seen that it achieves larger hysteresis voltage and lower start-up current. Thanks to these advantages, this work’s energy consumption and self-heating effects are extremely low. In addition, GR9230 has the same scheme of separation of the controller and the power MOSFET, which also meets Energy Star VI standard. However, the design of GR9230 is based on a 1P3M process, which has an additional mask layer. Furthermore, the controller chip area of GR9230 is 1.5 mm2, while the area of the proposed system is only 1 mm2. Compared to GR9230, this work performs better and has a lower cost in practical applications.
Table 1 also exhibits the standby power consumption and the average efficiency in the flyback topology shown in Fig. 7. It is quite clear that the average standby power consumption of the PWM AC/DC controller proposed in this work is less than 0.1 W, and the average efficiency reaches 85%. The results are proven to meet the Energy Star VI standard.
| Parameter | This work | GR9230 | ME8109 | PT2263 |
| Process | 1P2M | 1P3M | – | – |
| Die size (mm2) | 1.03 | 1.5 | – | – |
| Topology | Flyback | Flyback | Flyback | Flyback |
| Input voltage (V) | 10–30 | 10–30 | 10–30 | 10–30 |
| Output voltage (V) | ≤ 18 | ≤ 18 | ≤ 18 | ≤ 18 |
| Switching frequency (kHz) | 30~100 | 20~100 | 65 | 65 |
| UVLO hysteresis range (V) | 11.308 | 8 | 5 | 5.2 |
| Startup current (μA) | 2.3 | 2.6 | 5 | 10 |
| Standby power (mW) | < 90 | < 100 | < 100 | > 100 |
| Average efficiency | ≥ 85% | ≥ 85% | < 85% | < 85% |
Table1.
Test results of key indicators.
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| Parameter | This work | GR9230 | ME8109 | PT2263 |
| Process | 1P2M | 1P3M | – | – |
| Die size (mm2) | 1.03 | 1.5 | – | – |
| Topology | Flyback | Flyback | Flyback | Flyback |
| Input voltage (V) | 10–30 | 10–30 | 10–30 | 10–30 |
| Output voltage (V) | ≤ 18 | ≤ 18 | ≤ 18 | ≤ 18 |
| Switching frequency (kHz) | 30~100 | 20~100 | 65 | 65 |
| UVLO hysteresis range (V) | 11.308 | 8 | 5 | 5.2 |
| Startup current (μA) | 2.3 | 2.6 | 5 | 10 |
| Standby power (mW) | < 90 | < 100 | < 100 | > 100 |
| Average efficiency | ≥ 85% | ≥ 85% | < 85% | < 85% |
5.
Conclusion
In this paper, a high-performance PWM AC/DC controller with a novel UVLO circuit is presented, which can drive a 650-V power MOSFET according to the Energy Star VI standard in typical applications of AC/DC adapters in portable electronic devices. This work is based on a 40-V 0.8-μm 1P2M CMOS technology. The key function of the proposed UVLO circuit is realized with the reverse-stability characteristic of a Zener diode. Test results obtained for the turn-on voltage and the turn-off voltage of the UVLO circuit are 19.318 and 8.01 V, respectively, with a hysteresis range of 11.308 V. The high hysteresis voltage makes the power-charging capacitance as low as 1 μF, reducing the production cost. The start-up current is only 2.302 μA, significantly reducing the standby power consumption and improving the start-up speed. The chip area is 1410 × 730 μm2. Furthermore, the controller can be applied in quick-charge applications, which are the most advanced power adapters in the market. The controller has been mass produced on an industrial scale.
