1.
Introduction

In recent years, tunnel field effect transistors (TFETs) have been extensively preferred as a prominent device due to their advantages such as reduced sub-threshold swing (SS), less leakage current (I_OFF) and low threshold voltage (V_t)^[1–4]. Though TFETs have many advantages, the realistic use of the devices has been delayed due to low ON-current (I_ON) and ambipolar behavior. Various techniques have been suggested to improve the device performance^[5]. To boost I_ON without compromising I_OFF, double gate TFETs (DG TFETs)^{[6, 7]}, dual material gate^[8], strain engineering^[9] are employed. It has been reported that TFET with gate–drain overlap suppresses the ambipolar current^[10?12].



Compared to silicon TFETs, various other material configurations such as indium arsenide (InAs) in the entire region^[13] shows better device performance. TFETs with InAs/Si hetero junction have been reported from the perspective of combining the tunneling efficiency of narrow bandgap material TFETs and the high mobility of III–V TFET to improve the device performance^[14]. Moreover, a heavily doped pocket layer in between the source and channel forming a p–n–i–n structure have been reported from the point of reliability improvement^[15].



This paper deals with the study of geometrical parameters, gate length (L_g), gate oxide thickness (t_ox), channel thickness (t_ch), and doping parameters channel doping (N_ch), drain doping (N_d) and source doping (N_s) variations to extract RF parameters, unity gain cut off frequency (f_t), maximum oscillation frequency (f_max), intrinsic gain and admittance (Y) parameters for InAs-based DG TFETs. An asymmetric gate oxide is introduced in the gate-drain overlap and its RF/analog performance is studied, modelled and compared with that of DG TFETs. Section 2 deals with the simulator and simulation methodology. The results and discussions are presented in Section 3 and finally Section 4 provides the conclusion.

2.
Simulator and simulation methodology

2.1
Device description

TCAD simulator from Synopsys^[16] has been used to carry out the simulations. The device structure of InAs DG TFET and DG TFET with gate–drain overlap is shown in Figs. 1(a) and 1(b) respectively. In Fig. 1(b), an asymmetric gate oxide has been introduced in order to create an overlap. The asymmetric gate oxide thickness and the overlap are optimized to have the value of t_ox1 = 8 nm and L_ov = 2 nm. Fig. 1(c) shows the electron barrier tunneling for both DG TFET and DG TFET with gate–drain overlap. This plot shows the rate at which electrons are generated at the source side due to tunneling. From Fig. 1(c) it can be seen that DG TFET with gate-drain overlap has more electron tunneling probability compared to that of DG TFET. In this study gate voltage of 1.8 V is used. Table 1 provides the dimensions of InAs-based DG TFET.






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Figure1.
(Color online) Device structure of (a) InAs-based DG TFET and (b) DG TFET with gate–drain overlap. (c) Electron barrier tunneling for DG TFET and DG TFET with gate–drain overlap.

	Parameters	Nominal value	Range of values
	Gate length Lg (nm)	50	40–60
	Gate oxide thickness tox (nm)	3	1–5
	Channel thickness tch (nm)	10	8–15
	Channel doping concentration Nch (cm?3)	1 × 1016	1 × 1015–1 × 1017
	Drain doping concentration Nd (cm?3)	1 × 1019	5 × 1017–1 × 1020
	Source doping concentration Ns (cm?3)	2 × 1019	8 × 1018–4 × 1019

Table1.
Parameter space of DG TFETs with and without gate–drain overlap.



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	Parameters	Nominal value	Range of values
	Gate length Lg (nm)	50	40–60
	Gate oxide thickness tox (nm)	3	1–5
	Channel thickness tch (nm)	10	8–15
	Channel doping concentration Nch (cm?3)	1 × 1016	1 × 1015–1 × 1017
	Drain doping concentration Nd (cm?3)	1 × 1019	5 × 1017–1 × 1020
	Source doping concentration Ns (cm?3)	2 × 1019	8 × 1018–4 × 1019

The physics section of the device simulator uses doping dependence mobility, effects of high and normal electric fields on mobility and velocity saturation, band-to-band tunneling along with Shockley–Read–Hall recombination model. The tunneling probability of the device can be given as follows using Wentzel–Kramer–Brillouin (WKB) approximation^[17,18],

$${T_{ m {WKB}}} approx { m {exp}}left( { - frac{{4lambda sqrt {2m^*} sqrt {E_{ m g}^3} }}{{3qhbar left( {Delta varPhi + {E_{ m g}}} ight)}}} ight),$$

(1)

where m* is the effective carrier mass, E_g is the bandgap, λ is the screening tunneling length, ΔΦ is the potential difference between source valence band and channel conduction. Eq. (1) relates the tunneling probability with the bandgap. In our simulations, we have used the bandgap for both silicon and InAs.



Figs. 2(a) and 2(b) shows the band diagram of both DG TFET and DG TFET with gate-drain overlap in OFF and ON states, respectively. During OFF state, the potential barrier between source and channel is large and hence no tunneling of charge carriers takes place. Necessary gate bias is applied to turn on the device. During ON state, the width of the barrier reduces due to band bending and causes the electrons to tunnel from source to channel.






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Figure2.
(Color online) Band diagram of DG TFET and DG TFET with gate–drain overlap. (a) OFF state. (b) ON state.




Fig. 3(a) depicts the I_d–V_g characteristics of InAs-based DG TFET and DG TFET with gate-drain overlap. The current value of InAs-based DG TFET that is shown in Fig. 3(a) is calibrated against the published results on InAs-based DG TFETs^[14]. I_OFF of DG TFET with gate-drain overlap is matched with DG TFET to make a fair comparison. The two devices are matched to I_OFF = 29 fA by proper gate work function (WF) tuning. The work function of DG TFET is 4.15 eV and DG TFET with gate-drain overlap are given as WF1 = 4.16 eV, WF2 = 4.2 eV. Since ΔΦ denotes the potential difference between source valence band and channel conduction band there would be concentration gradient existing between these two bands and hence more diffusion of carriers from valence to the conduction band takes place. Fig. 3(b) shows the I_d–V_d characteristic of DG TFET and DG TFET with gate-drain overlap. It can be observed that DG TFET with gate-drain overlap offers more drain current.






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Figure3.
(a) I_d–V_g characteristics of DG TFET and DG TFET with gate–drain overlap with I_OFF matched to 29 fA. (b) I_d–V_d characteristics of DG TFET and DG TFET with gate-drain overlap




Fig. 4 depicts the gate capacitance (C_gg) versus V_g plot for both DG TFET and DG TFET with gate–drain overlap. It can be seen that DG TFET with gate–drain overlap have more capacitance value. This can be attributed to the overlap capacitance present with the gate capacitance as per Eq. (2)^[19].






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Figure4.
Gate capacitance versus gate voltage.

$${C_{ m {gg}}} = {C_{ m {gd}}} + {C_{ m {gs}}},$$

(2)

where the gate–drain capacitance (C_gd) and gate-source capacitance (C_gs) are given as follows,

$${C_{ m {gd}}} = {C_{ m {of}}} + {C_{ m {dif}}} + {C_{ m {dov}}} + {C_{ m {gd,inv}}},$$

(3)

$${C_{ m {gs}}} = {C_{ m {of}}} + {C_{ m {sif}}},$$

(4)

where C_of is the outer fringing capacitance, C_dov is the drain-overlap capacitance, C_gd,inv is the inversion capacitance, C_dif and C_sif are the inner fringing capacitances at the drain and source sides respectively.

2.2
Simulation methodology

In this study, sensitivity analysis on the geometrical and doping parameter variations of DG TFET and DG TFET with gate-drain overlap is carried out. The sensitivity analysis can be performed by varying one parameter at a time and keeping all other parameters as a constant quantity. These parameter variations correspond to ± 10% (3σ) deviation of the nominal values. The geometrical and doping parameters are considered to be the independent parameters (X) whereas f_t, f_max, intrinsic gain and Y-parameters are the dependent parameters (Y). Sensitivity of Y is done with respect to X as follows^[20],

$${S_{YX}} = frac{{partial Y}}{{partial X}}.$$

(5)

Standard AC simulations are carried out in SDevice for extracting f_t, f_max and Y-parameters. f_t is the frequency at which current gain equals one and it strongly depends on the gate bias. At various gate biases, f_t is calculated and their maximum is taken as f_t.



f_t is expressed as,

$${f_{ m t}} = frac{{mathop gnolimits_{ m m} }}{{2pi mathop Cnolimits_{ m {gg}} }},$$

(6)

where g_m is the transconductance, C_gg is the gate capacitance.



f_max is extracted from AC simulations which is the frequency measured at unity power gain and it is given as,

$$mathop fnolimits_{ m {max}} = frac{{mathop fnolimits_{ m t} }}{{sqrt {4mathop Rnolimits_{ m g} (mathop gnolimits_{ m {ds}} + 2pi mathop fnolimits_{ m t}mathop Cnolimits_{ m {gd}} )} }},$$

(7)

where R_g is the gate resistance and g_ds is the output conductance.



Intrinsic gain is given as the product of transconductance (g_m) and output resistance (R_o). From the saturation I_d–V_g characteristics, g_m is extracted. From I_d–V_d characteristics, R_o is extracted. Both g_m and R_o are extracted at bias point V_dd/2.



Fig. 5 shows the small signal equivalent circuit of TFETs. In the circuit, C_gs and C_gd are intrinsic gate-to-source and gate-to-drain capacitances. C_gse and C_gde are the extrinsic gate-to-source and gate-to-drain capacitances, respectively. R_s, R_d and R_gd are the gate-to-source, gate-to-drain and distributed gate resistances. g_m and g_ds are transconductance and source-to-drain conductance. Time constant τ represents the charge transport delay. Admittance (Y) parameters are extracted from the AC simulations. The Y-parameter matrix can be treated as the combination of real (conductance) and imaginary (capacitance) components. After disregarding the extrinsic parameters from the equivalent circuit, the admittance (Y) parameters can be expressed as follows:






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Figure5.
Small signal equivalent circuit of TFETs.

$$mathop Ynolimits_{11} approx {omega ^2}{R_{ m {gd}}}C_{ m {gd}}^2 + jomega ({C_{ m {gs}}} + {C_{ m {gd}}}),$$

(8)

$$mathop Ynolimits_{12} approx - {omega ^2}{R_{ m {gd}}}C_{ m {gd}}^2 - jomega {C_{ m {gd}}},$$

(9)

$${Y_{21}} approx {g_{ m m}} - {omega ^2}{R_{ m {gd}}}C_{ m {gd}}^2 - jomega ({C_{ m {gd}}} + tau {g_{ m m}}),$$

(10)

$$mathop Ynolimits_{22} approx {g_{ m {gd}}} + {omega ^2}{R_{ m {gd}}}C_{ m {gd}}^2 + jomega ({C_{ m {gd}}}),$$

(11)

where,

$$tau = - frac{1}{{{g_{ m m}}}}left( {frac{{{mathop{ m Im}nolimits} ({Y_{21}})}}{omega } + {C_{ m {gd}}}} ight).$$

(12)

Since τ depends upon g_m and C_gd, which in turn vary with respect to the geometrical and doping parameters, it is a technology-dependent factor.

2.3
Modeling parameters

The RF parameters, f_t, f_max, intrinsic gain and Y-parameters are modelled with respect to the geometrical and doping parameters. The model that specifies the parameters is given as follows^[21],

$$begin{split}Y =& {b_0} + {b_1}{x_1} + {b_2}{x_2} + {b_3}{x_3} + {b_4}{x_4} + {b_5}{x_5} + {b_6}{x_6} & + {b_{12}}{x_1}{x_2} + {b_{13}}{x_1}{x_3} + {b_{14}}{x_1}{x_4} + {b_{15}}{x_1}{x_5} + {b_{16}}{x_1}{x_6} & + {b_{23}}{x_2}{x_3} + {b_{24}}{x_2}{x_4} + {b_{25}}{x_2}{x_5} + {b_{26}}{x_2}{x_6} + {b_{34}}{x_3}{x_4} & + {b_{35}}{x_3}{x_5} + {b_{36}}{x_3}{x_6} + {b_{45}}{x_4}{x_5} + {b_{46}}{x_4}{x_6} + {b_{56}}{x_5}{x_6} & + {b_{11}}x_1^2 + {b_{22}}x_2^2 + {b_{33}}x_3^2 + {b_{44}}x_4^2 + {b_{55}}x_5^2 + {b_{66}}x_6^2,end{split}!!!!!!!!!!!$$

(13)

where x₁ is the gate length, x₂ is the gate oxide thickness, x₃ is the channel thickness, x₄ is the channel doping, x₅ is the drain doping, x₆ is the source doping and Y is the output RF parameters and b’s are the fitting parameters extracted from the model.

3.
Results and discussion

DG TFET and DG TFET with gate-drain overlap are compared for their RF characteristics in both qualitative and quantitative fashion.

3.1
Qualitative study

The geometrical and doping parameters of DG TFET and DG TFET with gate-drain overlap are varied as shown in parameter space to extract f_t, f_max, intrinsic gain and Y-parameters.

3.1.1
Geometrical parameter variations

Variation of f_t against gate length (L_g) is shown in Fig. 6(a). It can be observed from the plot that increasing L_g results in reduced f_t and this is due to reduced g_m. DG TFET with gate–drain overlap offers more f_t compared to DG TFET due to higher values of g_m^[22]. From the plot it can also be inferred that f_max decreases with increasing L_g. As L_g scales down, f_max increases due to reduced channel resistance, C_gd and g_ds. As DG TFETs with gate-drain overlap offers more f_t, the value of f_max will be higher which is evident from the plot.






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Figure6.
f_t and f_max versus geometrical parameters (L_g, t_ox and t_ch).




Fig. 6(b) shows the variation of f_t plotted against t_ox. For lower values of t_ox, higher values of f_t are achieved due to increasing g_m. It is evident from the plot that f_t enhancement is seen in DG TFET with gate–drain overlap as compared to DG TFET due to improvement in g_m. It can also be inferred from the plot that f_max increases with decreasing t_ox. Since inversion layer is formed near the drain, the carriers that are driven from source to channel tend to move towards the drain causing reduction of channel resistance at the source side and providing high f_max^{[19, 23]}. DG TFET with gate-drain overlap offers more f_max due to its enhanced f_t and reduced g_ds.



Fig. 6(c) shows the f_t variation plotted against t_ch. From the plot it can be inferred that increased f_t is obtained for lower values of t_ch. Also it can be observed that DG TFETs with gate-drain overlap shows a gradual decreasing trend whereas DG TFETs shows a flat behavior. This can be reasoned out as for lower values of C_gg, increased f_t is obtained because of the improvement in screening of gate fringing fields^[24]. DG TFET with gate-drain overlap shows better f_t values than DG TFET due to reduced values of C_gg. The output conductance is found to be high for higher values of t_ch. Hence f_max decreases and follows the same trend of f_t for both the devices. This can be same reasons as discussed earlier for the L_g and t_ox variations for the two devices.



Fig. 7(a) shows intrinsic gain variation against L_g. It is evident from the graph that intrinsic gain increases for higher values of L_g. The combined effect of both g_m and R_o decides intrinsic gain and R_o is more dominant compared to that of g_m, which increases with L_g resulting in high gain. It can also be inferred from the graph that DG TFET with gate-drain overlap offers more intrinsic gain compared to DG TFET due to higher R_o for larger values of gate length.



Fig. 7(b) depicts the variation of intrinsic gain with respect to t_ox. It can be observed from the plot that intrinsic gain decreases with increasing t_ox. For lower values of t_ox, g_m is increased whereas R_o gets reduced thereby ultimately increasing the overall intrinsic gain^[25]. The dominant of g_m is more than R_o in DG TFET with gate-drain overlap and hence it offers more gain.



Fig. 7(c) shows the intrinsic gain variation against t_ch. It can be observed from the graph that intrinsic gain increases with lesser values of t_ch. Here g_m is more dominant than R_o and hence gain increases for lower values of t_ch. DG TFET with gate-drain overlap offers better intrinsic gain due improved g_m compared to DG TFET.






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Figure7.
Intrinsic gain versus geometrical parameters (L_g, t_ox and t_ch).




Figs. 8(a)–8(d) shows the admittance (Y) parameters, both real and imaginary, as a function of gate length for both DG TFET and DG TFET with gate-drain overlap. As per Eqs. (8)–(11), Y-parameters depend on g_m, g_ds, C_gs, C_gd and also the operating frequency^{[26, 27]}. The results obtained for Y-parameters can be reasoned with the behavior of all of these parameters. It can be seen from the plot that both real and imaginary part of Y₁₁ decreases due to the combined effect of the frequency, C_gs and C_gd. The real and imaginary part of Y₁₂ and Y₂₁ increases due to the combined effect of g_m, C_gd and the frequency. As L_g scales down, reduced g_ds offers higher values of Y₂₂. It is evident from the plot that DG TFET with gate-drain overlap shows an improvement in both real and imaginary part of Y-parameters.






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Figure8.
Y-parameters versus L_g.




Figs. 9(a)–9(d) shows the variation of Y-parameters for various values of oxide thickness. Both the real and imaginary part of Y₁₁ decreases with increasing t_ox due to decreasing values of C_gd. Decreasing values of C_gd with increasing t_ox results in Y₁₂ improvement. In TFET the inversion layer formed from drain side to source side, causes the C_gd to increase for increasing gate voltage. Hence reduced value of C_gd is obtained for lower V_g and thus C_gd is found to be a dominant parameter in capacitance between gate and inversion layer^[26]. It is evident from the plot that for reducing t_ox, the real part of Y₂₁ increases due to increase in g_m. It can also be observed from the graph that decreased values of C_gd results in lower values of Y₂₂ for increasing t_ox. DG TFET with gate-drain overlap offers better Y-parameter values compared to DG TFET. Generally Y-parameters represent the conductance component in their real part and capacitive component in their imaginary part. Since DG TFETs with gate-drain overlap offers more I_ON compared to that of DG TFETs, they have higher conductance and hence give better Y-parameter values.






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Figure9.
Y-parameters versus t_ox.




Figs. 10(a)–10(d) shows the Y-parameters variation for varying t_ch. It can be inferred from the plot that Y₁₁ has increased values for increasing t_ch due to higher values of C_gd. Lower values of Y₁₂ and Y₂₁ are observed for increasing t_ch for the same above reasons. The combined effect of g_ds and C_gd determines Y₂₂ as per the Eq. (11). From Fig. 10(d), it can be seen that real and imaginary part of Y₂₂ are increasing and hence following the same trend as per the Eq. (11). As discussed earlier, enhanced admittance values are achieved for DG TFET with gate-drain overlap.






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Figure10.
Y-parameters versus t_ch.

3.1.2
Doping parameter variations

Fig. 11(a) shows the variation of f_t against channel doping (N_ch). From the graph it can be observed that f_t remains constant for all levels of channel doping as mentioned in Table 1. This is because the channel is intrinsic. f_max also remains constant for all levels of channel doping. Fig. 11(b) shows the f_t variation with respect to drain doping (N_d). For higher doping concentration, increased f_t is achieved due to higher values of g_m. From Fig. 11(b) it can be observed that f_max is decreasing up to the nominal value and thereafter it starts to increase. f_max not only depends upon the output conductance parameter (g_ds) but also gate–drain capacitance (C_gd) as per Eq. (7). The decreasing values of f_max for lesser values of drain doping are due to the increase in C_gd, which is more dominant compared to that of the output conductance.






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Figure11.
f_t and f_max versus doping parameters (N_ch, N_d, and N_s).




Fig. 11(c) shows the f_t and f_max variation for different values of source doping (N_s). It can be observed that for both DG TFET and DG TFET with gate-drain overlap, f_t increases with increasing N_s due to the effect of both transconductance and total capacitance. f_max increases till the nominal value as specified in Table 1 and thereafter decreases due to the effect of gate resistance. From the graph it is evident that DG TFET with gate-drain overlap offers more f_t and f_max values compared to DG TFET due to improved g_m.



Fig. 12(a) shows the variation of intrinsic gain for various values of channel doping (N_ch). It can be observed from the plot that intrinsic gain remains constant for increasing N_ch for both the devices. Higher intrinsic gain is seen for DG TFET with gate-drain overlap compared to DG TFET due to improved g_m and R_o.



Fig. 12(b) depicts the variation of intrinsic gain against drain doping (N_d). The plot shows a decrease in intrinsic gain for increasing doping concentration of drain. Though g_m increases for increasing N_d, reduced R_o becomes predominant and results in lower values of intrinsic gain. DG TFET with gate-drain overlap structure offers higher values of intrinsic gain.



Fig. 12(c) depicts the variation of intrinsic gain against source doping (N_s). From Fig. 12(c), it can be seen that intrinsic gain for DG TFETs is slightly increasing (and not flat) whereas DG TFETs with overlap shows higher gain values (i.e.) more sensitive to N_s. This is because of more R_o and g_m values for higher values of source doping. For DG TFETs without overlap R_o and g_m values are comparatively lower and hence intrinsic gain is less.






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Figure12.
Intrinsic gain versus doping parameters (N_ch, N_d and N_s).




Fig. 13(a)–13(d) shows the Y-parameters variation for various channel doping concentrations. All the Y-parameters are found to be constant for all channel doping levels as mentioned earlier for both the devices.






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Figure13.
Y-parameters versus N_ch




Fig. 14(a)–14(d) shows the Y-parameters variation for various drain doping concentrations. From the plot it can be observed that both real and imaginary part of Y₁₁ increases because of higher values of C_gd. Reduced Y₁₂ and Y₂₁ values are achieved due to combined effect of g_m and C_gd. Increasing C_gd for increasing N_d provides higher values of Y₂₂. Improved admittance values are seen for DG TFET with gate-drain overlap compared to DG TFET.






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Figure14.
Y-parameters versus N_d.




Fig. 15(a)–15(d) shows the Y-parameters variation for various source doping concentrations. It can be seen from the plot that both real and imaginary part of Y₁₁ increases due to the combined effect of the C_gs and C_gd. As per the Eqs. (10) and (11), Y₂₁ and Y₂₂ depends on C_gd in addition to g_m and g_ds respectively. Y₂₁ depends on both g_m and C_gd, and from Fig. 15(c), it can be seen that Y₂₁ shows a decreasing trend because of both g_m and C_gd. From Fig. 15(d) it can be observed that Y₂₂ increases with N_s since C_gd is more dominant than g_ds and hence the trend is the reverse of what is expected.






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Figure15.
Y-parameters versus N_s.

3.2
Quantitative study

The RF parameters considered in this study are modeled in terms of the geometrical and doping parameters. Multiple regression analysis derived from enter method is carried out using SPSS^[28]. This gives the predicted values of the output RF parameters, which are then compared with the simulated RF parameters. Figs. 16–19 plot the comparison between the simulated and modelled (predicted) values of f_t, f_max, intrinsic gain and Y-parameters for both DG TFET and DG TFET with gate-drain overlap respectively. It can be seen from these graphs that the simulated RF parameters taken into consideration almost match closely with the modelled values. This is evident from the correlation coefficient (r), which equals to unity for all of the extracted RF parameters.






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Figure16.
(Color online) Correlation graph of TCAD values plotted against model values for f_t.






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Figure17.
(Color online) Correlation graph of TCAD values plotted against model values for f_max.






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Figure18.
(Color online) Correlation graph of TCAD values plotted against model values for intrinsic gain.






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Figure19.
(Color online) Correlation graph of TCAD values plotted against model values for Y-parameters.

4.
Conclusion

In this paper we have studied the effect of geometrical and doping parameter variations of DG TFETs and DG TFETs with gate–drain overlap. The geometrical parameters, L_g, t_ox, t_ch along with the doping parameters, N_ch, N_d, N_s are considered in this study. The parameters are varied in and around the nominal value of the devices. RF parameters extracted in this study are f_t, f_max, intrinsic gain and Y-parameters. It can be observed that DG TFETs with gate–drain overlap shows better performance with respect to f_t, f_max and intrinsic gain for all of the geometrical and doping parameter variations. DG TFETs with gate–drain overlap device offers higher value of f_t and intrinsic gain for gate oxide thickness variations. Higher value of f_max is obtained for DG TFETs with gate–drain overlap devices with variations in N_d. In case of Y-parameters, DG TFETs with gate–drain overlap offers better values in terms of Y₁₁ and Y₂₂. The values of Y₁₂ and Y₂₁ are comparatively lower than DG TFETs because of the influence of C_gd along with g_m and g_ds respectively. A numerical model was developed to check the validity of our simulations. The model values are generated for all of the RF parameters and their corresponding correlation coefficients were extracted. It has been found that the simulated and modelled values are approximately the same.