1.
Introduction
Nowadays a wireless body sensor network (BSN) is widely used in human body monitoring such as electroencephalogram (EEG), electrocardiogram (ECG) and wireless capsule endoscope (WCE) applications. The network controller in BSN plays an important role to collect vital data sensed by each node and transmit them to a remote access point, as shown in Fig. 1. It can minimize the energy consumption of the implantable and wearable sensor nodes by concentrating the communication power to one single device. In the versatile network controller, the dual-band transceiver which supports the body channel communication (BCC) and medical implant communication service (MICS) is in use[1–3]. Meanwhile, OOK and BFSK modes are becoming popular in MICS and BCC systems on account of their lower consumption and sufficient data rates[1–6]. It is valuable to implement the BFSK/OOK demodulation circuit in the network controller of MICS and BCC systems.
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Figure1.
(Color online) Unified wireless body sensor network for MICS and BCC system.
In most RF CMOS receivers, low intermediate frequency (IF) architectures are usually used to extract the base-band signal because they combine the advantages of both superheterodyne and zero-IF topologies, while maintaining a good compromise in terms of power dissipation, integration capability and complexity[4, 5]. Aimed at the implementation of low-IF base-band receivers, two key modules should be considered carefully. On one hand, a variable gain amplifier (VGA) is an essential module of IF circuits because the power received from the wireless channel is unpredictable; it should maintain a relatively fixed output for different input signal levels. Especially in the advanced transceivers, a settling-time constraint is necessary to allow high data rates; it makes the conventional closed-loop feedback automatic gain control (AGC) impractical, and a feed-forward AGC is adopted to shorten the settling time.
On the other hand, the low-IF scheme is very sensitive to the image problem. Through the operation of down-converted mixer, both the desired and the image bands are superimposed in the output band. The image signal can be considered as an interference source that needs to be eliminated. Thus, the complex filter becomes an indispensable block in low-IF receivers. Conventionally, Gm–C topology is the most popular selection to implement complex filters for its better frequency response and lower power consumption[3]. In order to satisfy the demand of transferring different data rates in a wireless channel, a re-configurable channel selection filter is necessary with variable center and cutoff frequencies.
To solve the problems above, an improved fully differential demodulation circuit is proposed to deal with the IF signal derived from the dual-band mixers. The main modules include programmable gain amplifiers (PGA) and a Gm–C complex filter. The PGAs are utilized to obtain a faster gain settling time and narrower output dynamic range, thus relaxing the input dynamic requirement of the following circuits. Meanwhile, a complex Gm–C filter with re-configurable center frequencies and channel bandwidths is proposed to improve the image problem. This paper is organized as follows. Section 2 introduces the scheme of the low-IF demodulation circuit. The practical circuits implementation is discussed in Section 3. Section 4 gives the measurement results. Finally, Section 5 draws the conclusions.
2.
Systematic design of low-IF receiver
Based on the requirement of BCC and MICS, BFSK and OOK modulation is employed in this paper[6]. Also the channel bandwidth should be variable to satisfy the demand of BCC mode. Fig. 2 shows the low-IF receiver scheme for dual-band BCC/MICS operation. The LNA and mixer circuits are shared between BCC and MICS systems. The MICS band antenna attached to the skin also functions as an electrode that couples the BCC signal to the human body. Following the dual-band front end, the BCC and MICS signals are down-converted to IF modules.
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Figure2.
The proposed IF circuits in network controller.
In order to assign the IF gain reasonably, the proposed VGA circuit consists of a programmable gain amplifier (PGA) to implement the coarse gain control and a fixed gain amplifier (FGA). The PGAs locate between the mixers and complex filter. They serve as a coarse gain-setting block to ensure that the input signal of the complex filter is not far from its optimal value and thus relaxes the input dynamic range requirement of the filter and FGA. In order to ameliorate the image rejection performance of an adjacent channel, a complex Gm–C filter is applied with re-configurable center and cutoff frequencies for different channel bandwidths. The main function of FGAs is to improve the linearity of the IF signal because the linearity is dominated by the last stage of cascade amplifiers. Finally, a 4-input “quadratic sum” synthesizer is used to convert the analog orthogonal signals into a digitally single channel output.
As described in the specified communication protocols, the receiver should be capable of decoding input signals with power level less than ?95 dBm[1, 2]. Considering a fixed gain of 25 dB of the receiver RF front-end, namely LNA and mixer, the minimum input signal of the IF circuit can be confirmed about ?70 dBm. Thus, the distribution of characteristic parameters of each block is shown in Table 1. After the amplification of PGA, the signal dynamic range is limited to 10 dB, a range small enough to relax the design specifications of complex filter and FGA. Also other key parameters are listed to be the references of circuit implementation.
| Parameter | Value | |
| PGA | Input range (dBm) | ?70 to 0 |
| Gain step (dB) | ?10/0/10/20/30/40/50 | |
| Settling time (μs) | < 5 | |
| Complex filter | Input range (dBm) | ?20 to ?10 |
| Image rejection (dB) | > 30 | |
| Center freq. (kHz) | 250/500/1000 | |
| Bandwidth (Hz) | variable | |
| FGA | Adjustable gain (dB) | 10/15 |
| Output amplitude (mV) | > 500 | |
Table1.
Summarized target specifications of IF blocks.
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| Parameter | Value | |
| PGA | Input range (dBm) | ?70 to 0 |
| Gain step (dB) | ?10/0/10/20/30/40/50 | |
| Settling time (μs) | < 5 | |
| Complex filter | Input range (dBm) | ?20 to ?10 |
| Image rejection (dB) | > 30 | |
| Center freq. (kHz) | 250/500/1000 | |
| Bandwidth (Hz) | variable | |
| FGA | Adjustable gain (dB) | 10/15 |
| Output amplitude (mV) | > 500 | |
3.
Circuits implementation
This section will describe the circuit design consideration of the building blocks, including the gain-variable VGA, the complex filter and the ‘quadratic sum’ demodulator.
3.1
PGA
Conventional AGCs use a closed-loop feedback scheme to settle the desired output signal level. It suffers from a trade-off between response speed and loop stability, which is not suitable for the design requirement of WBSN applications. As a substitution, a feed-forward PGA scheme is adopted because its immunity of trade-off between settling time and stability[9, 10]. The feed-forward PGA is composed of two forward paths, namely the signal path and the control path. In order to adjust the gain of VGA, a feed-forward control path including detector is adopted, illustrated in Fig. 3. The detector detects the amplitude of the input signal and converts it into a control signal to change the gain setting of the VGA. As signal amplifying and signal detection are performed simultaneously, the feed-forward PGA offers a much more rapid convergence of gain when compared with feedback ones. Furthermore, the feed-forward scheme is unconditionally stable as an open configuration.
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Figure3.
Feed-forward AGC.
As shown in Fig. 4, the proposed PGA is composed of one ?10 dB gain amplifier A0, five 10 dB gain amplifiers A1–A5 and six pairs of control switches S0–S5. To speed up the gain-setting time, the coarse gain control consists of a comparator and a digital control logic circuit. The comparator compares input signal Vin with reference voltage Vref and converts the analog input signal into a digital signal. If the amplitude of the input signal is larger than Vref, the output of the comparator is ‘1’, otherwise the output is ‘0’. Based on the output of the comparator, the digital logic circuit generates a control bit to decide whether the corresponding switch in the amplifier stage is on or off. Thus the gain of each stage can be set as 0 or 10 dB. The overall gain of the PGA is determined. Finally, it can provide a series of ?10/0/10/20/30/40/50 dB variable gain.
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Figure4.
Topology of coarse gain control of PGA.
3.2
Complex filter
After proper amplification of the coarse gain-setting, the input dynamic range of the complex filter is compressed into a much narrower one. In this paper, a fifth-order Butterworth Gm–C complex filter is designed to meet the design requirements with some margins, which is shown in Fig. 5. A leapfrog structure is utilized because of its lowest sensitivity and best dynamic range performance[12]. The filter prototype comprises a pair of real filters (Gm, Ci, i = 1, …, 5) and a series of cross-branch trans-conductance amplifiers (±Gmi, i = 1, …, 5). Compared with a single-ended filter, the complex one needs another series of trans-conductance amplifiers (Gm’ = Gm) to form the feedback loop.
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Figure5.
The presented low-IF receiver scheme.
The reconfigurability of the complex filter can be implemented by changing two frequency variables, namely center frequency (f0) and cutoff frequency (fc). It can be derived that:
$${f_0} = frac{G_{{ m m}i}}{{2pi {C_{i}}}},;;;;;i = 1, ldots, 5,$$  | (1) |
$${f_{ m c}} = frac{{{tau _{ i}}{G_{ m m}}}}{{2pi {C_{ i}}}},;;;;;i = 1, ldots ,5,$$  | (2) |
where τi (i = 1, …, 5) are constant depending on the adopted filter. It can be seen that the center frequency f0 can be changed by tuning the transconductance amplifiers Gmi. The cutoff frequency fc can be changed by adjusting the value of Gm (including Gm’). Also the capacitance Ci are chosen to adapt the different bandwidths.
The complex filter can be regarded as an asymmetrical single-band band-pass filter. In the low-IF receiver, it can serve as a signal demodulator aiming at the OOK or BFSK modulation data. According to the designing specifications in Table 1, three kinds of center frequency 250, 500, and 1000 kHz are set, which are half of the signal bandwidth respectively.
3.3
FGA
In general, the large gain range of VGA results in poor linearity. To settle down the trade-off, FGAs with constant gain but good linearity are cascaded after the filter. The schematic is shown in Fig. 6. Differential input Vi+ and Vi? are applied at the gates of source followers M1a and M1b, which are connected in feedback loops with M2a and M2b to form a pair of flipped voltage followers (FVFs)[10]. The FVFs force constant current in M1a and M1b so that nodes X1 and X2 follow Vi+ and Vi? with constant VGS offset. Thus, the current IX through resistor RX is accurately proportional to input voltage Vin. A highly linear trans-conductance Gm = 2/RX can be achieved. Feeding the output current of the trans-conductance amplifier to a load RL would give a constant gain 2RL/RX. In this paper, the gain is designed to be 10 and 15 dB selectively.
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Figure6.
Schematic of FGA.
3.4
Demodulator
The 4-phase “quadratic sum” block is shown in Fig. 7. The IF signals from FGAs are converted into current signals and added together to achieve “quadratic sum” functions[13]. The output current can be expressed as:
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Figure7.
Schematic of the ‘quadratic sum’ block.
$$begin{split}{I_{ m{OUT}}} & = {I_{ m{IN}}} - {I_0} & = {sumlimits_{i = 0}^3 {beta left[ {{V_{ m {in}}} cos ({omega _{_{ m{IF}}}}t + i pi /2) + {V_{ m {od}}}} ight]} ^2}- ,, 4beta V_{ m {od}}^2& = 2beta V_{ m {in}}^2 .end{split}$$  | (3) |
Thus the output current is proportional to the square of the input modulated voltage Vin. Because the IF signal ωIF is naturally removed from the baseband signal, theoretically the scheme can recover the data from any IF signal even if the IF is as low as the signal bandwidth. It can eliminate the adoption of the ADC module in the low-IF receiver. The overall power consumption of analog base-band is reduced on the demodulation modes such as OOK and BFSK, etc.
4.
Measurement results
The fully differential IF circuit is implemented in SMIC 0.18 μm standard CMOS process with supply voltage of 1.8 V. Fig. 8 shows the chip micro-photograph of the IF receiver. The total chip area including pad is about 5.36 mm2.
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Figure8.
(Color online) Micro-photograph of the fabricated IF circuits.
The measured transient waveforms of the BFSK mode are shown in Fig. 9. The displayed signal data rate is 500 kbps with the IF carrier of 1 and 3 MHz respectively. The orthogonal 4-channel signals are listed in the left chart. On account of the limited input ports of the oscilloscope, the output waveform of FGAs (only 3 channels displayed) and the demodulator are given simultaneously in the right chart.
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Figure9.
(Color online) Transient waveforms of BFSK mode receiver.
The measured transient plots of the OOK demodulation mode are shown in Fig. 10. The data rate of the input signal is 500 Kbps with the IF carrier frequency of 1 MHz. The orthogonal 4-channel signals are listed in the left chart, which are input of PGAs. The output waveform of complex filter (3 channels displayed) and the demodulator are given simultaneously in the right chart.
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Figure10.
(Color online) Measured waveforms of OOK mode receiver.
The reconfigurability of the complex filter is shown in Fig. 11. Fig. 11(a) shows the variable center frequencies with a fixed bandwidth, while Fig. 11(b) gives the variable bandwidth with a constant center frequency. To measure IMRR, the filter response at negative frequency can be obtained at the corresponding positive frequency. The only modification is to change the phase sequence of the input signal from (0°, ?180°, ?90°, ?270°) to (0°, 180°, 90°, 270°). Then the gain difference at the specified center frequency point of two phase sequences is measured as an image rejection ratio in Fig. 12. It shows that the IMRR is larger than 30 dB, which is enough for design specifications.
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Figure11.
(Color online) Measured reconfigurability of the tunable complex filter. (a) Variable center frequencies with a fixed bandwidth. (b) Variable bandwidths with a fixed center frequency.
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Figure12.
(Color online) Transfer functions of different working modes.
Finally, the principal characteristics comparison of this work with other IF designs are summarized in Table 2.
| Parameter | Ref. [7] | Ref. [8] | Ref. [14] | Ref. [15] | This work |
| Technology | 0.18 μm dnw | 90 nm | 0.18 μm | 0.18 μm | 0.18 μm |
| Topology | Low-IF | Low-IF/Zero-IF | Low-IF | Low-IF | Low-IF |
| Modulation type | ? | ? | ASK | FSK | BFSK/OOK |
| Current consumption (mA) | 6 (Rx) | 2.1-3 (Filter & PGA) | 1.21 | 2.46 | 9.5 |
| IF frequency (MHz) | 2 | 0.2–6 | 10 | 0.25/0.5/1/2 | 0.5/1/2 |
| VGA control mode | Feedback | ? | Feedback | ? | Feed-forward |
| Input signal range (dB) | ? | ? | 105 | ? | 70 |
| Gain range | 0–60 dB | (0–71)/1 dB | (–10 to 50)/4 dB | ? | (–10 to 50)/10 dB |
| Settling time (μs) | ? | ? | 20 | ? | < 2.8 |
| IMRR (dB) | > 35 | 55 | No function | > 20 | > 30 |
Table2.
Comparisons with other low-IF works.
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| Parameter | Ref. [7] | Ref. [8] | Ref. [14] | Ref. [15] | This work |
| Technology | 0.18 μm dnw | 90 nm | 0.18 μm | 0.18 μm | 0.18 μm |
| Topology | Low-IF | Low-IF/Zero-IF | Low-IF | Low-IF | Low-IF |
| Modulation type | ? | ? | ASK | FSK | BFSK/OOK |
| Current consumption (mA) | 6 (Rx) | 2.1-3 (Filter & PGA) | 1.21 | 2.46 | 9.5 |
| IF frequency (MHz) | 2 | 0.2–6 | 10 | 0.25/0.5/1/2 | 0.5/1/2 |
| VGA control mode | Feedback | ? | Feedback | ? | Feed-forward |
| Input signal range (dB) | ? | ? | 105 | ? | 70 |
| Gain range | 0–60 dB | (0–71)/1 dB | (–10 to 50)/4 dB | ? | (–10 to 50)/10 dB |
| Settling time (μs) | ? | ? | 20 | ? | < 2.8 |
| IMRR (dB) | > 35 | 55 | No function | > 20 | > 30 |
5.
Conclusions
Aiming at the requirement of a dual-band BCC/MICS network controller, critical design considerations of an improved fully differential low-IF base-band circuit for BFSK and OOK modes are presented. The central task is focused on the implementation of IF blocks, including the fast-settling feed-forward PGA, a re-configurable complex filter, and FGAs. The low-IF receiver is designed with the 0.18 μm standard CMOS process. Measurement results are expatiated to verify the feasibility of the design goals.
