1.
Introduction

Self-power supply technology can solve the issues in which the battery-dependent technique suffers from its weight, size and lifetime constraints. In some special applications for security considerations, such as micro implantable medical devices, realization of self-power supply is of great significance. The key to self-power supply technique is harvesting energy from the ambient environment. More fortunately, energy in motion, heat, light, and electromagnetic radiation are inexhaustible and environmentally safe. Among these possible sources, kinetic energy in motion has a relatively high power density and scalability. Moreover, piezoelectric harvesters^[1] are compatible with traditional integrated circuit technology. Its electromechanical conversion characteristics have been widely used in vibration energy harvesting (VEH). A piezoelectric harvester, vibrating at or close to its resonant frequency can be modeled as a sinusoidal current source i_P in parallel with a capacitor C_P and a resistor R_P^[2–4], as shown in Fig. 1. The current can be expressed as i_P(t) = I_P sin (2πf_P t), where I_p is the amplitude of the sinusoidal current and it varies with mechanical vibration, f_p is the frequency with which the piezoelectric harvester is excited. The output of a piezoelectric harvester is a sinusoidal AC signal, which needs to be converted into a DC voltage by rectifiers to supply power for micro electronic equipment. Usually, the output voltage and power of a piezoelectric harvester are low, therefore, a high-performance rectifier is required when slight vibration is excited.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-1.jpg'"
class="figure_img" id="Figure1"/>



Download



Larger image


PowerPoint slide






Figure1.
Equivalent circuit of a piezoelectric energy harvester.




Typical piezoelectric harvesters can provide an energy of 10–500 μW/cm^{2[5, 6]}, which is undoubtedly a serious constraint on the design of a relevant power management interface circuit. Full bridge rectifiers are widely used in commercial applications due to their simple structure and good reliability. But the large threshold voltage loss limits its further application. Meanwhile, the poor extraction capability is also one reason that limits its output power of a piezoelectric energy interface circuit. Most of the charge available from the harvester does not flow into the output at high voltage. The loss in charge due to charging and discharging of C_P limits the maximum power that an interface circuit can extract. For full bridge rectifier, current i_P needs to charge or discharge C_P from – ( V_L + 2V_D) to (V_L + 2V_D) before it flows into the output, where V_D is the voltage drop loss on a diode, as shown in Fig. 2. In order to improve the power extraction capability from piezoelectric harvesters, many efficient interface circuits^{[7, 8]} are put forward, including maximum power point tracking (MPPT)^{[9, 10]}, synchronous charge extraction circuit (SECE)^{[1, 11]} and synchronous switch harvesting on inductor (SSHI)^[12–14]. Among these interface circuits, SSHI circuits have received considerable attentions due to their high extraction efficiency and power efficiency. SSHI circuits are used to optimize the charge flipping of C_P in RLC system by controlling the synchronous switches. SSHI can be classified into two categories: parallel-SSHI (P-SSHI) and series-SSHI (S-SSHI). As Refs. [6, 15] presented, performance of P-SSHI is better than that of S-SSHI, especially when vibration energy is relatively weak.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-2.jpg'"
class="figure_img" id="Figure2"/>



Download



Larger image


PowerPoint slide






Figure2.
Full bridge rectifier and associated waveforms.




Aiming at improving the low power conversion efficiency and poor power extraction capability of a conventional full bridge rectifier, a P-SSHI rectifier with high conversion efficiency is proposed in this paper. Active diodes instead of traditional ones are adopted to reduce voltage drop loss over the rectifying path. P-SSHI is introduced to improve the poor power extraction capability of the proposed rectifier. At the same time, LDO has a large transient output power thanks to the power management unit worked in intermittent mode. The whole energy harvesting system can achieve self-powered supply^{[16, 17]}. This paper is organized as follows: Section 2 mainly introduces the basic principle of the P-SSHI circuit. Section 3 shows the proposed P-SSHI rectifier and IPMU. Simulation results and performance analysis are given in Section 4, followed by a summary of the article.

2.
Circuit structure and operation principle

2.1
Working principle of the P-SSHI rectifier

In order to reduce the loss in charge due to charging and discharging of C_P and improve the power extraction capability of a traditional full bridge rectifier, an SO (switch-only) rectifier^[13] was proposed by Ramadass et al. In Ref. [13], a power switch is connected in parallel with the piezoelectric harvester, the switch turns on for a brief time to reset C_P when current i_P crosses zero. Thus i_P only needs to charge C_P up to V_L before it flows into the output during both half-cycles of the input current. Although SO rectifier can reasonably reduce the energy used to discharge C_P, there are still plenty of charges used to charge C_P up and wasted. P-SSHI rectifiers are successfully proposed and measured by Ramadass et al.^[13] and Aktakka et al.^[16]. By adopting an additional inductor of L_F, P-SSHI rectifiers can greatly improve the power extraction efficiency from the piezoelectric harvester.



Basic schematic diagram and working processes of the proposed P-SSHI circuit are illustrated in Fig. 3. When V_f < V_e < V_L, power switch S₁ is on and D₅ is off in the first branch of the P-SSHI circuit and S₂ and D₆ are off in the second branch. Thus there are no current flows from node e to node f through the P-SSHI circuit, and no current flows to output. Capacitor C_P is charged by i_P until V_e = V_L. At this moment, D₁ and D₄ turn on and current flows to output. At time t_π, when i_P crosses zero and changes direction, C_P is discharged and V_e starts decreasing. D₁ and D₄ are then off. After that, S₁ is off while S₂ is on. Therefore C_P, S₂, D₆, and L_F subsequently form a resonant loop. The resonant loop, including L_F and C_P, helps to flip the voltage across C_P. All the energy stored onC_P is initially transferred to inductorL_F, and then this energy is transferred back to capacitor C_P where the voltage is reversed. Due to the presence of D₆ in the loop, current i_P flows only from e to S₂, D₆, and f. Thus, the flipping procedure automatically finishes after all the energy from L_F is transferred back to C_P without any conditional control circuits. A similar effect occurs in negative half cycle of the transducer current. This process makes full use of the obtained energy and improves the energy efficiency. The above description is of the diode D₁–D₆ as ideal diodes, ignoring the diode conduction drop loss of V_D.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-3.jpg'"
class="figure_img" id="Figure3"/>



Download



Larger image


PowerPoint slide






Figure3.
Basic structure of the P-SSHI rectifier and operational waveforms.




Detecting the zero-crossing point of i_P effectively has a great influence on the performance of the whole P-SSHI circuit. Taking into account commercial prospects of the entire PEH system, the complexity of the whole circuit and the self-power supply, the proposed P-SSHI circuit should detect the current changes every half cycle adaptively. The closing time of the switch should be automatically controlled to match the voltage reversal time to obtain a high flipping efficiency. In Refs. [6, 14], a reference voltage V_ref which is set slightly higher than – V_D of a diode is adopted, helping to detect the zero-crossing point of i_P. Ideally, the LC resonant loop makes the voltage flip on C_P the same absolute value. However, due to the conduction loss of inductor L_F and MOS switches, the flipping voltage can only reach ±V_S, which greatly affects the efficiency of the P-SSHI circuit. In addition, it is necessary to ensure that the total power consumption is less than the harvesting energy to realize the realization of self-powered supply.

2.2
Active diode

Active diodes are widely used to replace traditional PN junction diodes to prevent current backflow and reduce on-resistance of the rectifying path. As shown in Fig. 4, the active diode consists of a PMOS switch and a control comparator^[18]. The source terminal and drain terminal of the PMOS switch are connected to the non-inverting terminal and the inverting terminal of the comparator, respectively. The gate voltage of the MPS is controlled by V_COMP. The comparator-based active diode has the characteristics of an ideal diode. Once the voltage of node A is greater than node B, MPS turns on and turns off otherwise.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-4.jpg'"
class="figure_img" id="Figure4"/>



Download



Larger image


PowerPoint slide






Figure4.
Model of an active diode.




In start-up phase or output voltage of the rectifier V_L is very small, the comparator cannot work normally. An auxiliary bypass PMOS diode (MPBD) in parallel to the active diode is adopted to ensure a safe stare-up of an active rectifier under different conditions. When the output voltage of the rectifier increases slowly and the comparator can operate normally, MPBD is no longer operating and always in a high impedance state. Additionally, effect of substrate leakage current cannot be ignored due to the large size of the MPBD and MPS in the active diode. The proposed bulk regulation circuit ensures the substrate potentials of MPBD and MPS are always connected to the higher of the anode voltage and the cathode voltage, preventing the substrate PN junction generates substrate leakage current.

2.3
Proposed piezoelectric energy harvesting system

Fig. 5 shows the basic block diagram of the interface circuit presented in this paper. Based on 0.18 μm CMOS technology, a simple and efficient P-SSHI rectifier circuit and its power management circuit are designed and verified. The output signal of the piezoelectric harvester is rectified by the full bridge rectifier. The output DC voltage is stored on capacitor C_L. Active diodes instead of traditional passive ones are used thus the voltage loss over the rectifier is some tens of millivolt, which results in a power efficiency of over 90%. In P-SSHI circuit, the control circuit is designed by detecting the zero-crossing point of i_P and the change of inductor current. It can adaptively and precisely control the switch on and off in the P-SSHI circuit. The IPMU with hysteresis comparators works in intermittent mode to ensure the interface circuit has a large transient output power. The output voltage of the rectifier set in the range of 2.2 to 2 V is also to prevent the MOS transistors from breakdown. With P-SSHI circuit, the output voltage range of 2.2 to 2 V may have a lower power efficiency under certain conditions. In these cases, the rectifier still has a large power output and will be analyzed in the following section. The proposed P-SSHI rectifier interface circuit can be self-powered without the need of additional power supply.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-5.jpg'"
class="figure_img" id="Figure5"/>



Download



Larger image


PowerPoint slide






Figure5.
Structure of the proposed interface circuit.

3.
Circuit implementation

3.1
Proposed P-SSHI active rectifier

Fig. 6 presents a high efficiency P-SSHI rectifier circuit. It consists of an active full bridge rectifier and a P-SSHI circuit. The proposed active full bridge rectifier consists of four comparator-based active diodes. Comparators COMP₁ and COMP₂ adopt the same PMOS source input structure. Similarly, comparators COMP₃ and COMP₄ use the same NMOS source input structure. The P-SSHI circuit consists of an inductor L_F, a pair of power switches M_S1 and M_S2, two active diodes D₅ and D₆ and a switch control unit.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-6.jpg'"
class="figure_img" id="Figure6"/>



Download



Larger image


PowerPoint slide






Figure6.
The proposed P-SSHI active rectifier.




At the start-up phase, comparators in active diodes cannot work properly. Thus, the full bridge rectifier is composed of four MPBDs. After active diodes start working, these bypass diode are always in high impedance state. When the rectifier works normally, taking the positive cycle of i_P for an example, the charge of C_P makes voltage V_P keep rising while V_N is declining. When V_P is greater than V_L, comparator COMP₁ outputs low level, and M_SP1 is on. At the same time, V_N is lower than GND, comparator COMP₄ outputs high level, and M_SN2 is on. Thus, piezoelectric energy is transferred to capacitor C_L through M_SP1, C_S and M_SN2 and backflows to piezoelectric harvester.



When current i_P gradually reduces to zero, thus V_P is equal to V_L, then COMP₁ output is high, and M_SP1 turns off, there is no rectifier path at this time. When current i_P changes direction, it firstly charges V_N and discharges V_P. At the same time, since the non-inverting terminal voltage of COMP₅ is greater than the inverting terminal voltage, COMP₅ outputs high level, M_N1 turns on while M_N2 turns off similarly. The zero-crossing point of i_P is precisely detected by comparing V_P and V_N with a reference voltage V_ref. The reference voltage V_ref is set to zero. V_ref should be set to the negative value of the voltage drop across an active diode. The selected V_ref will affect the current detection accuracy of i_P. When V_N is higher than V_ref, Q₂ is low level and the same as Q₁. The switching logic control signals CLK₁ and CLK₂ can be obtained through the two signals Q₁ and Q₂, which reveal the zero-crossing point of i_P every cycle. Then CLK₁ becomes high level and M_S1 turns on. Since V_P is still greater than V_N, M_N1 remains in on state. Thus, a resonant loop circuit of C_P, L_F, M_N1 and M_S1 is generated. All of the energy stored in the capacitor C_P is initially converted into the inductor. When voltage is flipped, the charge in the inductor is shared to capacitor C_P finally. When V_P is gradually discharged equal to zero, M_N1 turns off, and the voltage flipping is completed. It is similar to that of the negative cycle of i_P. The P-SSHI circuit can reduce the loss in charge due to charging and discharging of C_P dramatically, resulting in a good extraction capability of the proposed rectifier.

3.1.1
Design of the clock divider circuit

From the structure of the circuit, NOR gate output frequency is two times the frequency of its input signal. The signal CLK₁ becomes high level, while CLK₂ remains low. Then M_S1 turns on while M_S2 is off when current i_P changes its direction from positive to negative. Similarly, when i_P changes from negative to positive, signal CLK₁ should remain low, while signal CLK₂ changes from low level to high level, thus M_S2 turns on while M_S1 is off. Therefore, a frequency division is needed. Fig. 7(a) is the clock divider circuit and Fig. 7(b) shows the control signals of CLK₁ and CLK₂.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-7.jpg'"
class="figure_img" id="Figure7"/>



Download



Larger image


PowerPoint slide






Figure7.
(a) Clock divider circuit (b) and its associated waves.

3.1.2
Design of the comparators

Taking into account the needs of an actual circuit, comparators used in this paper are shown in Fig. 8. Comparators COMP₁ and COMP₂ adopt the same PMOS source input structure while COMP₃ and COMP₄ use NMOS source input structure. All of the comparators are powered by the output of the rectifier. All transistors are biased in subthreshold region to consume less current. The specific implementation of the proposed comparators, COMP₁ and COMP₃, whose topologies are symmetrical are shown in Fig. 8. Taking COMP₁ as an example, the comparator consists of two pairs of common gate input stages (M_P1, M_P2 and M_P3, M_P4), a current mirror (M_N1, M_N2), a common source inverter (M_P5, M_N4), and a push-pull inverter (M_P6, M_N5). The first stage is common-gate stage structure, which can be compatible with the input signal range of the rectifier circuit. The second stage and third stage are common-source amplifiers to provide high gain and increased output swing. The working principle is: V_in+ remains constant while V_in- increases, the current of M_N2 goes up with the increase of current flowing through M_P2. However, the current flowing through M_P4 keeps constant, thus the gate voltage of M_P4 rises up. The current flow through M_P3 becomes smaller, comparator outputs low. Power switch M_SP1 in Fig. 6 is on. A similar process can be shown when V_in+ is higher than V_in.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-8.jpg'"
class="figure_img" id="Figure8"/>



Download



Larger image


PowerPoint slide






Figure8.
Schematics of comparators used in active diodes.

3.2
Design of the proposed IPMU

Amplitude and frequency of a piezoelectric harvester change with surrounding environment, so the rectifier may not be able to provide stable supply power to the load. In order to meet the requirements of different devices for power consumption, an intermittent power management unit^{[16, 19]} is proposed in this paper. As shown in Fig. 5, the IPMU consists of an oscillator, a hysteresis comparator, a bandgap reference and a low power output cap-less LDO.

3.2.1
Design of the proposed hysteresis comparator

Fig. 9(a) shows the proposed hysteresis comparator^[20]. PMOS transistors, M_P2 and M_P3, form a latch. M_P1 and M_P4 are used to reset the latch. When signal S3 is low, M_P1 and M_P4 are on, M_N5 and M_N6 are off, nodes B and C are pulled up to a high level. The process is equivalent to a reset action. In the latch comparator, the input voltage V_A and the reference voltage V_ref1 determine the current magnitude of M_N3 and M_N4. When V_A is greater than V_ref1, current flow through M_N3 is larger than that of M_N4, node B is quickly pulled down to a low level while node C is pulled up to a high level by M_P3, so as to achieve the function of a comparison.



When V_L ranges from 2 to 2.2 V, V_OUT1 remains low level while S4 is high level. Thus V_L is sampled and divided by capacitors C₁, C₂ and C₃. The gate voltage of M_N1 is V_A = V_LC₁/(C₁ + C₂ + C₃). When V_L is equal to 2.2 V, V_OUT1 becomes high level while S4 becomes low. Then V_L begins to decrease due to the load consumption. When V_L ranges from 2.2 to 2 V, signal S4 remains unchanged. Thus V_A = V_LC₁/(C₁ + C₂). When V_L decreases to 2 V, S4 becomes high level again. We adjust the ratio of C₁–C₃ to set V_L between 2.2 and 2.0 V. The control signals of the comparator are shown in Fig. 9(b). When S1 is high while S2 and S3 are low, V_L is sampled and stored on C₁ and comparator is reset. When S1 is low, the voltage stored on C₁ is divided by C₂ and C₃. After the completion of the share process, S2 becomes high level and the comparator starts to work. When the output of the comparator is set by comparing V_A with V_ref1, a sample signal S3 arrives and V_OUT1 follows with the change of the output signal. The switching frequency of S₁ is set to 100 kHz, which is much higher than the frequency of the piezoelectric harvester. Thus the sampling of signal V_L can be treated as continuous. The use of switched-capacitor voltage divider not only reduces the power consumption of the comparator, but also the area of the layout.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-9.jpg'"
class="figure_img" id="Figure9"/>



Download



Larger image


PowerPoint slide






Figure9.
Schematic of (a) the hysteresis comparator and (b) its control signals.

3.2.2
Design of the bandgap reference circuit

In order to meet the requirements of ultra-micro energy harvesting as well as the power consumption, a bandgap reference circuit^{[21, 22]} was introduced in IPMU, as shown in Fig. 10.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-10.jpg'"
class="figure_img" id="Figure10"/>



Download



Larger image


PowerPoint slide






Figure10.
Schematic of the proposed bandgap reference circuit.




The reference consists of a start-up circuit, a bias circuit and a bandgap reference core circuit. The design of the start-up circuit can quickly generate a bias current to solve the degenerate operating point in the reference circuit. Once the core circuit reaches a stable state, the start-up circuit turns off automatically. In the reference core, the cascade amplifier senses V_A and V_B such that node A and B settle to approximately equal voltages. The reference voltage is obtained at the source terminal of M_native. Hence a reference voltage of

$${V_{ m {ref}1}} = {V_{ m {BE}2}} + frac{{{V_{ m T}}left( {ln ;n} ight)}}{{{R_3}}}left[ {{R_2} + {R_3} + 2left( {{R_4} + {R_5} + {R_{ m trim}}} ight)} ight].$$

(1)

With a PTAT (proportional to absolute temperature) voltage and a CTAT (complementary to absolute temperature) voltage, a temperature independent bandgap reference can be obtained. Moreover, for better TC and more accuracy, trimming resistors R₆, R₇ and R₈ are utilized.

3.2.3
Design of the cap-less LDO

Due to the low accuracy and large ripple of the output voltage of the proposed rectifier, a low dropout linear regulator (LDO) is designed to obtain a high precision and low ripple DC voltage. Traditional LDOs need a large off-chip filter capacitor to achieve a very small output voltage ripple and ensure the stability of the system. But it is not conducive to integration. Therefore, to perfect the harvesting system, an output cap-less LDO^{[23, 24]} is adopted as a power management circuit to regulate the output of the rectifier, the simplified structure is shown in Fig. 11. The proposed LDO reduces the filter capacitor size dramatically, and it can also be integrated.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-11.jpg'"
class="figure_img" id="Figure11"/>



Download



Larger image


PowerPoint slide






Figure11.
Structure of the proposed cap-less LDO.

4.
Simulation results and analysis

The proposed design, which consists of a P-SSHI active rectifier and an IPMU, has been designed, implemented and simulated in a 0.18 μm CMOS process. The corresponding open-circuit voltage amplitude of the piezoelectric harvester was 2.0 V for this simulation. The working frequency is 225 Hz for a commercial use. The simulated power consumptions of the proposed interface circuit are analyzed firstly. Then simulation results of the P-SSHI active rectifier are given and followed by the function of the IPMU.

4.1
Power consumption

The design consists of an active full-bridge, a P-SSHI circuit and an IMPU. The following power consumption is measured at the output V_L of 2 V. The active full-bridge rectifier consists of four active diodes AD₁–AD₄, each active diode dissipates a bias current of 200 nA, and the power loss is 1.6 μW. The P-SSHI consists of four comparators COMP₅– COMP₈. COMP₅ and COMP₆ consume a very small current since they have no requirement on performance. To assure a high detecting resolution and speed, COMP₇ and COMP₈ need a large current. But they are only needed to work when i_P reduces to zero-crossing point, so its average current over the entire period is also small. The average current consumption of the P-SSHI is 175 nA, and the power loss is 0.35 μW. The IMPU consists of an oscillator CLK, a hysteresis comparator HC, a voltage bandgap reference BGR and a LDO. The BGR consumes a current of 0.4 μA. The total current loss of the IMPU is 0.8 μA. The simulated current consumptions of the stages are listed in Table 1.

Stage		Value (μW)
P-SSHI	COMP5–COMP8	0.35
Active-full bridge	AD1–AD4	1.6
IMPU	CLK, HC, BGR, LDO	1.6
Total power loss		3.55

Table1.
Overall power consumption of the interface circuit.



Table options
-->


Download as CSV

Stage		Value (μW)
P-SSHI	COMP5–COMP8	0.35
Active-full bridge	AD1–AD4	1.6
IMPU	CLK, HC, BGR, LDO	1.6
Total power loss		3.55

4.2
Simulation results of the proposed P-SSHI active rectifier

The performance of the rectifier has a great influence on the function and efficiency of the whole energy harvesting system. The simulated voltage waves across C_P of the proposed P-SSHI rectifier with an 820 μH inductor is shown in Fig. 12.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-12.jpg'"
class="figure_img" id="Figure12"/>



Download



Larger image


PowerPoint slide






Figure12.
(Color online) Flipping efficiency of the proposed P-SSHI rectifier.




As the wave shows, voltage V_F across C_P is naturally inverted, the flipping efficiency of the circuit is given as Eq. (2)

$${eta _{ m F}} = frac{{{V_{ m F}} + {V_{ m L}}}}{{2 {V_{ m L}}}} times 100% .$$

(2)

From the Eq. (2) and the simulation results, we can easily obtain the flipping efficiency of over 80%. The current detecting accuracy of i_P is less than 6 μA, very close to the zero-crossing point of I_P. The maximum output power that the full-bridge rectifier can obtain is given by Eq. (3)

$${P_{ m {REC}}}left( {max } ight) = {C_{ m P}}{left( {{V_{ m P}} - 2{V_{ m D}}} ight)^2}{f_{ m P}},$$

(3)

where V_P = I_P/ω_PC_P. This is achieved at V_L = V_P/2 – V_D. From Eq. (3), the drop loss V_D has a great influence on the output power of the rectifier.



Fig. 13 is output power comparison between the proposed rectifier and a traditional one. As the figure shows, for a traditional full bridge with V_D = 0.4 V, the maximum output power is 5.8 μW at V_L of 0.6 V. The maximum output power is 13.3 μW and V_L of 0.94 V the proposed active full-bridge rectifier can obtain. Thanks to the active diodes reducing the voltage drop loss on the rectifying path, the maximum output power of the proposed active full-bridge rectifier is 2.3 × that of a traditional one. In addition, a traditional full-bridge with P-SSHI achieves an output power of 34.24 μW at V_L of 2 V. The proposed active P-SSHI rectifier can achieve an output power of 44.4 μW at V_L of 2 V, the increase is 30% compared to a traditional P-SSHI rectifier. Even though the effect of P-SSHI cannot be fully released, the output power of the proposed P-SSHI rectifier at V_L of 2.0 V is much greater than the maximum output power that an active rectifier or a traditional one with P-SSHI can obtain. Both active diodes and P-SSHI help to improve the output power of the proposed rectifier.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-13.jpg'"
class="figure_img" id="Figure13"/>



Download



Larger image


PowerPoint slide






Figure13.
(Color online) Simulated output power of the proposed P-SSHI rectifier.

4.3
Simulated results of the proposed IPMU

The simulation results of reference voltage versus temperature are shown in Fig. 14(a), which shows the TC (temperature coefficient ) of the reference voltage is 25.98 ppm/°C when the swept temperature is ranging from ?45 to 85 °C. Fig. 14(b) is the 200 Monte Carlo simulation results of the bandgap reference on its offset voltage with process and mismatch variations. It can be seen from the histogram that the mean value (μ) of the reference voltage is 1.19239 V with the standard deviation (σ) of 3.96 mV. The coefficient of variation for it is about 0.33%.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-14.jpg'"
class="figure_img" id="Figure14"/>



Download



Larger image


PowerPoint slide






Figure14.
(Color online) (a) Reference voltage versus temperature. (b) 200 Monte Carlo simulation results.




Simulated results of the proposed IPMU are shown in Fig. 15. The output voltage V_L of the proposed P-SSHI rectifier changes relatively slowly when a small input voltage instead of a large one is considered. When V_L rises up to 2.2 V, LDO is used as a followed load stage to consume power and provide a stable and precise output voltage of 1.8 V. Then V_L begins to decline, when V_L drops to 2.0 V, LDO stops working. As the simulation waveform shows, V_L vibrates between 2.2–2.0 V regularly. The power management unit works in intermittent mode can provide a large transient output power for LDO to meet different devices for different power demand.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-15.jpg'"
class="figure_img" id="Figure15"/>



Download



Larger image


PowerPoint slide






Figure15.
(Color online) Simulated function of the proposed IPMU.




Fig. 16 shows the loop stability of the LDO with different load conditions. When the I_load is 1 μA, the phase margin of the loop is 60°. When load current increases to 1 mA, the phase margin of the loop is 80°. The gain bandwidth product of the loop is 500 kHz. The proposed cap-less LDO can ensure the loop stable with different load conditions.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-16.jpg'"
class="figure_img" id="Figure16"/>



Download



Larger image


PowerPoint slide






Figure16.
(Color online) Loop stability of the LDO with different loads.

4.4
Layout

Fig. 17 shows the overall layout of the piezoelectric energy harvesting system. The chip area of is 1.1 × 1.1 mm², and the core area of the rectifier is 0.31 × 0.39 mm². All power switches are isolated from the adjacent circuits by the protection rings. The parasitic parameters of the P-SSHI rectifier have been extracted and process corner models have been considered to obtain more accurate simulation results.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/4/PIC/17030018-17.jpg'"
class="figure_img" id="Figure17"/>



Download



Larger image


PowerPoint slide






Figure17.
(Color online) (a) Layout of the chip. (b) Layout of the core.




A comparison with other reported P-SSHI rectifiers is summarized in Table 2. The FOM is defined as the ratio of the maximum output power of the proposed rectifier and that of the traditional full-bridge rectifier. From the table, only the proposed P-SSHI rectifier and Ref. [13] show a CMOS integration and performance enhanced at the same time. In Ref. [13], the maximum output power the introduced rectifier with an 820 μH inductor can obtain is 47 μW, which is 4× greater than that of the full bridge. An interface circuit with good performance and load independent has been proposed in Ref. [17]. However, it is based on discrete devices and not good for the system integration. Moreover, when the open-circuit voltage of the piezoelectric transducer is less than 10 V, its conversion efficiency will be very low. So it is not applicable to low voltage and low power devices. In Ref. [27], a flipping efficiency as high as 94% is obtained, however, some external devices are needed to adjust the flip timing. The output power of the proposed P-SSHI rectifier with an 820μH inductor is 44.4 μW at V_L of 2.0 V. Taking the conventional full-bridge rectifier as a common reference, the proposed rectifier can improve the harvested energy by up to 7.7× compared to the conventional full-bridge rectifier.

Parameter	Process	IP (μA)	CP (nF)	fP (Hz)	ηF	PO (μW)	FOM: PO/PFB
Ref. [13]	0.35 μm CMOS	63	12	225	75% (LF = 820 μH)	47	4 ×
Ref. [14]	Discrete	63	18	225	—(LF = 940 μH)	48	5.8 ×
Ref. [17]	Discrete	1000	220	50	> 80% (LF = 1 mH)	—	3 ×
Ref. [25]	CMOS	80	26	200	70% (LF = 400 μH)	71	4.5 ×
Ref. [26]	Discrete	80	12	200	68% (LF = 22 μH)	120	3.6 ×
Ref. [27]	0.35 μm CMOS	14	9	229	94% (LF = 3.3 mH)	8.19	4.4 ×
This work	0.18 μm CMOS	50	17.5	225	> 80% (LF = 820 μH)	44.4	7.7 ×

Table2.
Performance comparison of the reported designs.



Table options
-->


Download as CSV

Parameter	Process	IP (μA)	CP (nF)	fP (Hz)	ηF	PO (μW)	FOM: PO/PFB
Ref. [13]	0.35 μm CMOS	63	12	225	75% (LF = 820 μH)	47	4 ×
Ref. [14]	Discrete	63	18	225	—(LF = 940 μH)	48	5.8 ×
Ref. [17]	Discrete	1000	220	50	> 80% (LF = 1 mH)	—	3 ×
Ref. [25]	CMOS	80	26	200	70% (LF = 400 μH)	71	4.5 ×
Ref. [26]	Discrete	80	12	200	68% (LF = 22 μH)	120	3.6 ×
Ref. [27]	0.35 μm CMOS	14	9	229	94% (LF = 3.3 mH)	8.19	4.4 ×
This work	0.18 μm CMOS	50	17.5	225	> 80% (LF = 820 μH)	44.4	7.7 ×

5.
Conclusion

A power-enhanced P-SSHI active full-bridge rectifier for piezoelectric energy harvesting has been designed, fabricated in SMIC 0.18 μm standard CMOS technology and simulated. The active diodes instead of traditional PN junction diodes are utilized in the rectifier, the voltage drop loss on the rectifying path is only tens of millivolts, and thus a higher power conversion efficiency is obtained. The maximum output power of the proposed active rectifier is 2.3× that of a traditional rectifier. A P-SSHI circuit is also adopted to improve the poor power extraction capability of the rectifier. The proposed P-SSHI circuit can detect the zero-crossing point of current i_P precisely. The flipping efficiency of the proposed P-SSHI circuit is superior to 80%. The proposed P-SSHI rectifier can improve the harvested energy by up to 30% compared to a traditional rectifier with P-SSHI. The IPMU ensures a large transient power for the followed circuit LDO. A stable and precise voltage of 1.8 V is obtained at the output of the cap-less LDO. The proposed P-SSHI rectifier can be self-powered without any additional power supply. The size of the layout is 1.1 × 1.1 mm².