1.
Introduction
Ultra-wideband (UWB) technology has attracted extensive attention since it was released by the U.S. military for civilian use in 2002. The abundant spectral resource makes it a good candidate for high-data-rate applications, but only within a short range because of its limited power emission for multi-radio compatibility. It is more efficient compared to the existing Wi-Fi technique and the emerging standards at the 60-GHz frequency band, where the former requires a high-linearity power amplifier (PA) and the latter requires a high-power PA. In standards such as IEEE 802.11ad[1], the 60-GHz PA should deliver both high power and high linearity to support complex modulation and overcome oxygen absorption at the 60-GHz band. Designing such PAs is not a trivial task, and they are far from efficient.
The UWB technique, although it has no dominant standard for now, is usually categorized into multiband orthogonal frequency-division multiplexing (MB-OFDM) and the impulse radio scheme (IR-UWB). MB-OFDM UWB, which was once actively pursued by industry, divides the frequency into 528-MHz bandwidth sub-bands, and shares a similar coding scheme with the 802.11 standards. It was widely implemented to achieve a 480 Mbps data rate[2–5] with over 237 mW/ 284 mW power consumption for the transmitter/receiver. Although MB-OFDM UWB can follow the evolution path of the 802.11 standards family to achieve higher performance, the high power consumption impedes its widespread adoption. IR-UWB, which employs short pulses to utilize the wideband spectra, usually shows good energy efficiency for low- to medium-data-rate applications[6–9] using the 3.1–5 GHz frequency band. Most IR-UWB transmitters employ a simple modulation scheme such as on-off keying (OOK)[6, 7], pulse position modulation (PPM)[8], and bi-phase modulation (BPSK)[9, 10], or their combinations to reduce the spectral lines[11]. The way toward higher data rates has been pursued by utilizing more spectral resources (e.g., utilizing the 6–10 GHz frequency band[12, 13] or the entire 3.1–10.6 GHz band[14]). A higher-order modulation scheme could be another resort for IR-UWB to achieve higher data rates in a given spectrum, avoiding the severe inter-symbol-interference (ISI) faced by high-rate pulse-based transceivers, as in Refs. [12–14].
This study explored a high-data-rate integrated IR-UWB transceiver using the offset quadrature phase-shift keying (O-QPSK) modulation scheme. The proposed transceiver features direct phase multiplexing O-QPSK modulation to enhance the data rate and energy efficiency. The digital modulator with direct phase multiplexing shows extendibility toward higher-order phase modulation with little power and hardware overhead. Energy-efficient wideband circuit techniques further help to achieve low power consumption.
2.
Transceiver architecture and system overview
Fig. 1 shows a block diagram of the UWB chipset. The design and analysis of the RF chip, including transmitter (TX), receiver (RX), and synthesizer, was the focus of this study. The RX as indicated in the schematic is a direction conversion structure with two quadrature chains. It consists primarily of an LNA, two passive mixers, and VGAs. High-pass filters are inserted after the driving amplifier (DA) and mixers to facilitate the independent bias of the mixers and VGAs and eliminate the accumulated offset voltage. The TX, on the other hand, employs a single mixer. However, it makes full use of the available quadrature phases to implement quadrature phase modulation (QPSK) through direct-phase multiplexing. In practice, the O-QPSK modulator is designed to avoid an abrupt 180° phase transition, relieving the linearity requirement on the PA. Compared to the commonly adopted IR-UWB modulation schemes (i.e., OOK, PPM, and BPSK), this means a direct data-rate boost factor of four or two. The data rate boost from O-QPSK modulation can be instead used to improve link robustness over the systems with OOK/PPM and BPSK modulations, by spreading one-bit information onto two or four pulses to obtain a 3- or 6-dB processing gain. The costs, however, are only the extra digital-capable mapping modulator and slightly expanded multiplexer. The direct-phase multiplexing implementation of QPSK modulation features insensitivity to amplitude imbalance due to the hard limiting amplifier following the multiplexer. It is also flexibly expandable toward even higher orders (i.e., M-ary PSK) as long as phases are available. The pulse generator (PG) produces a spectrally shaped baseband envelope, eliminating the power-hungry high-speed digital-to-analog converter (DAC) and high-frequency low-pass filter (LPF) in a conventional transmitter. Overall, the minimally maintained hardware for a QPSK-capable transceiver helps to achieve good energy efficiency. With energy-efficient wideband circuit design, the overall solution is even more attractive.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-1.jpg'" class="figure_img" id="Figure1"/>
Download
Larger image
PowerPoint slide
Figure1.
(Color online) QPSK transceiver schematic.
The intermediate frequency (IF) of the 3–5 GHz receiver is up to 1 GHz, requiring the analog-to-digital (ADC) sampling rate to be 2 GHz according to Nyquist sampling theory. Thus, the ADC power dissipation is prohibitively high with full resolution. The quadrature analog correlation (QAC) receiver[15], which shifts the correlation from the digital domain to the analog domain for reducing the ADC sampling rate to the pulse repetition frequency (PRF), is not optimal for our system, for the following reasons. First, the sampling rate reduction is one to two orders or more with a QAC structure for a low-rate system (such as 20 Mpulses/s in Ref. [16]), but much less for our intended high-rate system with a 500-MHz PRF or even higher. Second, the analog correlation circuit, usually implemented as a simplified template windowed integrator, could exhibit high power consumption for sustaining a high PRF. Furthermore, under the high-PRF condition, a small misalignment between the narrow-duration template and incoming narrow pulses will induce greater signal-to-noise ratio (SNR) degradation, whereas the room to increase window duration to overcome the concern is small because of the minor time interval between pulses. To circumvent the heavy power dissipation associated with the high sampling rate and high-resolution ADC in the DC IR-UWB receiver, low-resolution ADCs are preferred. The bit-truncated ADC degrades system SNR, e.g. 3.5 dB for the extreme 1-bit case in standard UWB communication channels[17], which then drives the system to reach stricter requirements on the noise figure (NF) and local oscillator (LO) integrated phase noise. Those arrangements result in significant power savings on the companion based band chip (BBIC), including the ADC and following digital back end. However, the low-resolution ADC would make carrier offset correction difficult in the digital domain. Thus, an analog offset compensation solution is attractive[18]. In this work, it is fulfilled by a sigma-delta modulator (SDM)-based fractional phase-locked loop (PLL). The quadrature reception enables the frequency offset and direction detection[15]. The BBIC performs the assessment and sends an adjustment code to the SDM PLL of the RX chip to complete the compensation during the preamble of each packet.
3.
Transmitter
Fig. 2 presents the details of the O-QPSK modulator. It is purely implemented with logic gates, including inverters, NAND gates, and NOR gates. The analog methodology, rather than a digital synthesized circuit to implement them as in Ref. [19], accommodates a high-speed clock for high-data-rate applications. Proper phase mapping, as shown in Fig. 2, was performed to achieve the O-QPSK constellation diagram. The separate NOR gate and NAND gate generate the complementary signals
m {and}}, ,overline {SX} $
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-2.jpg'" class="figure_img" id="Figure2"/>
Download
Larger image
PowerPoint slide
Figure2.
(Color online) O-QPSK modulator.
Fig. 3 shows the remaining blocks of the TX. It includes a tunable PG, mixer, and PA. The PG makes use of two offset-delayed CLK signals and a NOR gate to generate the pulse, where tuning is performed by controllable current-starved inverters. The pulse width is adjustable from 0.6 ns to 4 ns with a rectangle- and trapezoid-like shape, projecting the sinc-shaped spectrum with 12–16 dBc sidelobe rejection. A passive single balanced mixer was adopted to accommodate the high swing envelope signal; input-grounded dummy switches help to reduce the LO leakage. The PA stage adopts a source follower to match with the output transmission line and antenna. Furthermore, the capacitor cross-couple (CCC) technique was employed to overcome gain and swing limitations imposed by the static current of the source follower. Further analysis on its benefits are provided in the LNA and the down-conversion mixer sections because they share the same working principle.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-3.jpg'" class="figure_img" id="Figure3"/>
Download
Larger image
PowerPoint slide
Figure3.
Transmitting chain.
4.
Receiver
4.1. Low power UWB LNA
As the first block of the receiver, the LNA must provide a low NF, sufficient gain (s21), and well-matched input impedance (s11) across a wide frequency band under power-consumption and die-area constraints. To meet those design targets simultaneously, this LNA utilizes a common-gate amplifier with inductive load as the first stage for wideband input matching, and a cascade common-source amplifier with another inductive load as the second stage. Two cascaded inductive-peaked stages and the associated stagger tuning help to widen the bandwidth of the LNA.
Fig. 4 shows the detailed circuit implementation[20]. High-Q Metal–Insulator–Metal (MIM) (contributing negligible noise) CCC capacitors (C3 and C4) boost the effective transconductance of the input stage to reduce the NF and the power consumption. To reduce the power consumption even more drastically, the second stage is DC-stacked with the first stage through inductor L1 (L2). Leveraging those circuit techniques, the proposed LNA can achieve wideband input matching, flat gain response, and a low NF as well as low power simultaneously.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-4.jpg'" class="figure_img" id="Figure4"/>
Download
Larger image
PowerPoint slide
Figure4.
(Color online) LNA (a) schematic and (b) wideband operation.
Those inductors used in the LNA help in boosting the gain and bandwidth but usually occupy a large portion of the chip area. To reduce costs, inductors Ls1 and Ls2 are reused from an off-chip balun. Furthermore, inductors L1–L4 are implemented with 4 μm-wide topmost metal (2.17 μm thick), which trades off with the Q for chip area because the wideband application does not require a high-Q inductor. Those customized on-chip inductors are modeled by electromagnetic (EM) analysis software to ensure one-time pass design.
The common-gate amplifier has high isolation intrinsically because its feedthrough is dictated by the transistor’s parasitic Cds, which is usually much smaller than Cgd of the common-source counterpart. The second stage employs a cascode structure to improve the isolation further, preventing LO leakage from manifesting itself at the RX input and improving stability. However, there is still potential instability caused by the parasitic feedback loop from the supply or ground. In this design, the second stage cascade device gate is isolated from the supply through large resistance Rb2-Cas, and then AC-grounded (Cdec) to the same ground as C5 and C6, guaranteeing that the second stage is well referenced to the ground. The loop introduced by Cdec is monitored and well maintained under the safe region, involving controls of ground bondwire inductance, supply and ground decoupling, and cascode node decoupling (Cdec).
4.2. Quadrature down-conversion mixer
As shown in Fig. 5, the mixer of the receiver consists of a wideband CCC transconductance (Gm) stage and double-balanced passive mixer stage. From a system-level view, the IQ double-balance mixer is driven by the shared Gm stage, which saves 50% of the DC current compared to an IQ mixer with separate transconductance stages.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-5.jpg'" class="figure_img" id="Figure5"/>
Download
Larger image
PowerPoint slide
Figure5.
Quadrature mixer schematic.
The CCC technique, which is similar to the one used in LNA, is also employed for the Gm stage to save current consumption further. The DC current of the source follower (M1 and M2) and common source stage (M3 and M4) is reused but the transconductances are finally summed in-phase because their inputs are out of phase. The effective transconductance can be simplified as
m m1}} + frac{{{C_{
m c}}}}{{{C_{
m c}} + {C_{
m gs3}}}}{g_{
m m3}}$
m c}}}}{{{C_{
m c}} + {C_{
m gs3}}}}$
Another capability of this structure is rebalancing the accumulated phase and amplitude mismatch introduced by the preceding components, i.e., the balun, LNA, and their on-board and on-chip interconnections.
ight){
m{ cdot cos}}left( {{w_{
m o}}t}
ight)$
ight){
m{ cdot cos}}left( {{w_{
m o}}t + Delta varphi }
ight)$
$$begin{split}{i_ + } = &{g_{{ m m}1}} cdot {A_0} cdot aleft( t ight) cdot cos left( {{w_{ m o}}t} ight) & +{g_{ m m3}} cdot ({A_0} + Delta {A_0}) cdot aleft( t ight) cdot { m{cos}}left( {{w_{ m o}}t + Delta varphi } ight),end{split}$$  | (1) |
$$begin{split}{i_ - } = & - {g_{ m m2}} cdot ({A_0} + Delta {A_0}) cdot aleft( t ight) cdot cos left( {{w_{ m o}}t + Delta varphi } ight) &-{g_{ m m4}} cdot {A_0} cdot aleft( t ight){ m{ cdot cos}}left( {{w_{ m o}}t} ight).end{split}$$  | (2) |
Assume the transconductance of M1 (M2) and M3 (M4) are matched and equal to gm, then the simplified outputs are:
$$begin{split}{i_ + } = & {g_{ m m}} cdot {A_0} cdot aleft( t ight) cdot cos left( {{w_{ m o}}t} ight) &+{g_{ m m}} cdot ({A_0} + Delta {A_0}) cdot aleft( t ight) cdot { m{cos}}left( {{w_{ m o}}t + Delta varphi } ight),end{split}$$  | (3) |
$$begin{split}{i_ - } = &- {g_{ m m}} cdot ({A_0} + Delta {A_0}) cdot aleft( t ight) cdot cos left( {{w_{ m o}}t + Delta varphi } ight) &-{g_{ m m}} cdot {A_0} cdot aleft( t ight) cdot { m{cos}}left( {{w_{ m o}}t} ight).end{split}$$  | (4) |
Eqs. (3) and (4) clearly show perfect balanced outputs, which proves the CCC Gm stage’s capability to clear the accumulated amplitude and phase mismatch.
4.3. Wideband VGA
Fig. 6 shows the VGA architecture[21] and its key building blocks. In this work, three-stage designs are chosen to trade off among power consumption, gain, and bandwidth. Offset cancellation is also included to prevent it from saturating the VGA output. An extra operational amplifier is added to increase this feedback loop’s open-loop gain to improve the accuracy of the offset cancellation.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-6.jpg'" class="figure_img" id="Figure6"/>
Download
Larger image
PowerPoint slide
Figure6.
VGA and last stage buffer schematic.
On-chip capacitor C1 (C2) coupling interfaced with the mixer output is adopted because the receiver bandwidth is high enough that the low-frequency signal loss from the high-pass filter C1 and R1 (C2 and R2) is more acceptable than the direct conversion receiver in a narrow-bandwidth system. The unit gain cell employs an active inductor to extend the bandwidth, while controlling the gain by tuning the cascade gate bias to meet the gain tuning range specification.
The output buffer also employs CCC to enhance the maximum output swing compared to a conventional source follower buffer, allowing more margin for the loss of the on-board balun, transmission line, and cable for the chipset demonstration system. The final integrated solution does not need this buffer.
5.
Fractional synthesizer
The full synthesizer architecture is depicted in Fig. 1. The SDM input bit length is 19, and the frequency program resolution is ~38 Hz (for a 20-MHz reference frequency, 20 MHz/219 = 38.1 Hz). The integer division ratio is configurable so that the synthesizer can accommodate various reference frequencies. The quadrature LO signal could be implemented as a voltage-controlled oscillator (VCO) combined with a poly-phase filter, two inversely coupled VCOs (i.e. QVCO) and a 2fo VCO with a /2 divider. Considering the intended 0.18-μm CMOS process and power consumption, the QVCO structure is preferable in this work. Although the PA output operates at the same frequency as the QVCO, the pulling effect is small because the PA is designed without inductors and its output bondwires are floorplanned far from the spiral inductor of the QVCO. The QVCO drives separate local buffer chains for TX and RX so that the on-chip routing loss is well compensated from degrading the transceiver’s performance. The synthesizer also includes a /2 divider, which provides the clock for the ADC, which is integrated into the baseband (BB) chip.
The remainder of this section details the key blocks and their design considerations to achieve low integrated phase noise.
5.1. QVCO phase noise suppression
The proposed QVCO, as shown in Fig. 7, employs an NMOS/PMOS complementary VCO core with complementary NMOS/PMOS as an inverse coupling branch. This design is discussed in Ref. [22], but here we put more effort in disclosing the improvement mechanism and practical guidelines to achieve the best phase noise.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-7.jpg'" class="figure_img" id="Figure7"/>
Download
Larger image
PowerPoint slide
Figure7.
(Color online) QVCO schematic.
The current reuse structure, for both NP cross-coupled pairs and the NP quadrature coupling branch, helps to reduce current dissipation, and the fully symmetrical design is advantageous for flicker noise suppression[23]. However, it still shows a corner frequency over hundreds of kilohertz, for which NMOS cross-coupled transistors dominate the contribution. This limits the fractional PLL in adopting a large loop bandwidth to suppress the VCO’s flicker noise contribution, therefore providing less suppression for the out-of-band phase noise introduced by SDM, a dilemma for achieving both good in-band and out-of-band phase noise.
The flicker noise of the NMOS cross-coupled pair can be reduced by increasing the area (i.e., increase the length and width of the NMOS), but this shrinks the tuning range and might cause additional phase noise degradation with a smaller L/C ratio. In the proposed design, the even-harmonic nulling capacitors at the sources of the cross-coupled transistors are adopted to prevent the NMOS transistors’ flicker noise from up-converting into phase noise, rather than reducing the flicker noise itself. The extra capacitors at the sources of M1 and M2 (M5 and M6) can suppress the residual even-harmonic components at those nodes[24]. Mainly because of the reduced second harmonic at the source of those NMOS transistors, flicker noise up-conversion into phase noise at the 1/f 3 region is suppressed.
Fig. 8 shows the Cnull effect on oscillation frequency and phase noise. The Cnull seen from the tank presents negative conductance; therefore, the oscillation frequency should increase after adding the source capacitor[25]. However, the weakened quadrature coupling strength shifts the oscillation frequency in the opposite direction. The combined oscillation frequency variation due to Cnull is desensitized. The maximum frequency shift is ~50 MHz. It can be concluded that the phase noise will improve with the increase of Cnull, but will reach the optimum value when the Cnull is set as ~250 fF. With the optimized Cnull, the phase noise is improved by 5 dB and 14 dB for a 1-MHz and 10-kHz offset, respectively.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-8.jpg'" class="figure_img" id="Figure8"/>
Download
Larger image
PowerPoint slide
Figure8.
(Color online) Simulated oscillation frequency and phase noise at 10 KHz and 1 MHz offset over Cnull sweep.
Figs. 9(a) and 9(b) summarize the noise contribution from the main active devices at 10-kHz and 1-MHz offset, respectively, where fn and id represent flicker noise and channel thermal noise, respectively. From the experiment, we can see that the flicker noise of the NMOS transistors for negative resistance and quadrature coupling contributes 93.4% and 63.8% of the phase noise at 10-kHz and 1-MHz offset, respectively. With the Cnull, the phase noise contributed by the flicker noise of the NMOS cross-coupled transistors and quadrature-coupling NMOS transistors are fully eliminated. This understanding also leads to designs without a harmonic termination capacitor at the sources of the PMOS cross-coupled pair, because the flicker noise of the PMOS transistor is much less than that of the NMOS transistor in the intended 0.18-μm CMOS process. However, because the PMOS becomes more prominent in more advanced CMOS processes, this Cnull can be adopted at the PMOS source using the same reasoning.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-9.jpg'" class="figure_img" id="Figure9"/>
Download
Larger image
PowerPoint slide
Figure9.
(Color online) Active transistors’ noise influence at (a) 10 kHz and (b) 1 MHz offset.
5.2. In-band noise-aware design of PFD/CP
Phase-frequency detection and charge pump (PFD/CP) also critically affect the synthesizer’s performance, especially the in-band phase noise. Its output current noise usually determines the in-band phase noise of the integer-N PLL, and its non-linearity degrades the in-band phase noise by folding the out-band SDM noise into the in-band[26] in SDM-based fractional-N PLL. The degraded in-band phase noise shrinks the optimum loop bandwidth and greatly degrades the integrated phase noise.
In this work, the implemented PFD employs a conventional structure with sufficient delay time to avoid the dead zone, and the subsequent cross-zero region non-linearity in PFD/CP. However, this delay time keeps the CP sink and source both on, and therefore degrades the output current noise. Because both turn-on times ton increase the CP output noise contribution to the in-band phase noise but decrease the PFD non-linearity-caused in-band noise degradation, the optimum ton should be chosen.
Except for the cross-zero non-linearity, the mismatch between sink and source also greatly worsens the in-band phase noise by the same folding effect. Fig. 10 shows the implemented source-switched CP structure. This source-switched CP features smaller clock feedthrough and therefore better reference spur performance. To reduce the CP output noise (both flicker and thermal noise) and current mismatch, the source and sink current (M2 and M3) is required to have a large channel length and channel width-length ratio. This increases the output impedance of the CP, reducing the channel length modulation-induced mismatch. However, the larger channel length pushes the channel width even higher, which degrades the transient current switching and makes the transient sink and source current even more difficult to match with each other. Therefore, the short channel-length M2 and M3 are chosen, but an operational amplifier (OP)-based negative feedback loop[27] is added to adjust the source current for eliminating the mismatch induced by the channel length modulation effect.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-10.jpg'" class="figure_img" id="Figure10"/>
Download
Larger image
PowerPoint slide
Figure10.
(Color online) (a) OP feedback-based charge pump and (b) bias circuit for the OP.
The negative feedback loop consists of the OP, M5 ± M8 formed second stage, and compensation Cc. The unwanted positive feedback loop on the right-hand side is valid only when the sink and source current turn on simultaneously, i.e., at the ton period when the PLL is locked, which corresponds to very small duty-cycle operation (< 1% in this work). In summary, the negative feedback dominates and regulates output current matching accordingly. TheRf and Mfp (Mfn) filter is added to reduce the noise contribution from M6 (M7), the OP, and its preceding current mirror. Mfp and Mfp are NMOS and PMOS capacitors that are referenced to supply and ground, respectively, so that the high-frequency bounce at supply or ground is canceled (between the gate and source of M2 and M3), relieving the phase noise degradation induced by the switching noise coupled from the digital circuit or VCO. The OP is biased through a supply-insensitive constant-Gm circuit with an auxiliary start-up circuit, which consists of only thick-oxide transistors to limit its output flicker noise. The static current matching and output noise performance, considering the entire PFD and CP, are shown in Fig. 11. The simulation shows the static current mismatch is reduced drastically by the OP-based negative feedback (e.g., eliminating the 5% mismatch at the 0.3 V common mode output voltage) while the output noise remains almost unchanged at the concerned offset frequency range (i.e., 1 to 100 kHz).
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-11.jpg'" class="figure_img" id="Figure11"/>
Download
Larger image
PowerPoint slide
Figure11.
(Color online) (a) Simulated current matching and (b) output noise of the charge pump.
5.3. Other parts of the synthesizer and loop bandwidth optimization
In this fractional PLL, a single-loop SDM structure was employed because it shows fewer output levels and less high-frequency quantization noise[28]. The loop filter was a third-order passive RC filter, which was implemented by discrete components. It also provides the flexibility to alter the loop dynamics. The divider chain consisted of an analog current-mode-logic (CML) divider-based 8/9 prescaler and digital counter-based low-frequency divider.
In addition to all the noise reduction techniques, loop bandwidth is also optimized to minimize the overall integrated phase noise. The loop can be described with typical parameters Icp = 200 μA, Kvco = 60 MHz/Hz, and N = 200 for 4 GHz output with 20 MHz reference frequency. The external filter is designed to reach a loop bandwidth of ~180 kHz. The calculated RMS integrated phase noise is 0.35°, corresponding to 0.46 ps RMS jitter.
6.
Experimental results
The prototype chips were fabricated with a 0.18-μm CMOS process. Fig. 12 shows the chip microphotograph. The chip size is 3 × 3 mm2, including the pad ring with electrostatic discharge (ESD) protection circuits. The die was directly attached on an FR4 board, and the pads were wire bonded to on-board traces for the test signals.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-12.jpg'" class="figure_img" id="Figure12"/>
Download
Larger image
PowerPoint slide
Figure12.
(Color online) Chip photograph.
6.1. Synthesizer
Because there was no dedicated output pad for the VCO output, measurements were taken at the /2 divider outputs, which were used as the ADC clock. Therefore, the phase noise measurement accounted for this arrangement, i.e., a theoretical 6 dB was added to extract the fundamental signal’s performance. Measurements were taken when the output frequency was set to 4.025 GHz, resulting from the default integer division ratio of 200 and fraction division ratio of 1/8. Fig. 13(a) shows the phase noise plot under 50 kHz and 160 kHz loop bandwidth, respectively, corresponding to an integrated RMS phase noise (jitter) of 0.78° (1.08 ps) and 0.52° (0.72 ps), where the noise integration was performed by an Agilent 5052B. Optimized loop bandwidth showed a 0.36-ps RMS jitter improvement. The wider bandwidth was limited by the less-attenuated SDM noise and the degraded loop phase margin.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-13.jpg'" class="figure_img" id="Figure13"/>
Download
Larger image
PowerPoint slide
Figure13.
(Color online) Measured (a) phase noise, (b) reference spur, and (c) wideband spurs at fo/2.
Fig. 13(b) also shows a reference spur of –77.2 dBc, which was ensured by the proposed CP. Proper supply partition and substrate guard ring, and sufficient decoupling capacitors, ensured few spurs from cross-talk. The observable tones were located at 500 MHz and 4.025 GHz, for which the former was < –65 dBc and the latter was –31 dBc. The 500-MHz tone originated from the 8/9 prescaler, whereas the 4.025-GHz tone was the second harmonic. Those spurs were worth those efforts because they greatly affect the communication quality itself and compatibility with other radios. For example, a large 500-MHz spur is converted to a receiver passband and greatly spoils the received signal’s quality, and the second harmonic interferes with wireless connections using the 6–10 GHz frequency band.
6.2. Transmitter
The TX is configurable to both BPSK and QPSK modes through the two-bit baseband inputs. Fig. 14 shows the time-domain waveform of the transmitter. It performed well up to the 500-MHz PRF with ~1 ns pulse duration. The transmitter showed ~180 mV peak-to-peak output swing, which includes the output balun (BD3150N50100A00), SMA, and transmission line loss. These results show that the proposed transmitter can support 500-Mbps and 1-Gbps data rates in BPSK and QPSK modes, respectively.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-14.jpg'" class="figure_img" id="Figure14"/>
Download
Larger image
PowerPoint slide
Figure14.
(Color online) Measured waveform at (a) 250 MHz PRF and (b) 500 MHz PRF.
Fig. 15 shows four different simulated overlapped states of the output pulse. Because each state selects one of the quadrature phases, those four pulses show a phase offset of 90° (62.1 ps offset for the 4.025 GHz LO), one after another.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-15.jpg'" class="figure_img" id="Figure15"/>
Download
Larger image
PowerPoint slide
Figure15.
(Color online) Simulated four-states transmitter output pulses with 4.025 GHz LO and 1 ns pulse duration.
Output spectra at the QPSK mode with pulse durations of 1 ns and 2 ns are shown in Fig. 16. Fig. 16 also shows the MATLAB? calculated power spectral density (PSD) of the ideal trapezoidal enveloped pulse train using QPSK modulation. The theoretical result resembles the measurement. Note that the implemented transmitter shows similar spectra for both BPSK and QPSK modulation because it is determined only by the baseband pulse, i.e., shape and duration. The data rate, which is PRF-determined in this work, affects only the spectral amplitude. PSD results of the mathematical model-based BPSK, QPSK, and 8PSK data streams mimicking the output of the implemented transmitter confirm the statement.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-16.jpg'" class="figure_img" id="Figure16"/>
Download
Larger image
PowerPoint slide
Figure16.
(Color online) (a) Measured transmitter output spectrum, (b) simulated spectra with 1 ns and 2 ns pulse width, (c) simulated spectra for pulse train with random BPSK/QPSK/8PSK data.
6.3. Receiver
Fig. 17 shows the receiver noise under a moderate gain setting. It shows a minimum noise figure of 5.2 dB, including the input balun, SMA, and transmission line loss. The input balun is also a BD3150N50100A00 with nominal passband insertion loss of ~0.6 dB and phase imbalance of 3°. The IF bandwidth was measured at 370 MHz, which is smaller than the 600-MHz simulation result, mainly because of the inconsistency between VGA measurement and simulation results. The VGA bandwidth shortage would limit the maximum achievable PRF of the receiver, which can be fixed by a modified version. The VGA showed a gain tuning range of 38 dB to accommodate communication distance variations.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-17.jpg'" class="figure_img" id="Figure17"/>
Download
Larger image
PowerPoint slide
Figure17.
(Color online) Measured receiver gain and noise versus IF frequency.
IQ channel-matching performance was captured at the IQ receiver output when a 4.5 GHz sine signal was applied to the receiver input, as shown in Fig. 18. This indicates that both the QVCO and IQ-receiver had good phase and magnitude matching performance. Furthermore, the transmitter’s attenuated output was looped back to the receiver input for the demodulation test. The plot in Fig. 19 shows the receiver IQ outputs consisted of four combinational states, with two-bit random data inputs (QPSK mode), whereas those outputs presented only two combinational states with one-bit random data input. Because of the VGA bandwidth limitation, the maximum PRF was up to 400 MHz, indicating a maximum 800 Mbps data rate with QPSK modulation.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-18.jpg'" class="figure_img" id="Figure18"/>
Download
Larger image
PowerPoint slide
Figure18.
(Color online) Receiver output IQ waveforms with 4.5-GHz sinusoid input. The phase difference between the I- and Q-channel measures 24.7%, i.e., 2.7°.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050006-19.jpg'" class="figure_img" id="Figure19"/>
Download
Larger image
PowerPoint slide
Figure19.
(Color online) Loop-back waveform test of the transceiver: (a) 125-MHz PRF and (b) 400-MHz PRF.
6.4. Summary
The TX, including LO buffers after the QPSK modulator, had a measured 8.9 mA current consumption when the PRF was 500 MHz, the RX consumed 17.5 mA excluding the VGA output buffers, and the PLL dissipated ~20 mA, all from a 1.8 V supply. For the TX, the current was mainly dissipated by the PA (3 mA) and LO buffers (4.5 mA) on the basis of simulation results. The RX current was distributed as 4.5 mA for the LNA, 3 mA for the IQ mixer, and 10 mA for the VGAs. A performance summary is shown in Table 1. What is notable is that the proposed transceiver achieved a comparable data rate and energy efficiency using the 3–5-GHz spectral resource and a low-cost 0.18μm CMOS process.
| Parameter | This work | JSSC'15 | JSSC'16 | JSSC'08 | ||
| CMOS technology (nm) | 180 | 65 | 65 | 180 | ||
| VDD (V) | 1.8 | 1 | 1.2 | 1.8 | ||
| Frequency band (GHz) | 3～5 | 7.25～9.5 | 3～10 | 3～5 | ||
| Modulation | QSPK | OOK | BPSK | BPSK | ||
| Data rate (Gbps) | 1 TX 0.8 TRX | 0.5 TX 0.25 TRX | 1 TX 1 TRX | 1 TX 1 TRX | ||
| TX | Pulse width (ns) | 1 | NA | 3 | ～0.5 | |
| Pulse amplitude (Vpp) | 0.18 | 0.4 | 0.16 | 0.7 | ||
| Maximum PRF (MHz) | 500 | 500 | 333* | 1000 | ||
| Power consumption (mW) | 16.0 | 6.9 | 21.4–22.6 | 108 | ||
| RX | Gain (dB) | 26～64 | NA | 15.4～67.6 | 82 | |
| Noise figure (dB) | 52～1.5 | NA | 6.9～7.6 | 4.5 | ||
| Maximum PRF (MHz) | 400 | 500 | 333 | 1000 | ||
| Power consumption (mW) | 31.5 | 5.9 | 17.3～20.9 | 66.6 | ||
| LO | Freq (GIIz) | 4.025 | 8.645 | 10.56 | 4 | |
| VCO PN @l MHz (dBc/Hz) | –125 | –105.6 | NA | –119 | ||
| PLL PN @l MHz (dBc/Hz) | –122.8 | NA | –92.38 | NA | ||
| In band PN (dBc/Hz) | –93 | NA | –92.38 | NA | ||
| RMS Phase noise (ps) | 0.73 | NA | NA | NA | ||
| Reference spur (dBc) | –77.2 | NA | –59 | NA | ||
| Power consumption (mW) | 36 | 2.2 | 10.5～29.4 | 32.4 | ||
| Enegry efficiency (pJ/bit) | 104 | 26 | 59.7–102.2 | 206 | ||
| * Each channel has fixed PRF of 333 MHz, three channels used to achieve effective 1 GHz PRF. | ||||||
Table1.
Performance summary and comparison.
Table options
-->
Download as CSV
| Parameter | This work | JSSC'15 | JSSC'16 | JSSC'08 | ||
| CMOS technology (nm) | 180 | 65 | 65 | 180 | ||
| VDD (V) | 1.8 | 1 | 1.2 | 1.8 | ||
| Frequency band (GHz) | 3～5 | 7.25～9.5 | 3～10 | 3～5 | ||
| Modulation | QSPK | OOK | BPSK | BPSK | ||
| Data rate (Gbps) | 1 TX 0.8 TRX | 0.5 TX 0.25 TRX | 1 TX 1 TRX | 1 TX 1 TRX | ||
| TX | Pulse width (ns) | 1 | NA | 3 | ～0.5 | |
| Pulse amplitude (Vpp) | 0.18 | 0.4 | 0.16 | 0.7 | ||
| Maximum PRF (MHz) | 500 | 500 | 333* | 1000 | ||
| Power consumption (mW) | 16.0 | 6.9 | 21.4–22.6 | 108 | ||
| RX | Gain (dB) | 26～64 | NA | 15.4～67.6 | 82 | |
| Noise figure (dB) | 52～1.5 | NA | 6.9～7.6 | 4.5 | ||
| Maximum PRF (MHz) | 400 | 500 | 333 | 1000 | ||
| Power consumption (mW) | 31.5 | 5.9 | 17.3～20.9 | 66.6 | ||
| LO | Freq (GIIz) | 4.025 | 8.645 | 10.56 | 4 | |
| VCO PN @l MHz (dBc/Hz) | –125 | –105.6 | NA | –119 | ||
| PLL PN @l MHz (dBc/Hz) | –122.8 | NA | –92.38 | NA | ||
| In band PN (dBc/Hz) | –93 | NA | –92.38 | NA | ||
| RMS Phase noise (ps) | 0.73 | NA | NA | NA | ||
| Reference spur (dBc) | –77.2 | NA | –59 | NA | ||
| Power consumption (mW) | 36 | 2.2 | 10.5～29.4 | 32.4 | ||
| Enegry efficiency (pJ/bit) | 104 | 26 | 59.7–102.2 | 206 | ||
| * Each channel has fixed PRF of 333 MHz, three channels used to achieve effective 1 GHz PRF. | ||||||
7.
Conclusion
To improve energy efficiency, a direct phase-switching O-QPSK modulator and current-efficient circuit techniques are proposed for the IR-UWB transceiver. The O-QPSK modulation scheme doubles the system data rate over that of the bi-phase scheme through a passive quadrature phase multiplexer extension, adding very little area and power overhead to the system. A combination of circuit techniques, including CCC and a current-reused LNA, CCC-enhanced PA and transconductance amplifier, passive up- and down-conversion mixer, and passive multiplexer, further help to keep the overall current consumption low. The LO achieves 0.52° integrated phase noise through combinational techniques such as the even-harmonic nulled QVCO phase noise suppression technique, in-band noise-aware design of the PFD/CP, and optimized loop bandwidth.
Further research is encouraged on high data-rate and energy-efficient UWB transceivers based on even higher-order passive phase multiplexing using technologies that are more advanced. Such an example could be using a multi-stage ring type oscillator to generate 8 or 16 phases in an advanced (e.g., 40 nm) CMOS process, where the loss and speed associated with the passive multiplexer are of little concern.
