Application of source biasing technique for energy efficient DECODER circuit design: memory array ap

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1.
Introduction

Memory is one of the essential building blocks for VLSI system design. As the demand of battery operated systems like mobile phones, laptops, hand held devices, biomedical implants, etc are increasing exponentially, the demand of VLSI circuits also increases. For battery operated systems power dissipation is one of the critical parameters for VLSI design engineers. Power reduction in memory cells has been addressed by many researchers and different SRAM cell architectures like 6T, 7T, 8T, 9T and 12T for low power applications have been proposed^[1].

For selecting the proper word width from the memory array, a decoder circuit decodes the address provided by the CPU/peripheral. Though the traditional decoder design for memory array application consumes significant power during the word selection process, very few researches have addressed this issue^[2]. Here in this work we provide a solution for this issue and propose four different decoder circuit design techniques^[3].

Over recent years, circuit designers have faced the challenge of designing high-performance energy efficient circuits. At low supply voltage, maintaining the high speed of an integrated circuit and low power dissipation are major challenges for circuit designers. The leakage current becomes a major component of the total power dissipation for scaling down the feature size in the MTCMOS circuit^[4].

The Decoder is a combination of logic gates which are arranged in a specific way so only one output can be LOW or equal to logic 0 at any given time, with all the other outputs being HIGH for the case of the NAND decoder^[5].

Decoders are also available with an additional “Enable” input pin which is used to turn ON or turn OFF the decoder output by applying logic 1 or 0 to the input of the enabling pin. For example, when the enable input is at logic level 0, (EN = 0) all outputs of the decoder circuit are ON or high state for NAND gates irrespective of the state of inputs A and B. When the enable pin is logic high (EN = 1), the output of the decoder depends upon the input condition to be applied.

To implement this function, the 2-input AND or NAND gates are replaced with 3-input AND or NAND gates by using different techniques.

When we talk about a 3-to-8 decoder circuit using a NAND gate, the circuit has 3 inputs and 8 outputs. The binary inputs are applied at the input terminal the output will either be logical high or low on one of the 8 outputs, which is termed as a digital equivalent for that binary input. For example, a binary input 100, which is 4 in the digital number system, the output pin called D4 goes to low and other output pins go to high.

In the decoder circuit, one extra NMOS transistor is used called the SLEEP transistor^[6] which is used to reduce leakage current and delay of the circuit. Clustering technique, body bias technique, source bias technique and source coupling technique are used to reduce leakage and static energy in the effective manner.

A decoder circuit is used as a row and column decoder in the memory cell. It is also called an input circuitry of memory cell organization, where the 3 × 8 decoder is used for an 8 × 8 memory cell design. The Column decoder is used to select any one output from all eight outputs, which depends on input combinations. This decoder output selects 1 × 8 memory array from the 8 × 8 memory array. Row decoder output selects one array block, i.e. 1 × 1 array.

The paper is organized as follows: Section 2 describes the different DECODER techniques in which two techniques exist and four techniques are proposed. Experimental results, comparison, and discussion of all parameters of proposed techniques with existing techniques are presented in Section 3. The paper is concluded in Section 4.

2.
Different DECODER technique

There are different decoder techniques found to reduce leakage current, dynamic power dissipation, static power dissipation, and delay.

When we analyze the decoder circuit using the AND gate, we found that the high leakage current and static power dissipation compare to that of a decoder circuit using a NAND Gate. So we determine all parameters by using a NAND Gate.

All techniques are named as:

? DECODER circuit using NAND gate without SLEEP transistor

? DECODER circuit using NAND gate with SLEEP transistor

? DECODER circuit using NAND gate with cluster circuit

? DECODER circuit using NAND gate with Body Biasing circuit

? DECODER circuit using NAND gate with Source biasing circuit

? DECODER circuit using NAND gate with Source coupling circuit

2.1
DECODER circuit using NAND gate without SLEEP transistor

This is a normally working 3 × 8 decoder circuit using a NAND Gate and an inverter test bench for complimentary operation^[7]. The output of the decoder circuit is from D₀ to D₇ and the input is given, which is A, B, and C as shown in Fig. 1. This is a conventional decoder that works in normal operation mode when the given input is ABC = (001), then the D₁ output line is zero and the other output lines are one, and so on. The green line indicates the ground terminal, and the pink line indicates the V_dd terminal in Fig. 1.

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Techniques	Dynamic power (μW)/ Dynamic energy (pJ)	Leakage current (pA)	Static power (pW)	Delay
Techniques	Dynamic power (μW)/ Dynamic energy (pJ)	Leakage current (pA)	Static power (pW)	Min (ns)	Max (μs)
Without SLEEP	0.386	?	?	0.372	0.99
With SLEEP	0.372	4.86	5.832	0.212	0.99
Cluster	0.370	16.59	19.908	0.264	0.99
Body bias	0.370	4.297	5.1564	0.264	0.99
Source bias	0.364	3.62 × 10^?3	0.0043	0.159	0.99
Source coupled	0.489	29.08	34.896	0.387	0.99

Techniques	Static energy		Dynamic PDP/EDP
Techniques	Min (zJ)	Max (aJ)	Min	Max
Without SLEEP	?	?	0.143	0.382
With SLEEP	1.236	4.811	0.078	0.368
Cluster	5.255	16.424	0.097	0.366
Body bias	1.361	4.254	0.097	0.366
Source bias	6.91 × 10^–4	3.5 × 10^–3	0.05	0.360
Source coupled	13.504	28.789	0.189	0.484