1.
Introduction

The power MOSFETs are indispensable components in power electronic systems for space and atmospheric applications. Unfortunately, these devices are sensitive to the space radiation environment, which is composed of various nature and energetic particles such as heavy ions. single-event burnout (SEB) is one of the main destructive phenomenon in space application that could cause the permanent failure of power MOSFETs. When heavy ions strike a device at the off-state condition, the parasitic bipolar transistor inherited in the power MOSFET could be triggered by extensive carriers generated by energetic heavy ions. Once the parasitic bipolar transistor turns on, the inner carrier multiplication effect and peak electric field shifting (named the Kirk effect) may become more severe due to the positive feedback effect of the parasitic bipolar transistor. This phenomenon will lead to thermal runaway and burnout of the device^[1]. Therefore, to suppress the activity of the parasitic bipolar transistor becomes one of the main design considerations in structure optimization.



Some technical solutions have been carried out to improve the SEB survivability of power MOSFET by suppressing the parasitic bipolar transistor behavior. One commonly proven way is the use of an enlarged P⁺ region at source contact. It can increase the voltage drop of the parasitic bipolar transistor between the base (P-well region below the N⁺ region) and the emitter (the N⁺ region), making it harder to turn on. But the device threshold voltage could be influenced by using excessive P⁺ lateral diffusion. Another effective way presented by S. Liu et al. is that the power MOSFET with an appropriate buffer layer between the N-drift and N-substrate improves the secondary-breakdown behavior of the parasitic bipolar transistor^[2]. However, the overall on-resistance of the device is influenced due to the additional buffer layer^[1]. In addition, many other hardening techniques have also been proposed recently, such as the UMOSFET with enlarged P⁺ structure, the power MOSFET integrated with Schottky structure, the optimized split gate trench structure, the local carrier lifetime control skill, the high-k gate Dielectrics structure, the planar power MOSFET with linear doping layer and the split gate trench with dual channels structure^[3–9]. By using these structures, an enhanced SEB performance is achieved with varied levels of success and the influence of the parasitic bipolar transistor can be suppressed to a certain degree. However, the activation of the parasitic bipolar transistor still dominates the main influence factor in the SEB performance due to the existence of the sensitive region (the P-well region below the N⁺ source) in the previous structures.



In this paper, a novel 150 V planar power MOSFET with partially widened trench source is investigated by three-dimensional (3D) numerical simulation with Synopsys Sentaurus Technology Computer Aided Design (TCAD) software. Based on the structure improvement, the activity of the parasitic bipolar transistor can be suppressed to a maximum degree due to the elimination of the sensitive region in the planar power MOSFET structure. This partially widened trench concept has been demonstrated experimentally in the IGBT structure by Sumitomo et al.^[10]. The fabrication process of a partially widened trench structure only needs to add a few steps through the trench etch and oxide deposit methods and it is completely compatible with the standard power semiconductor trench technology without a complicated technology process. One drawback is that the fabrication cost of the proposed structure is slightly higher than that of the conventional structure owing to the additional process steps.



To comprehensively study the structure performance, 3D numerical simulation is performed to compare the parameter characteristic of two structures firstly. Then the SEB performance is investigated by analyzing the critical SEB threshold voltage, the critical linear energy transfer (LET) value and the inner physical behavior. Simulation results show that the proposed power MOSFET presents a superior SEB performance compared with conventional planar structures.

2.
Device structure and characteristics simulation

2.1
Device structure

Fig. 1 gives a 3D simulated structure view and 2D cross-sectional view of the conventional planar power MOSFET and the proposed structure, respectively. Note that the metal region of the source is omitted in all simulations for the purpose of saving computing time. In order to achieve an accurate comparison, identical doping profiles and dimensional parameters are assumed in all structures, except for the source structure. According to our pervious study on the planar power MOSFET structure^[11], the technological parameters used in the simulation structure are consistent with our actual structure design. For the proposed structure, the source is designed with the trench structure and widened laterally at 0.35 μm depth, as shown in Fig. 1(b). The partially widened contact region with 6 μm width is just below the N⁺ source. Thus, the P-well region below the N⁺ region is replaced by the source contact. The major structure parameters are shown in Table 1.

Structure parameter	Conventional planar structure	Proposed structure
Cell pitch (μm)	10	10
N-drift thickness (μm)	10	10
Gate oxide thickness (nm)	100	100
Gate poly width (μm)	5	5
N-drift doping (1015 cm?3)	2	2
P-body depth (μm)	2.7	2.7
P-body doping (1016 cm?3)	8	8
N+ depth (μm)	0.35	0.35
N+ width (μm)	0.5	0.5
N+ doping (1020 cm?3)	1	1
P+ doping (1018 cm?3)	5	5
Trench source depth (μm)	?	0.85
Trench source width (μm)	?	6
Partially widened trench source width (μm)	?	6

Table1.
Major structural parameters for the simulation.



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Structure parameter	Conventional planar structure	Proposed structure
Cell pitch (μm)	10	10
N-drift thickness (μm)	10	10
Gate oxide thickness (nm)	100	100
Gate poly width (μm)	5	5
N-drift doping (1015 cm?3)	2	2
P-body depth (μm)	2.7	2.7
P-body doping (1016 cm?3)	8	8
N+ depth (μm)	0.35	0.35
N+ width (μm)	0.5	0.5
N+ doping (1020 cm?3)	1	1
P+ doping (1018 cm?3)	5	5
Trench source depth (μm)	?	0.85
Trench source width (μm)	?	6
Partially widened trench source width (μm)	?	6

To precisely analyze the heavy ions striking process, 3D mixed electro-thermal simulation with appropriate physics models are used in this work. The physics models used in our simulation are: generation and recombination models, including Shockley-Read-Hall (SRH) recombination, Auger recombination and avalanche generation models; mobility models with the high-field saturation, interface degeneration and Phillips unified mobility; and band structure models, including Fermi–Dirac statistic and bandgap narrowing models. Considering the mixed electro-thermal simulation is used to analyze the inner thermal-runaway and avalanche behavior, the thermodynamic model and the wide temperature avalanche model (the New University of Bologna Impact Ionization model) are employed in the simulation. The atmosphere temperature in all simulations is 300 K and the thermal resistance at the bottom side is set with 1 mm²·K/W. The heavy ions model is also included in the simulation to depict the ions behavior. The electron–hole pairs generation by heavy ions is described by the spatial and temporal Gaussian distribution along the vertical penetration track, and the charge distribution remains the same along this track^{[3, 7]}. The initial charge generation time is set at 5 ps. The characteristic time of the temporal Gaussian function is 2 ps, which is the default value in the Sentaurus. The simulation gives the electron–hole pairs concentration generated along the track after the ions penetrate the device and that can be calculated through the LET, the track radius and the ion penetrating range. In the previous study by Luu et al.^[12], the influence of the ion penetration depth, position and LET value for SEB in the planar power MOSFET has been studied in details. In our simulation, the heavy ions track is set to penetrate the entire device for the worst case condition and the ion track radius is set to be 0.1 μm^[7]. Therefore, the drain current induced by the heavy ions mainly depends on the LET value, which gives the deposited energy per unit of track length in units of MeV/cm or pC/μm (for silicon material, 1 MeV·cm²·mg^?1 = 0.01 pC/μm)^[6]. The unit pC/μm is used during the simulation. The striking position of heavy ions locates at the neck area near the channel region, which has been verified as the most sensitive area^[12]. An active area of 1 mm² is selected in the simulation.

2.2
Device parameter characteristics

Fig. 2 shows the breakdown voltage and threshold voltage of the conventional planar structure and the proposed structure, respectively. The threshold voltages of all structures are the same owing to the unchanged channel structure. The breakdown voltages of the two structures are all over 150 V blocking ability. It is worth noting that the breakdown voltages of the proposed structures are slightly lower than the conventional structure due to the influence of deep trench source design^[13]. For the conventional structure, the space of the depletion layer extension in the P-body region is enough before the breakdown behavior occurs. In the proposed structure, the deeper depth of the trench source can help to discharge the extensive holes and change the carriers flowing path away from the sensitive area effectively. But the much deeper trench depth will squeeze the depletion layer extension at the P-body side and it changes the charge to cumulate near the trench bottom region, resulting in the lower breakdown voltage phenomenon. To provide more insight on the influence of the trench depth, the breakdown voltage as a function of the trench depth with 0.5 μm steps is given in Fig. 3. It can be seen that the breakdown voltage decreases as the increasing of the trench depth, which is consistent with the conclusion in Ref. [13]. Therefore, in order to give enough of a margin of the breakdown voltage, the trench depth with 0.85 μm depth in the proposed structure is selected as an appropriate structure dimensions in our simulation. However, it should be noted that the dimensions selection of trench depth can be adjusted by the actual doping profiles and structure parameters to achieve the best optimization effect.






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Figure2.
?(Color?online)?Simulated results of the breakdown voltage and threshold voltage for two structures.






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Figure3.
(Color?online)?Simulated results of the breakdown voltage as a function of the trench sources depth.




Fig. 4 shows the comparison of the gate charge and forward I–V characteristic of the two structures. It clearly shows that the specific resistance R_DS(ON) and gate charge are the same. Therefore, the proposed structure can achieve the similar parameter performance compared with the conventional structure.






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Figure4.
(Color?online)?Simulated results of the gate charge and forward I–V characteristic of two structures.

3.
Simulation results of SEB performance and discussion

When an energetic ion strikes on the power MOSFET biased at an off-state condition, SEB may occur due to the triggering of the parasitic bipolar transistor. To investigate the SEB behavior, the gate electrode is shorted with the source to ensure the MOSFET is in the off-state. Then the bias drain voltage and LET value applied on the device are changed gradually to find the maximum critical value without SEB behavior. Firstly, the bias drain voltage is set to increase with 5 V steps at a fixed LET value. If the drain bias voltage reaches to maximum rated breakdown voltage (150 V for the simulation structure) without SEB, the LET value increases continually to find the next critical drain voltage. Once the drain current or lattice temperature increases continually during the transient process, that bias drain voltage and LET value can be extracted as the SEB threshold voltage and critical LET value. Then, the internal physical behavior is also investigated to compare the difference between the two structures.



Fig. 5 shows the extracted SEB threshold voltage and LET value for two structures. For the conventional MOSFET, SEB occurs under drain voltage 105 V and LET value 0.06 pC/μm. For the proposed structure, SEB threshold voltage is 120 V at LET value 0.7 pC/μm. Obviously, the proposed structure demonstrates a higher SEB threshold voltage and the critical LET value. The critical LET value applied on the proposed structure increases about 11 times. That means, the proposed structure presents an enhanced SEB performance at the much higher heavy ions energy and high drain bias voltage conditions compared with the conventional planar MOSFET.






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Figure5.
(Color?online)?Simulated results of drain current and lattice temperature for the two structures to find the SEB threshold voltage and the critical LET.




To further understand the difference of the inner physical mechanism, Fig. 6 shows the comparison result of the drain current and lattice temperature of two structures at the same drain bias voltage and LET value during the transient process. Both structures are fixed at drain bias voltage 105 V and LET value 0.06 pC/μm. It can be seen that the drain current and lattice temperature of the proposed structure (blue line) gradually decrease to the initial situation after the ions striking process. On the contrary, the drain current and lattice temperature of the conventional structure increase continually, which indicates the SEB phenomenon.






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Figure6.
(Color online) Comparison results of drain current and lattice temperature for two structures at the same bias condition.




To provide more clearly a comparing investigation, we capture the inner physical behavior of the 3D simulation structure and 2D cross-sectional view at two time points T₁ (0.1 ns) and T₂ (1 ns), respectively. Note that a 2D cross-sectional view is extracted at the half position of 3D structure, where the striking position of the heavy ions is.



Fig. 7 shows the distribution of electric field of the two structures at two time points. It can be seen that the peak electric field in all structures shifts to the N-drift/N-substrate junction at time T₁ (0.1 ns). This electric field shifting phenomenon, named the Kirk effect, is directly related to the SEB threshold voltage due to the avalanche effect and secondary-breakdown behavior of the parasitic bipolar transistor^[14–15]. Then, at time point T₂ (1 ns), the peak electric field of the conventional structure at the N-drift/N-substrate junction becomes higher due to the positive feedback behavior of the parasitic bipolar transistor. However, for the proposed structure, the electric field disappears obviously near the N-drift/N-substrate junction at time point T₂ and mainly stays at the P-well region.






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Figure7.
(Color online) Simulated results of electric field profile of two structures at transient time T₁ and T₂.




Figs. 8 and 9 show the comparison results of the electron current density and lattice temperature, respectively. From the electron current density distribution in Fig. 8, it can be seen that the substantial electron current is injected along the left side channel at time T₁, which is related to the dynamic avalanche behavior and the action of the parasitic bipolar transistor, and the electron injection behavior becomes more severe for the conventional structure at the time T₂. On the contrary, the electron current of the proposed structure disappears at time T₂, as shown in Fig. 8. That means the parasitic bipolar transistor turns off after the ions impacting process for the proposed structure. Fig. 9 presents the lattice temperature distribution of two structures. The temperature of the conventional structure locates along the striking path of a heavy ion due to the flowing of excessive carriers at time T₁, and the temperature increases much higher along this path at time T₂. Conversely, the temperature of the proposed structure gradually lowers to the initial atmosphere temperature at time T₂.






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Figure8.
(Color online) Simulated results of electron current density of two structures at transient time T₁ and T₂.






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Figure9.
(Color online) Simulated results of lattice temperature of two structures at transient time T₁ and T₂.




According to the simulation results above, an enhanced SEB performance is given by the proposed structure due to the advantage of structure improvement. When a heavy ion travels into the devices, extensive electro-hole pairs are generated along its path to form a transient current source. If this transient current is sufficiently high and long enough, a transition in the power MOSFET from a normal off-state voltage condition to a bipolar turning on condition occurs^[1]. This activation of the parasitic bipolar transistor can be seen in Fig. 8 at time T₁ for the two structures. Then, if the transient current increases continually under the high drain bias voltage and sufficient ion energy, a second breakdown behavior in the parasitic bipolar transistor could be triggered and it will cause the catastrophic failure of the device finally^[1]. The transition from the bipolar transistor turning on condition to the second breakdown condition is mainly related to electric-thermal self-sustained phenomenon due to the transient electric field shifting phenomenon (the Kirk effect) and avalanche behavior with local elevated temperature^{[1, 14]}. It can be seen in Fig. 8 at time T₂ that the SEB phenomenon occurs in the conventional structure at these bias conditions. On the contrary, although the turning on of the parasitic bipolar transistor occurs in the proposed structure, the second breakdown behavior of the parasitic bipolar transistor is hard to trigger due to the most sensitive region being replaced by the partially widened source structure, as shown in Fig. 1. The SEB phenomenon depends upon whether or not the bias conditions are sufficient to trigger the second breakdown behavior, which is related to the drain bias voltage and the ion’s energy (the LET value). The transition from the bipolar transistor turning on condition to the second breakdown condition in the proposed structure needs much higher electric field strength and current density compared with the situation in the conventional structure. Therefore, The SEB behavior related to the work of the parasitic bipolar transistor in the proposed structure can be reduced to a minimum degree.






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Figure1.
(Color online) 3D simulation structure view and 2D cross-sectional view of (a) the conventional planar power MOSFET and (b) the proposed power MOSFET with partially widened trench source.

4.
Conclusion

A novel planar power MOSFET structure with partially widened trench source is investigated and compared with the conventional planar structure by 3D numerical simulation (using the Sentaurus TCAD software). The SEB survivability of the proposed structure is improved effectively due to the elimination of the most sensitive area of parasitic bipolar transistor in the planar power MOSFET structure. Simulation results show that the optimized structure can increase the maximum critical LET applied on the device from 0.06 to 0.7 pC/μm. The SEB threshold voltage also increases, to 120 V (80% of breakdown voltage) compared with 105 V of the conventional structure. Meanwhile, the main parameter characteristics of the proposed structure are the same as those of the conventional structure. Therefore, the proposed structure indicates a potentially great ability to enhance the SEB performance for the planar power MOSFET structure.