1.
Introduction

With the rapid development and upgrading of integrated circuits, portable electronic devices with small volume, low power and good performance are used widely. As the block offering power and maintaining normal system operation, the power management circuit restricts the performance and development of electronic devices. Among the main forms of power management circuit, a low dropout (LDO) regulator has many advantages in terms of power consumption, area, circuit structure and transient response, so it is a preferable choice for applications.



Generally speaking, a traditional LDO regulator uses a large off-chip capacitor to maintain stable operation^[1–3]. However, it may not be suitable for portable applications where lots of voltage regulators are embedded. So output-capacitorless LDO regulators become popular in battery-powered portable products. But there are two main issues that must be considered in output-capacitorless design. The first is the frequency compensation strategy under the whole range of output current, and the second is the transient performance without an output capacitor.



Moreover, in order to increase the battery lifetime, the LDO regulator with ultra-low quiescent power is rather attractive. However, because of ultra-low power, the parasitic poles of error amplifier are located at low frequencies and need complicated frequency compensation. Meanwhile, the transient response is also greatly affected by the limited slew rate of the power transistor and loop bandwidth.



Several methods have been proposed to solve the above problems^[4–17]. The LDO regulator^[4] uses a digital error amplifier which consumes only 103 nA quiescent current, but it is reported that the settling time is as long as 400 μs. A dynamic bias-current boost technology^[6] is used to realize the ultra-low power design, which achieves only 1.2 μA quiescent current, but it has a large undershoot and overshoot, which makes it impractical in some applications. Based on a flipped voltage follower, a simple folding structure of LDO circuit^[8] is proposed. Thanks to the folding structure, the system loop keeps stable easily while the loop gain is sacrificed, therefore it will affect the load regulation. For improving dynamic performance, Ref. [9] introduces a momentarily current-boosting voltage buffer, Ref. [10] presents a push-pull technology, but the loop gains of these two LDOs are not high enough to achieve a rapid transient response. A direct voltage spike detection circuit^[11] is developed to enhance the slew rate and improve transient response, but this approach requires additional electronic components such as resistors and capacitors, which results in a large area. Furthermore, the circuit performance may be changed by process variation.



In order to solve the problems of output-capacitorless ultra-low power LDO more effectively, an LDO regulator which consists of a slew rate enhanced (SRE) circuit and a high performance buffer without output capacitor is presented in this paper. An ultra-low output impedance is obtained by the proposed buffer with the structure of dual shunt feedback loops. The buffer with ultra-low impedance improves load regulation, line regulation and transient response noticeably. The SRE circuit also has the ability to optimize the transient response.



This paper is organized as follows. Section 2 discusses the LDO’s structure and stability. The high performance buffer is introduced in Section 3. Section 4 presents a novel SRE circuit in detail. The corresponding experimental results are given in Section 5. Finally, the conclusion is given in Section 6.

2.
Circuit structure and stability analysis

2.1
Circuit structure

Fig. 1 gives the whole schematic of the proposed LDO regulator. The LDO contains six modules: error amplifier, buffer, power regulator, frequency compensation network, feedback network, and slew-rate enhanced circuit, where the buffer is used to improve load and line regulation, frequency compensation is used to maintain circuit stability mainly, and the slew-rate-enhanced module is used to improve transient performance.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-1.jpg'"
class="figure_img" id="Figure1"/>



Download



Larger image


PowerPoint slide






Figure1.
Schematic diagram of the proposed LDO regulator.




Fig. 2 gives the main circuits in Fig. 1 except the SRE circuit which will be described in part 4. The error amplifier is formed by transistors M₀–M₈, transistors M₉–M₁₁ and capacitor C_m, resistance R₁ constitutes the buffer, the feedback circuit is realized by resistances R_f1 and R_f2, M_P is the power transistor, V_REF is a reference voltage and C_C is the Miller compensation capacitor.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-2.jpg'"
class="figure_img" id="Figure2"/>



Download



Larger image


PowerPoint slide






Figure2.
Main circuits of the proposed LDO regulator.

2.2
Stability analysis

In order to analyze the stability of LDO, the corresponding small signal model is shown in Fig. 3. It uses Miller compensation technology to achieve stability of the whole system. The increased error amplifier (EA) output capacitance is obtained by Miller compensation. Thus, the pole P₁ at node A shown in Fig. 2 becomes the dominant pole. What is more, because of the low output impedance of the buffer, the pole P₂ at node B shown in Fig. 2 is located at higher frequency. Hence, there is only the dominant pole P₁ within the unity gain bandwidth, and the loop of the system will remain stable. The open-loop function can be expressed as follows:






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-3.jpg'"
class="figure_img" id="Figure3"/>



Download



Larger image


PowerPoint slide






Figure3.
Small signal model of the proposed LDO.

$$T(s) = frac{{{A_{ m dc}}}}{{(1 + frac{s}{{{P_1}}})(1 + frac{s}{{{P_2}}})(1 + frac{s}{{{P_3}}})}}, $$

(1)

where A_dc is low frequency gain, P₁ is the dominant pole and P₂, P₃ are nondominant poles. They can be expressed by:

$${A_{ m dc}} = {A_1}{A_2}{A_3} = {g_{ m m1}},,{g_{ m m2}},,{g_{ m mp}},,{R_{ m EA}},,{R_{ m m buffer}},,{R_{ m out}}, $$

(2)

$${P_1} = frac{1}{{{R_{ m EA}}[(1 + {A_2}{A_3}){C_C} + {C_1}]}}, $$

(3)

$${P_2} = frac{1}{{{R_{ m buffer}}{C_2}}}, $$

(4)

$${P_3} = frac{1}{{{R_{ m out}}{C_{ m out}}}}, $$

(5)

where A₁, A₂, A₃ are the gains of error amplifier, buffer and output stage respectively. Similarly, g_m1, g_m2, g_mp, R_EA, R_buffer, R_out, C₁, C₂, and C_out respectively present transconductances, output resistances and output capacitances of the three stages.



The frequency responses of the LDO with different load currents and input voltages are simulated and shown in Fig. 4. For example, Fig. 4(a) shows a phase margin of 68° and a low frequency loop gain of 85 dB when the load current is 10 μA, a gain margin of 86° and a low frequency loop gain of 53 dB when the load current is 200 mA. It can be seen that the LDO regulator keeps steady within the load current range from 10 μA to 200 mA, or the input voltage range from 2 to 3.3 V.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-4.jpg'"
class="figure_img" id="Figure4"/>



Download



Larger image


PowerPoint slide






Figure4.
The frequency responses of the LDO (a) when load current varies from 10 μA to 200 mA. (b) When input voltage varies from 2 to 3.3 V.

3.
High performance buffer

Fig. 5 shows the structure of the ultra-low output impedance buffer^[18]. Based on quasi floating gate (QFG) technology, a new class-AB super follower is developed. The gate of current source M₁₁ is connected to the gate of transistor M₁₂ weakly by a large resistance R₁, which can be replaced by a diode-connected PMOS transistor op-erating in the cut-off region. Since there is no DC current flowing through R₁, the DC gate voltage of M₁₁ is the same as M₁₂’s, so the quiescent current of M₁₁ is accurately written as:






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-5.jpg'"
class="figure_img" id="Figure5"/>



Download



Larger image


PowerPoint slide






Figure5.
The proposed buffer.

$${I_{11}} = 2{I_{ m{B}}}.$$

(6)

When the output load varies quickly, the capability of dynamic current boosting which can improve the transient response obviously is obtained by the follower. Specifically, when output current (I_out) decreases abruptly, an overshoot of output voltage (V_out) occurs. Then the error amplifier detects the overshoot of V_out and produces an error voltage V_EA. If V_EA rises, V_a and the current in M₁₀ would decrease, therefore, the gate voltage of M₁₁ also decreases when C_m couples V_a variation. As a result, more drain current from M₁₁ is generated, and the gate capacitance of M₁₁ will be charged through the increasing drain current. So that the output voltage V_out decreases and will recover to a stable value after a short response time. Similarly, when I_out becomes large suddenly and produces an undershoot voltage, V_a and the current in M₁₀ will increase with the decreased V_EA. C_m couples the voltage variation of V_a to the gate of M₁₁, therefore more drain current is obtained from M₁₀ to discharge the gate capacitance. In a word, in both cases, a push-pull output stage constituted of M₁₀ and M₁₁ realizes dynamic current boosting.



A small output impedance buffer with the structure of dual shunt feedback loops is obtained in the proposed LDO. The buffer can not only improve load and linear regulations, but also improve the transient performance significantly. The output impedance can be written as follows:

$${R_{ m buffer}} = frac{1}{{{g_{ m m9}}({g_{ m m10}} + {g_{ m m11}})({r_{10}}//{r_{11}})}},$$

(7)

where g_m9, g_m10, g_m11 present the transconductances of M₉–M₁₁ respectively, r₁₀ and r₁₁ are the output resistances of M₁₀ and M₁₁.

4.
Slew-rate-enhanced circuit

Fig. 6 shows the proposed slew-rate-enhanced circuit. It is mainly used to overcome the difficulty of slew-rate limitation at the gate of power transistor M_P under the condition of ultra-low quiescent current. For achieving good push–pull driving performance when load current changes suddenly and reducing power consumption at steady state, the width-to-length ratio of transistors M₁₆–M₁₉ should be designed carefully to guarantee the voltages V_X and V_Y close to input voltage and ground respectively.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-6.jpg'"
class="figure_img" id="Figure6"/>



Download



Larger image


PowerPoint slide






Figure6.
The proposed SRE circuit.




The width-to-length ratio of M₁₆–M₁₉ should be designed to satisfy

$${left( {frac{W}{L}} ight)_{16}} < ,,{left( {frac{W}{L}} ight)_{17}}, $$

(8)

$${left(frac{W}{L} ight)_{18}} > ,,{left(frac{W}{L} ight)_{19}}.$$

(9)

According to Eq. (8), the voltage V_X keeps low-level and M₂₁ is turned off during stable state. When the load current increases suddenly, the output voltage decreases consequently, and the drain (gate) voltage of M₁₄ decreases rapidly by the detection of capacitance C_f. Then, V_X is pulled up and M₂₁ is turned on, a large current is generated by M₂₁ to discharge the gate capacitance of M_p rapidly. Similarly, according to Eq. (9), the voltage V_Y keeps high-level and M₂₀ is turned off during stable state. When the load current decreases, the output voltage increases and V_Y is pulled down to turn on M₂₀, a large current is generated by M₂₀ to charge the gate capacitance of M_p quickly. Therefore, this dynamic push-pull technique shortens the settling time drastically. That is to say, the proposed SRE circuit can increase the slew rate and reduce overshoot (undershoot) voltages greatly at load transients, thus the transient response will be improved. Besides, the stability of the LDO is not affected by the SRE circuit, because there is only a 0.5 pF sense capacitor C_f and the transistors M₂₀ and M₂₁ operate in the cut-off region when the system works normally.



Fig. 7 compares the simulated transient responses with and without the SRE circuit. When the load current changes from 10 μA to 200 mA within 1 μs, the LDO in Fig. 7(a) realizes stable output voltage within 21 μs with undershoot of 110 mV, or within 42 μs with overshoot of 50 mV. As shown in Fig. 7(b), thanks to the proposed SRE circuit, the LDO settling time is reduced to 10 μs with an undershoot of 35 mV, or 25 μs with an overshoot of 16 mV. It can be seen that the SRE circuit indeed improves the transient response of the LDO greatly.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-7.jpg'"
class="figure_img" id="Figure7"/>



Download



Larger image


PowerPoint slide






Figure7.
The simulated transient responses. (a) Without the SRE circuit. (b) With the SRE circuit.

5.
Experimental results

In this work, the proposed LDO regulator is fabricated by standard SMIC 0.18 μm CMOS technology. The output voltage is stabilized at 1.8 V while the supply voltage varies from 2.0 to 3.3 V. The chip microphotograph and its layout are shown in Fig. 8. It includes the LDO circuit, reference current circuit, reference voltage circuit, shut-down circuit and pins. Because the LDO regulator does not contain any off-chip capacitor, it occupies a small area of 220 × 210 μm² without pins (750 × 750 μm² with pins).






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-8.jpg'"
class="figure_img" id="Figure8"/>



Download



Larger image


PowerPoint slide






Figure8.
(Color online) The microphotograph of the chip.




The measured plots of line regulation are shown in Fig. 9. According to the pictures, the variation of output voltage is as small as 20 mV when the input voltage varies from 3.3 to 2.0 V in Fig. 9(a) (2.0 to 3.3 V in Fig. 9(b)) with edge time of 1 μs, so the calculated line regulation is 15.38 mV/V. As illustrated in Section 4, the SRE circuit improves the transient response of the LDO greatly. It can be seen that the LDO keeps stable after 12 μs with an undershoot of 26 mV, or after 35 μs with an overshoot of 12 mV.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-9.jpg'"
class="figure_img" id="Figure9"/>



Download



Larger image


PowerPoint slide






Figure9.
(Color online) Line transient response: (a) input voltage varies from 3.3 to 2.0 V and (b) input voltage varies from 2.0 to 3.3 V.




Similarly, Fig. 10 shows the measured plots of load regulation. With a constant input voltage of 2.0 V, the load current suddenly varies from 10 μA to 200 mA in Fig. 10(a) (200 mA to 10 μA in Fig. 10(b)) with edge time of 1 μs, the output voltage varia-tion is only 40 mV, therefore the load regulation of LDO is 0.4 mV/mA. The LDO settles down after 12 μs with an undershoot of 38 mV, or after 31 μs with an overshoot of 18 mV.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/3/PIC/17050026-10.jpg'"
class="figure_img" id="Figure10"/>



Download



Larger image


PowerPoint slide






Figure10.
(Color online) Load transient response. (a) Output current varies from 10 μA to 200 mA. (b) Output current varies from 200 mA to 10 μA.




Table 1 shows the performance parameters of our work. The LDO regulator has a maximum output current of 200 mA. The input voltage range is 2.0–3.3 V, the drop-out voltage is 200 mV and the quiescent current is only 1.2 μA. Table 2 gives the comparison with some previous works. It can be clearly seen that the proposed LDO has more advantages in chip area, low power consumption, line and load regulation.

Parameter	Value
Input voltage	2.0–3.3 V
Output voltage	1.8 V
Load capacitor	100 pF
Miller capacitor	10 pF
Max. output current	200 mA
Quiescent current	1.2 μA
Dropout voltage	200 mV
Line regulation	15.38 mV/V
Load regulation	0.4 mV/mA

Table1.
Performance parameters of the proposed LDO.



Table options
-->


Download as CSV

Parameter	Value
Input voltage	2.0–3.3 V
Output voltage	1.8 V
Load capacitor	100 pF
Miller capacitor	10 pF
Max. output current	200 mA
Quiescent current	1.2 μA
Dropout voltage	200 mV
Line regulation	15.38 mV/V
Load regulation	0.4 mV/mA

Parameter	Ref. [6]	Ref. [13]	Ref. [17]	Ref. [11]	Ref. [16]	This work
Year	2011	2012	2013	2010	2016
Technology (μm)	0.13	0.09	0.18	0.35	0.18	0.18
Vin (V)	0.9	1	1.8	1.4	2.1–3.3	2.0–3.3
Chip-area (mm2)	0.031	0.0041	NA	0.155	0.0058	0.042
Vout (V)	0.8	1	1.64	1.2	1.8	1.8
VDO (mV)	100	150	200	200	NA	200
IQ (μA)	1.3	60	0.33	43	50	1.2
Imax (mA)	50	100	150	100	10	200
ΔVout (mV)	700	28	48	70	NA	40
Output capacitor (μF)	Cap-free	1	13.12	0.1	NA	0–0.1
Line regulation (mV/V)	NA	18	NA	NA	5.03	15.38
Load regulation (mV/mA)	NA	0.28	0.33	0.4	0.67	0.4

Table2.
Performance comparison of the proposed regulator and previous works.



Table options
-->


Download as CSV

Parameter	Ref. [6]	Ref. [13]	Ref. [17]	Ref. [11]	Ref. [16]	This work
Year	2011	2012	2013	2010	2016
Technology (μm)	0.13	0.09	0.18	0.35	0.18	0.18
Vin (V)	0.9	1	1.8	1.4	2.1–3.3	2.0–3.3
Chip-area (mm2)	0.031	0.0041	NA	0.155	0.0058	0.042
Vout (V)	0.8	1	1.64	1.2	1.8	1.8
VDO (mV)	100	150	200	200	NA	200
IQ (μA)	1.3	60	0.33	43	50	1.2
Imax (mA)	50	100	150	100	10	200
ΔVout (mV)	700	28	48	70	NA	40
Output capacitor (μF)	Cap-free	1	13.12	0.1	NA	0–0.1
Line regulation (mV/V)	NA	18	NA	NA	5.03	15.38
Load regulation (mV/mA)	NA	0.28	0.33	0.4	0.67	0.4

6.
Conclusion

This paper introduces a low-dropout regulator which obtains ultra-low quiescent power and high slew rate without output capacitor. An ultra-low output impedance buffer is also presented. The increased slew-rate is achieved by sensing the transient output voltage of the LDO regulator. The proposed LDO occupies only 0.042 mm² area. It consumes a low quiescent current of 1.2 μA. In addition, the measured line and load regulations meet the design requirements. So, the LDO achieves a good stability.