1.
Introduction

As the gate length of a bulk metal oxide semiconductor field effect transistor (MOSFET) shrinks below 32 nm the performance of the device is debased by severe short channel effects (SCEs). To overcome these types of problems ultra-thin body double-gate (DG) devices emerged as a more promising candidate. Among all the DG device structures^[1], FinFET has drawn significant interest in the semiconductor industry because of its quasi-planar structure and scalability than other planar DG structures^[2]. FinFET showed the intensity of VLSI research that it can be scaled up to the shortest channel length for the given gate oxide thickness^[3]. The undoped underlap region facilitates to reduce SCEs and leakage current. It also reduces random dopant effects, which improves process variation effects^[4]. These facilities are granted at the cost of increased source/drain (S/D) series resistance (R_S/D) that degrades the current driving capabilities and reliability^[5] of the device. Henceforth, the need of improving the performance along with the reliability of the device are fulfilled by the use of high-k spacers, because it has the high coupling capability of the fringe field between the gate and underlap region, which reduces series resistance. On the other hand, as the value of k increases, the fringe capacitance also increases that deteriorates the circuit delay. The device characteristics and circuit performance are together enhanced by using dual-k architecture in terms of symmetric and asymmetric design^[6]. This creates a trade-off between fringe capacitance and R_S/D, consequently to take advantage of the high-k spacer and underlap length optimized from Yang et al.^[7]. Many novel device architectures have been investigated in the past to improve the subthreshold characteristics. But the improvements in subthreshold characteristics of those structures come at the cost of reduced I_ON^{[8, 9]}.



For further improvement in the on-current (I_ON) on the same technology node (without reducing the gate length), strain engineering in FinFET also proved itself by introducing stressors in the form of SiC and SiGe in S/D regions for n-type and p-type respectively^{[10, 11]}. Due to a lattice constant mismatch between Si and SiC, the tendency of SiC alloy stressor to expand causes tensile stress. Such tensile strain in the channel increases the mobility of charge carrier in SiC S/D devices. The possible increment in the drive current is due to improvement in the carrier mobility because of longitudinal uniaxial (processed induced) strain developed on the Fin due to SiC stressors^[11]. The advantage of the uniaxial strain approach is that it can be engineered during the CMOS manufacturing. It has been shown that the introduction of a process induced stress in the Si channel can improve the mobility of both carrier types (n-FinFET and p-FinFET)^[12]. The amount of stress introduced into the channel depends on the amount of SiC elevation, SiC lateral compression and the exact shape. The stabilised amount of stress and major challenges based on the epitaxial SiC source/drain of FinFET are cautiously deliberated^[13]. Among the various reliability issues, positive bias temperature instability (PBTI) is the major issue which was described by the many authors for various alloy based devices such as In_xGa_1?xAs FinFET^[14]. But it has not been analysed for SiC FinFET, so we introduce reliability issues and their solutions for Si_1?yC_y FinFET for the first time.



In this work, we also thought-out and capture the assets of asymmetrical dual-k spacers and SiC S/D pockets to enhance the performance and reliability of n-type FinFET at the 14 nm node. Variations in SCEs are also studied and explained in relation to gate lengths (L_g) at 10, 14, 18, and 22 nm. We analyse the performance of SiC S/D asymmetric dual-k spacer for different mole fraction (y) in Si_1?yC_y like the analysis done by varying the Ge mole fraction for SiGe alloy^[15].



This paper is organized in the following segments. Section 2 comprises the device structure and simulation methods. Section 4 describes the performance, reliability and process variation analysis. Finally, conclusions are drawn in Section 4.

2.
Proposed device structure and simulation method

The 3-D simulation of the device is done using the Sentaurus TCAD tool^[16]. The proposed asymmetric dual-k spacer with SiC S/D FinFET 2-D and 3-D structures are shown in Fig. 1. It consists of an inner high-k (HfO₂, k = 25) spacer having length L_hk as 12 nm and an outer low-k (SiO₂, k = 3.9) spacer having length L_lk as 8 nm, introduced only at the source side. At the drain side, we use a low-k spacer of length L_ext maintained at 20 nm. The doping segregation length is 12 nm. The conventional FinFET has a Si S/D and single low-k spacer throughout the extension length (L_ext) region from the gate edge to S/D edges. The optimized width of dual-k spacers to optimize the underlap length is considered from Pal et al.^[17], and the key process steps are considered by Anderson et al.^[18]. The fabrication methods of the asymmetric dual-k spacer are discussed by Cheng et al.^[19]. Therefore, the fabrication of the proposed device is possible. Dimensions of the proposed structure are taken and calibrated according to ITRS projection 14 nm physical gate length for I_ON and device leakage current presented in Table 1^[20]. In the proposed structure we also used SiC in place of Si at the source and drain region to produce uniaxial tensile strain at the Si channel oriented at <110> orientation as the plane of conductance. For moderate stress levels, an average channel stress can be used to estimate the performance of the transistor with a non-uniform stress distribution across the channel. In order to ignore random dopant fluctuations and to increase mobility in the channel, the underlap and channel regions are considered with a lightly doped boron concentration of 1 × 10 ¹⁶ cm^?3[21].






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Figure1.
(Color online) (a) 3-D and (b) 2-D view of the proposed asymmetric dual-k SiC S/D FinFET structure in TCAD structure editor.

Device parameter	ITRS projection value
Physical gate length (Lg)	14 nm
Eq. oxide thickness (EOT)	0.72 nm
Fin thickness (Tsi)	9.4 nm
Supply voltage (VDD)	0.75 V
Channel doping (NA)	1 × 1016 cm?3
Source/drain doping (ND)	1 × 1020 cm?3

Table1.
ITRS projections for the high-performance device in the year 2017^[20].



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Device parameter	ITRS projection value
Physical gate length (Lg)	14 nm
Eq. oxide thickness (EOT)	0.72 nm
Fin thickness (Tsi)	9.4 nm
Supply voltage (VDD)	0.75 V
Channel doping (NA)	1 × 1016 cm?3
Source/drain doping (ND)	1 × 1020 cm?3

In this work, all the simulations are performed using a density gradient model for carrier transport. The quantum potential model is enabled to include the quantum confinement effect of inversion carriers in the the thin body and also the direct tunnelling model is used to consider the gate leakages. The enhanced high-k Lombardi mobility model has been enabled to account for high-k mobility degradation at the semiconductor–insulator interface. A hydrodynamic transport model and the Hobler model was used to simulate the damage profiles^[16].

3.
Simulation results and discussion

A well-designed device has to be optimized in the domain of performance, reliability and process variation effects, so that the device will work efficiently with a long working lifetime along with the easy and reasonable fabrication cost. Hence we present the simulation study of these areas for the proposed device in the below sub sections through the medium of this paper. The device calibration is done for the experimental data available for Si S/D FinFET, whereas we are analyzing for the first time the reliability and process variation issue for SiC S/D based FinFET under following subsections.

3.1
Performance analysis of the proposed device

The capability of the Sentaurus Process (Synopsys TCAD) to recalculate the stresses in the structure due to carbon redistribution allows the simulation of the stress formation due to the silicon–carbon pockets. The longitudinal tension generated in the Si channel region breaks the symmetry of the band structure resulting in a decrease of electron effective mass along the channel. Moreover, a redistribution of the carrier to low effective mass subband valleys reduces interband scattering of electrons in the channel caused by the stress alongx and z directions. Consequently, the electron mobility increases, so does the I_ON. The piezoresistive coefficients can have dependencies with respect to the normal electric field or the mole fraction or both. Hence the stress along the channel increased by increasing mole fraction of C (y) and the mobility of electron also increases, which results in the enhancement of the drive current. At the 14 nm gate length (L_g) the variation in drive current due to variation in C mole fraction (y) in Si_1?yC_y shown by the I_d versus V_gs curve at V_ds = V_dd = 0.75 V in Fig. 2. Also, it is checked by the I_d versus V_ds curve at 0.75 V as V_gs in Fig. 3. By taking V_ds = V_gs = 0.75 V and the value of C mole fraction y in Si_1?yC_y is 0.7 in our proposed device structure. The Si_0.3C_0.7 S/D stressor considered here is approximately the largest C content such that the material is still like Si and also this amount of content is feasible from the device design context because the higher value of C can distort the lattice structure. In addition to the stressors effect, a high-k spacer at the source side helps to increase the I_ON/I_OFF and reduces the SCEs. The high-k spacers are used to increase the electric field coupling between the gate and the underlap regions, this further increases the I_ON/I_OFF; therefore, the performance of the proposed device increases. By studying the I_ds–V_ds curve for different values of V_gs shown in Fig. 4, the results demonstrate the linear region and saturation region of the proposed device. The saturation behaviour of the device degrades with scaling of the device due to different mechanisms such as SCEs and source–drain resistance. In the proposed device, we noticed less saturation degradation because of reduction in source–drain series resistance^[22].






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Figure2.
(Color online) Variation in I_d with respect to V_gs at V_ds = 0.75 V for different values of y in Si_1?yC_y.






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Figure3.
(Color online) I_d–V_ds curve of the proposed device at V_gs = 0.75 V for various values of y in Si_1?yC_y.






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Figure4.
(Color online) I_ds–V_ds curve of proposed device structure considering Si_0.3C_0.7.




The performance of the device depends on the current driving capability of the device and current driving capability depends on the mobility of charge carrier. Hence we study the variation of electron mobility along the channel for different gate length considering constant Fin thickness (T_si) of 9.4 nm shown in Fig. 5. The increase in mobility with the scaling of the device is because of the increase in the undoped or less doped region towards the S/D region; the stress effect becomes more useful for small-scale L_g. The increase in electron mobility also increases the I_ON, which is presented by comparing the log(I_ON/I_OFF) curve of the reference Si FinFET with the proposed asymmetric dual-k spacer SiC FinFET sample in Fig. 6. This also shows that the S/D stressors become adequate in introducing tensile stress when the L_g scale down.






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Figure5.
(Color online) eMobility at the centre of the channel for gate lengths (L_g) 10, 14, 18, and 22 nm at constant fin width.






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Figure6.
(Color online) Variation of log(I_ON/I_OFF) with respect to gate length (L_g).




The electron transportation near the strained Si/oxide interface for the strained Si device at the subthreshold bias provides a better gate control, and thus a smaller subthreshold swing of the proposed device is obtained as compared to the conventional device. The potential of the drain decays as the length increases, hence the subthreshold swing of both the devices decreases with the increase in L_g. It is observed that the amount of subthreshold swing (SS) of Si S/D conventional structure at L_g = 14 nm is larger even than the SS of proposed device structure at L_g = 10 nm. The reduction in SS by introducing of this novel structure of FinFET can be clearly observed from the SS versus L_g curve Fig. 7. The transconductance against the V_gs for both types of devices is shown in Fig. 8. The peak linear transconductance for the FinFET with SiC S/D is much higher compared to that of the FinFET with Si as an S/D material, indicate a higher electron mobility enhancement due to induced stress. As we show above, the variation in eMobility with the change in L_g and the transconductance is directly proportional to the eMobilty. Hence, the transconductance also increases accordingly. This is mainly because of reduction in series resistance due to strain in the Si channel and the dual-k spacers at the source side. Hence an improved transconductance is obtained which helps to improve device performance. The proposed device improves device performance, but it reduces the reliability that will affect the device yield in terms of chip lifetime. Further reliability is analysed and gives possible solutions.






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Figure7.
(Color online) Change in subthreshold swing (SS) at different gate lengths (L_g).






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Figure8.
(Color online) Variation of G_m with V_gs for the proposed and Si S/D conventional FinFETs.

3.2
Reliability analysis

The improvement in device performance is imperative, but the reliability of the device is also a crucial point that shows the device lifetime. Reliability of the device is analysed by the relaxation method, scaling of device degrades the electrical properties because hot carriers break the bond at the Si/Oxide interface and some of them are also trapped in the former bulk defects. Along with hot carrier injection (HCI), positive bias temperature instability (PBTI) is also a serious issue, it breaks the Si–H dangling bond at the Si/Oxide interface and allows the incorporation of the charge carriers in the gate oxide. To compensate these trapped charges more potential is required, this increases the threshold voltage which is shown in Fig. 9. by means of different carbon mole fraction (y) for 14 nm gate length. The effective mole fraction helps to improve the reliability shown in Fig. 9. Because it has a direct impact on strain in the Si channel, which contributes to improving the reliability and in the proposed device maximum reliability is obtained at the maximum considerable mole fraction, which is 0.7. In Fig. 10. we study the ΔV_th variation with the stress time from 0 to 3 × 10⁵ s at different temperature points to check the recovery of trap charges, and we analyse that the traps at room temperature do not recover and hence the change in V_th is large at room temperature. In the process of temperature increment from room temperature to 393 K, the detrapping rate becomes approximately equal to the trapping rate, hence the overall trapping rate becomes low and the ΔV_th decline towards a negligible amount. The varying mole faction of carbon helps to increase the reliability of the device, it can also take the advantage to reduce the practical process variation effect on the performance and the total yield of the device.






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Figure9.
(Color online) Variation in V_th with carbon mole fraction and trapped charge.






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Figure10.
(Color online) Shift in ΔV_th at different temperature levels with time.

3.3
Process variation effect

To examine the effect of process variation in the proposed device we analysed that the addition of carbon mole fraction in the Si_1?yC_y enhances the effect of process variation expressed in terms of change in eMobilty with respect to change in doping concentration at the S/D region of Arsenic from 10¹⁸ to 10²² cm^?3. It is clearly observed that the variation in eMobility is very much less for Si_0.5C_0.5 than the Si_0.3C_0.7 and Si_0.25C_0.75 up to N_D at 10²¹. It is because of sufficient carbon atoms present in the substrate and reduces the RDF in the source/drain of the device. The sequence of variation in the eMobilty is Si_0.25C_0.75 > Si _0.3C_0.7 > Si _0.5C_0.5 which is reflected in Fig. 11. This study shows that the proposed device structure has improved its performance and reliability along with a reduced process variation effect, hence it is suitable for future high yield IC fabrication.






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Figure11.
(Color online) Analysing the process variation effect by change in eMobility with S/D doping concentration for different mole fraction of C in SiC.

4.
Conclusion

In this paper, we have proposed a novel asymmetric dual-k spacer based reliable and high-performance SiC FinFET device for future IC fabrication. We also studied the performance, reliability and process variation effect of the proposed SiC S/D Asymmetrical Dual-k spacer n-type FinFET. The SiC stressor provides a longitudinal uniaxial stress in the channel region to increase the charge carrier mobility, I_ON, subthreshold slope. Hence, the large drive current is obtained at optimized SCEs at different gate lengths of 10, 14, 18, and 22 nm. In addition to this, the improved reliability is demonstrated by the PBTI analysis and the process variation effect is highlighted by the eMobility variation with the S/D doping concentration.

Acknowledgments

We are thankful to the Indian Institute of Technology Indore for providing the laboratory facility under the CSIR Grant No: 22/0651/14/EMR-II to conduct this work and we also extend our sincere thanks to the M.P. Council of Science & Technology, Bhopal, India, for financial support under the R&D project scheme No: 1950/CST/R&D/Phy & Engg Sc/2015: 27 ^th Aug 2015.