1.
Introduction
High SRAM capacity and low power dissipation are two stringent requirements for advanced computing and communication systems[1]. Ternary SRAM is an alternative technology to binary SRAM for enlarging the SRAM storage capability and improving performance. For example, a 10 × 10 ternary SRAM has about the same SRAM storage capability as a 16 × 16 binary SRAM[2]; in the ternary SRAM systems, the number of the wordline and the bitline reduce by about 33% compared to the standard 6T SRAM[3]. However, the implementation of a compact CMOS ternary SRAM requires the utilization of additional bias voltages[1], thus increasing the complexity of the power grid and producing poor area efficiency.
The carbon nanotube field effect transistor (CNFET) is one of the most promising emerging technologies to high performance ternary SRAM designs due to the tunable threshold and low OFF-current properties[4–6]. By using CNFET based cross-coupled standard ternary inverters (STIs), a number of ternary SRAM cells have been proposed[7–10]. Among them, the conventional ternary SRAM cell[8] and the novel ternary SRAM cell[9] are the most representative ones. Although the performance is somewhat promising, the ternary SRAM cells still suffer from the following drawbacks. First, there are two direct current (DC) paths when the cell is storing logic ‘1’, leading to a large DC power dissipation. Second, as a serious matter, the half-select problem[11] causes serious damage to the cell’s stability; and in the novel ternary SRAM cell, the read-disturb problem[8] reduced the cell’s read static noise margin (RSNM).
In order to solve the problems above, in this paper we propose a low standby-power fast (LSF) ternary SRAM cell which is immune to half-select and read-disturb problems. Overall, the prominent features of this work are three fold. First, the proposed cell is designed with a novel structure as the storage element to achieve lower standby-power consumption and better performance. To be more specific, when storing logic ‘1’, there is only one DC-path, and the diode connected transistors in the path making the DC-current an appropriate value. Second, the proposed cell uses a separate circuit for the read and write operation to improve the read stability. By adding a column-select transmission gate, the half-select problem is totally removed. Third, owing to the almost equally distributed static stability regions[1] of the proposed cell, the RSNM is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively. Finally, it should be noted that all the simulation results in this study are obtained by HSIPCE on a 32 nm CNFET model[12].
The rest of this paper is organized as follows. A brief review of CNFET is presented in Section 2. Two representative CNFET based ternary SRAM cells are introduced in Section 3. The proposed cell is illustrated in Section 4. Simulated results and comparisons are demonstrated in Section 5. Finally, conclusions are drawn in Section 6.
2.
CNFET
A typical structure of CNFET is illustrated in Fig. 1[1, 12]. As can be observed from the figure, a CNFET is usually manufactured by depositing Carbon Nano-tubes (CNTs) to the substrate. Typically, CNTs are nanoscale tubes, which are fabricated by rolled sheets of graphene. A CNT can be either metallic or semiconducting depending on the chirality vector (i.e., the direction in which the graphene sheet is rolled) that is usually denoted by (n, m). A CNT is metallic if n = m or n – m = 3i, where i is an integer. Otherwise, it is semiconducting. The diameter of a CNT (DCNT) is determined by the chirality vector (n, m). It is assumed that m is always zero, thus DCNT≈ 0.0783n. Since the ballistic conveys electrons along the CNT, it can be used as the channel of the field effect transistors. One of the most useful properties of the CNFET is that the threshold voltage is in inverse proportion to the DCNT as[13]
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Figure1.
Schematic diagrams of a typical carbon nanotube transistor. (a) Cross sectional view. (b) Top view.
$${V_{ m {TH}}} = frac{{0.43}}{{{D_{ m {CNT}}}({ m {nm}})}}.$$  | (1) |
Based on Eq. (1), the threshold voltage can be effectively controlled by adjusting the value of DCNT.
3.
Previous works
The structure and transistor level implementation of the conventional ternary SRAM cell[8] and the novel ternary SRAM cell[9] are shown in Fig. 2. The conventional ternary SRAM cell (shown in Fig. 2(a)) uses a transmission gate for the write operation and a read buffer for the read operation to make them separate; the basic storage element is composed of two cross-coupled STIs. The novel ternary SRAM cell (shown in Fig. 2(b)) uses a transmission gate for the write operation and a transmission gate for the read operation; the basic storage element is composed of two STIs and a transmission gate; the ON and OFF states of the transmission gate between the two STIs are used to connect or disconnect the feed-back, which can accelerate the write operation and save power to a certain extent.
From Fig. 2, we have further observations. First, there are two DC-paths (path ‘1’) when storing logic ‘1’, leading to a large DC power dissipation; and the novel ternary SRAM cell consumes more DC power than the conventional ternary SRAM cell, as the four transistors in path ‘1’ of the novel ternary SRAM cell are completely open. Second, for the write operation, they share a common shortcoming which is known as the half-select problem[11]. In such case, cells within the unselected column in the selected wordline are open access to the write bitline wbl, and naturally the cells information are under any bias to wbl, thus deteriorating the cells stability and destroying the cells information. Third, it needs to be made aware that the read disturb problem[8] cannot be ignored in the novel ternary SRAM cell. When the read transmission gate is on, the precharge voltage and noise on read bitline rbl probably change the storage node information.
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Figure2.
(Color online) CNFET based ternary SRAM cells. (a) Conventional ternary SRAM cell[8]. (b) Novel ternary SRAM cell[9].
4.
Proposed design
To solve the problems analyzed above, an alternative half-select and read-disturb free LSF ternary SRAM cell is proposed. The proposed cell uses a separate circuit for the read and write operation to improve the read stability. The structure and its corresponding transistor level implementation are shown in Fig. 3. The proposed cell consists of two transmission gates, a basic storage element, a column-select transmission gate and a read buffer. The transmission gate connected to write bitline wbl is used for the write operation and the transmission gate connected to read bitline rbl is used for the read operation. The basic storage element consists of a compact connected ternary buffer, which is composed of 1T-2B and 2B-1T. The 1T-2B is the element that transfers a ternary signal to two binary signals, whereas the 2B-1T is reverse. The logic symbols and truth table of the 1T-2B and 2B-1T are presented in Table 1, where Q3 is the storage node, Q1 and Q2 are the control nodes. Finally, the addition of the column-select transmission gate and the read buffer are used to avoid the half-select and the read disturb problems, respectively.
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Figure3.
(Color online) Proposed ternary SRAM cell. (a) Structure and its transistor level implementation. (b) Transistors operating status when storing logic ‘0’, ‘2’ and ‘1’ (black and gray represent ON and OFF, respectively).
| Logic symbol | 1T-2B | 2B-1T | |||||||
| Ternary | Binary | Binary | Ternary | ||||||
| Voltage level (V) | Logic level | Q3 | Q1 | Q2 | Q1 | Q2 | Q3 | ||
| 0 | 0 | 0 | 2 | 2 | 2 | 2 | 0 | ||
| 0.45 | 1 | 1 | 0 | 2 | 0 | 2 | 1 | ||
| 0.9 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | ||
Table1.
Logic symbols and truth table of the 1T-2B and 2B-1T.
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| Logic symbol | 1T-2B | 2B-1T | |||||||
| Ternary | Binary | Binary | Ternary | ||||||
| Voltage level (V) | Logic level | Q3 | Q1 | Q2 | Q1 | Q2 | Q3 | ||
| 0 | 0 | 0 | 2 | 2 | 2 | 2 | 0 | ||
| 0.45 | 1 | 1 | 0 | 2 | 0 | 2 | 1 | ||
| 0.9 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | ||
The basic storage element of the ternary SRAM cell consists of transistors T1–T10; they keep logic ‘0’, ‘1’, and ‘2’ when the SRAM cell is storing data. The threshold voltages of the P-type CNFETs (T1, T3, T5–T7) are ?0.549, ?0.289 and ?0.422 V [from Eq. (1)], respectively. The threshold voltages of the N-type CNFETs (T2, T4, T8-T10) are 0.686, 0.196 and 0.422 V, respectively. The storage operation can be described as follows. Storing logic ‘0’, transistors T1, T3, T7, T8, T9 are ON and the others are OFF to keep node Q3 to the value of 0; storing logic ‘2’, transistors T2, T4, T5, T6, T10 are ON and the others are OFF to keep node Q3 to the value of Vdd; storing logic ‘1’, transistors T3, T4, T5, T7, T8, T10 are ON and the others are OFF to keep node Q3 to the value of Vdd/2. In addition, we can clearly see fromFig. 3(b) that there is only one DC-path ‘1’ when it is storing logic ‘1’, and the diode connected transistors (T7–T10) in the path making the DC-current to an appropriate small value.
The write operation is performed by the write transmission gate (T17–T18) and the column-select transmission gate (T15–T16), which are controlled by the write wordline wwl and the column-select line csl, respectively. When the write wordline wwl and the column-select line csl are high, and the wwlband cslb are low, both the write transmission gate and the column-select transmission gate are open, data on the write bitline wbl is written into the selected ternary SRAM cell. As the column-select transmission gates within the unselected columns in the selected wordline are closed down, the half-selected cells are immune to the data on wbl. Therefore, the half-select problem is totally removed.
The read operation is performed by the buffer (T11–T12) and the read transmission gate (T13–T14). The read bitline rbl is precharged to ‘1’ prior to the read operation, and a ternary buffer is connected to rbl to sense the voltage at rbl. When the read wordline rwl is high and the rwlb is low, the read buffer transfers the logic state ‘0’ and ‘2’ stored in node Q3. Its operation is as follows. Node Q3 is storing a ‘0’ (i.e., both node Q1 and Q2 are ‘2’), T11 is OFF and T12 is ON, and a ‘0’ is read by the read transmission gate; node Q3 is storing a ‘2’ (i.e., both node Q1 and Q2 are ‘0’), T11 is ON and T12 is OFF, and a ‘2’ is read by the read transmission gate; node Q3 is storing a ‘1’ (i.e., node Q1 is ‘0’, node Q2 is ‘2’), both T11 and T12 are OFF and the bitline rbl remains at ‘1’. As the storing node (Q3) is separated from the read bitline rbl, the storing node is immune to the data on rbl. Therefore, the read disturb problem is totally removed. In order to further enhance the read stability, the static stability regions of the proposed cell are nearly equally designed, which is realized by using chirality vectors (8, 0) and (28, 0) for transistors T2 and T4, respectively.
5.
Simulation results and analysis
The proposed ternary SRAM cell is simulated by HSPICE on a compact 32 nm CNFET model with a 0.9 V power supply[12]. Some of the important device parameters are listed in Table 2. A 1 × 128 ternary SRAM cell array is simulated to check the functionality of the proposed SRAM cell.
| Parameter | Value | |
| Physical channel length | 32 nm | |
| Mean free path in the intrinsic CNT | 100 nm | |
| Length of doped CNT drain-side region | 32 nm | |
| Length of doped CNT source-side region | 32 nm | |
| Mean free path in p+/n+ doped CNT | 15 nm | |
| Distance between the lefts of two adjacent CNTs within the same gate | ≤ 30 nm | |
| Sub-lithographic pitch | 4 nm | |
| Thickness of high-k top gate dielectric | 4 nm | |
| Dielectric constant of high-k top gate dielectric material (HfO2) | 16 | |
| Dielectric constant of substrate (SiO2) | 4 | |
| Coupling cap between the channel region and the substrate (SiO2) | 40 aF/μm | |
| Fermi level of the doped S/D CNT | 6 eV | |
| Work function of S/D metal contacts | 4.6 eV | |
| CNT work function | 4.5 eV |
Table2.
The important device parameters of the CNFET model.
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| Parameter | Value | |
| Physical channel length | 32 nm | |
| Mean free path in the intrinsic CNT | 100 nm | |
| Length of doped CNT drain-side region | 32 nm | |
| Length of doped CNT source-side region | 32 nm | |
| Mean free path in p+/n+ doped CNT | 15 nm | |
| Distance between the lefts of two adjacent CNTs within the same gate | ≤ 30 nm | |
| Sub-lithographic pitch | 4 nm | |
| Thickness of high-k top gate dielectric | 4 nm | |
| Dielectric constant of high-k top gate dielectric material (HfO2) | 16 | |
| Dielectric constant of substrate (SiO2) | 4 | |
| Coupling cap between the channel region and the substrate (SiO2) | 40 aF/μm | |
| Fermi level of the doped S/D CNT | 6 eV | |
| Work function of S/D metal contacts | 4.6 eV | |
| CNT work function | 4.5 eV |
Fig. 4 shows the write and read operation of the proposed ternary SRAM cell to verify the valid functionality. The write delay is measured from the 50% of the write wordline wwl rising edge to the 50% of the rising/falling edge of node Q3; the read delay is measured from the 50% of the read wordline rwl rising edge to the 50% of the rising/falling edge of read_out, as shown in Fig. 4.
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Figure4.
(Color online) (a) Write and (b) read operation of the proposed LSF ternary memory cell.
The standby-power of the CNFET based memory cell is lower compared to its CMOS counterpart, as the CNFET has a significantly higher ON/OFF current ratio[8]. The statistical histogram of delay (write and read) and standby-power of the proposed ternary SRAM cell and the other two cells (conventional ternary SRAM cell[8] and the novel ternary SRAM cell[9]) are presented in Fig. 5. The proposed cell saves up to 39.6% write delay and 58.2% read delay compared to the novel ternary SRAM cell which has the minimum delay among the other two ternary SRAM cells. The average standby power of the proposed cell is reduced by 60.5% and 78.1% compared to the conventional ternary SRAM cell and the novel ternary SRAM cell, respectively.
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Figure5.
Delay and standby-power of the proposed LSF ternary SRAM cell and the other two ternary SRAM cells. (a) Write delay. (b) Read delay. (c) Standby-power.
The RSNM of the proposed cell and the other two ternary SRAM cells are presented in Fig. 6. For the STIs based ternary SRAM cell, the RSNM can be graphically found on the butterfly curve plot, by drawing the VTC of the STI and mirroring the VTC for the same plot[8]. However, this method does not apply to the proposed one, as it is not composed of STIs. It is worth noting that the Q3 node state in the proposed cell is controlled by node states of Q1and Q2. Thus, the RSNM can be represented by the voltage on node Q3 that can make the node Q1/Q2 flip. The static stability[1] of the proposed cell (shown in Fig. 6(c)) is relatively equally divided into four regions, RSNM0-1, RSNM1-0, RSNM1-2 and RSNM2-1, respectively. Among them, the RSNM0-1 represents the Q3 node voltage that can make node Q1 flip. Whereas, the RSNM1-0 is the difference between logic ‘1’ and the node voltage of Q3 that can make node Q1 flip, and is similar for the two others. The RSNM is the minimum one among the four static stability regions, and the value is 204.5 mV; as the four regions have almost equal values, the RSNM is larger than both the conventional ternary SRAM cell[8] (101.8 mV) and the novel ternary SRAM cell[9] (105.1 mV).
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Figure6.
(Color online) RSNM under process variations. (a) Conventional ternary SRAM cell[8]. (b) Novel ternary SRAM cell[9]. (c) Proposed LSF ternary SRAM cell.
A summary of the simulated performances and comparisons against other works are presented in Table 3. In order to create a fair comparison, the novel ternary SRAM cell in Ref. [9] is simulated in a 1 × 128 cells array under the same condition. From Table 3, it is clearly observed that our proposed LSF ternary SRAM cell is superior to the others in terms of average standby-power, delay and stability. Since the read and write operations are separated, there are no read-disturb problems in the proposed ternary SRAM cell; without allowing a non-selected column, it is immune to the half-select problem.
| Parameter | Ref. [14] | Ref. [2] | Ref. [8] | Ref. [9] | Proposed | ||
| Technology (nm) | CMOS 120 | CMOS 180 | CNFET 32 | CNFET 32 | CNFET 32 | ||
| Logic type | Binary | Binary | Ternary | Ternary | Ternary | Ternary | |
| Supply voltage (V) | 1.2 | 1.2 | 1.8 | 0.9 | 0.9 | 0.9 | |
| Number of transistors | 6 | 11 | 10 | 18 | 18 | 18 | |
| Write delay (ps) | ‘0’→‘1’ | × | × | 840 | 113.10 | 8.49 | 5.19 |
| ‘0’→‘2’ | 111 | 60 | 650 | 20.64 | 5.94 | 2.05 | |
| ‘1’→‘0’ | × | × | 120 | 7.19 | 3.39 | 2.44 | |
| ‘1’→‘2’ | × | × | 570 | 5.85 | 3.14 | 1.99 | |
| ‘2’→‘0’ | 111 | 60 | 160 | 10.90 | 4.54 | 2.78 | |
| ‘2’→‘1’ | × | × | 1230 | 95.91 | 9.82 | 6.89 | |
| Avg. | 111 | 60 | 595 | 42.27 | 5.89 | 3.56 | |
| Read delay (ps) | ‘0’ | 80 | 85 | 200 | 127.60 | 79.75 | 30.20 |
| ‘1’ | × | × | 3900 | 39.00 | 35.85 | 19.38 | |
| ‘2’ | 80 | 14 | 165 | 135.30 | 74.25 | 30.10 | |
| Avg. | 80 | 49.5 | 14 212 | 100.63 | 63.28 | 26.44 | |
| Standby-power (nW) | ‘0’ | N/A | N/A | N/A | 0.3515 | 0.1359 | 0.2334 |
| ‘1’ | N/A | N/A | N/A | 828.7 | 1495.5 | 326.9 | |
| ‘2’ | N/A | N/A | N/A | 0.5104 | 0.2425 | 0.4538 | |
| Avg. | N/A | N/A | N/A | 276.5 | 498.6 | 109.2 | |
| RSNM (mV) | 195* | 395* | N/A | 101.8 | 105.1 | 204.5 | |
| Read-disturb problem | Yes | No | Yes | No | Yes | No | |
| Half-select problem | Yes | Yes | Yes | Yes | Yes | No | |
| ×?Not exist; N/A?Not available; * Simulated without process variations. | |||||||
Table3.
Simulation results and comparisons with other related works.
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| Parameter | Ref. [14] | Ref. [2] | Ref. [8] | Ref. [9] | Proposed | ||
| Technology (nm) | CMOS 120 | CMOS 180 | CNFET 32 | CNFET 32 | CNFET 32 | ||
| Logic type | Binary | Binary | Ternary | Ternary | Ternary | Ternary | |
| Supply voltage (V) | 1.2 | 1.2 | 1.8 | 0.9 | 0.9 | 0.9 | |
| Number of transistors | 6 | 11 | 10 | 18 | 18 | 18 | |
| Write delay (ps) | ‘0’→‘1’ | × | × | 840 | 113.10 | 8.49 | 5.19 |
| ‘0’→‘2’ | 111 | 60 | 650 | 20.64 | 5.94 | 2.05 | |
| ‘1’→‘0’ | × | × | 120 | 7.19 | 3.39 | 2.44 | |
| ‘1’→‘2’ | × | × | 570 | 5.85 | 3.14 | 1.99 | |
| ‘2’→‘0’ | 111 | 60 | 160 | 10.90 | 4.54 | 2.78 | |
| ‘2’→‘1’ | × | × | 1230 | 95.91 | 9.82 | 6.89 | |
| Avg. | 111 | 60 | 595 | 42.27 | 5.89 | 3.56 | |
| Read delay (ps) | ‘0’ | 80 | 85 | 200 | 127.60 | 79.75 | 30.20 |
| ‘1’ | × | × | 3900 | 39.00 | 35.85 | 19.38 | |
| ‘2’ | 80 | 14 | 165 | 135.30 | 74.25 | 30.10 | |
| Avg. | 80 | 49.5 | 14 212 | 100.63 | 63.28 | 26.44 | |
| Standby-power (nW) | ‘0’ | N/A | N/A | N/A | 0.3515 | 0.1359 | 0.2334 |
| ‘1’ | N/A | N/A | N/A | 828.7 | 1495.5 | 326.9 | |
| ‘2’ | N/A | N/A | N/A | 0.5104 | 0.2425 | 0.4538 | |
| Avg. | N/A | N/A | N/A | 276.5 | 498.6 | 109.2 | |
| RSNM (mV) | 195* | 395* | N/A | 101.8 | 105.1 | 204.5 | |
| Read-disturb problem | Yes | No | Yes | No | Yes | No | |
| Half-select problem | Yes | Yes | Yes | Yes | Yes | No | |
| ×?Not exist; N/A?Not available; * Simulated without process variations. | |||||||
6.
Conclusions
In this paper, a half-select and read-disturb free LSF ternary SRAM cell has been proposed based on CNFETs. HSPICE simulation results show that the proposed cell performs the correct function during the read and write operations. It saves up to 78.1% standby-power, 39.6% write delay and 58.2% read delay compared to the novel ternary SRAM cell. As the static stability regions are almost equally distributed, the RSNM of the proposed cell is 2.01× and 1.95× of the conventional and the novel ternary SRAM cells, respectively.
