1.
Introduction

As transistors scaling into the nanoscale, self-heating effects (SHE) have become more and more severe, especially in non-planar devices such as FinFETs and nanowires due to the increased power density^[1–3] and the deteriorated heat dissipation ability^[4–7]. SHE has become a key factor concerned in device manufacture^{[8, 9]} and circuit design^{[10, 11]}. SHE can lead to serious device performance degradation and reliability problems^{[12, 13]}. Many works^[14–16] have investigated and characterized SHE in semiconductor devices experimentally and theoretically. The performance of semiconductor devices is sensitive to ambient temperature (T_A). When T_A increases, the improvement in electrostatic properties^[17] and the degradation in carrier transport^{[18, 19]} occur simultaneously, which make it complicated to study the SHE. The energy relaxation time in silicon is 0.8 ps^[20]. The electron energy-relaxation-length can be 80 nm when considering the saturation velocity in silicon 10⁷ cm/s. Therefore, in nanoscale devices, many thermal non-equilibrium carriers can reach the drain end and take away a part of input power into MOL and BEOL^[21], which have an impact on the heat generation in devices. Monte Carlo (MC) simulation can perform the behaviors of thermal non-equilibrium carriers and get the non-local heat generation, which is more accurate than traditional continuum simulation methods^{[7, 22]} in describing nanoscale devices^[1].



In this work, we use a well-established electro-thermal Monte Carlo simulation framework to investigate SHE in 14 nm-node FinFETs with T_A from 220 to 400 K^[23]. Impurity freeze-out effects do not happen in this T_A range^[24]. We first investigate the heat generation under different operating voltages. Then we further explain the existence of serious non-equilibrium transport by investigating thermal power densities. What is more, we investigate the impact of T_A on current degradation, ballistic factor degradation caused by SHE and the thermal resistances. This work indicates the importance of T_A in studying SHE in nanoscale devices.

2.
Device structure and simulation method

Fig. 1 shows the device structure of the 14 nm-node Si bulk nFinFET^[25] used in this work. HfO₂/TiAlN is utilized as the high-k/metal-gate in nFinFET. The device parameters are listed in Table 1^{[25, 26]}.

Strcuture parameter	Description	Value
Hsd	Raised S/D height	52 nm
Hstop	Stop layer height	40 nm
Hsub	Substrate layer height	4 μm
Hfin	Fin height	42 nm
Lsd	Raised S/D length	20 nm
Lext	S/D length	10 nm
Lg	Gate length	20 nm
Wpitch	Fin pitch	42 nm
Wfin	Fin width	8 nm
Nchannel	Channel doping, p type	1 × 1015 cm?3
Nstop	Stop layer doping, p type	2 × 1018 cm?3
Nsd	Source/Drain doping, n type	1 × 1020 cm?3
Nsub	Substrate doping, p type	1 × 1015 cm?3
EOT	Equivalent oxide thickness	0.85 nm
Tox	Gate oxide thickness	5.4 nm

Table1.
Structure parameters of the 14 nm-node nFinFET.



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Strcuture parameter	Description	Value
Hsd	Raised S/D height	52 nm
Hstop	Stop layer height	40 nm
Hsub	Substrate layer height	4 μm
Hfin	Fin height	42 nm
Lsd	Raised S/D length	20 nm
Lext	S/D length	10 nm
Lg	Gate length	20 nm
Wpitch	Fin pitch	42 nm
Wfin	Fin width	8 nm
Nchannel	Channel doping, p type	1 × 1015 cm?3
Nstop	Stop layer doping, p type	2 × 1018 cm?3
Nsd	Source/Drain doping, n type	1 × 1020 cm?3
Nsub	Substrate doping, p type	1 × 1015 cm?3
EOT	Equivalent oxide thickness	0.85 nm
Tox	Gate oxide thickness	5.4 nm

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Figure1.
(Color online) The 14 nm-node Si bulk nFinFET structure used in this work.




Fig. 2 shows the electro-thermal simulation framework used in this work. Our in-house three-dimensional (3D) full-band ensemble MC simulator^{[27, 28]} and 3D Fourier heat conduction equation solver are used to perform the electro-thermal simulation. In this work, the operating voltage is less than 1 V. Therefore, the energy of most carriers is smaller than the bandgap of silicon (1.12 eV) and the generation–recombination (G–R) process can be ignored^[17]. Only the heat generation from the carrier-phonon scatterings is taken into account. Thermal convection is not considered inside the solid-state devices and thermal radiation can be ignored due to the non-existence of the G–R process in this situation. We only utilize heat conduction to obtain the spatial temperature distribution.






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Figure2.
(Color online) Electro-thermal simulation framework used in this work.




The simulation flow begins with a self-consistent MC simulation at a user-defined T_A, which is to achieve the steady electric profiles including potential profile and carrier profile, which are results without SHE. After that, a fixed-potential MC simulation is performed based on the steady electric profiles to achieve heat spatial distribution, which can eliminate errors from unphysical oscillations due to the MC nature in the self-consistent mode. The heat profile is achieved by counting the phonon emission (E_em) and absorption (E_ab), which is then sent to the heat conduction equation solver to achieve the temperature profile. To achieve the electric profiles with SHE, the temperature profile is then fed back to a new MC simulation with the same operating voltages to get the degraded electric properties where electric profiles in the previous loop are used as the initial condition. Steady results with SHE can be achieved after 2–3 times coupling loops.



The full band structure of silicon is considered in our MC simulator. It is obtained by the empirical pseudopotential calculation including spin-orbit interactions. Besides, main scattering mechanisms including acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are involved, which are verified and calibrated in Refs. [29, 30].



The carrier-phonon scatterings are calculated according to Ref. [31]. The inter-valley acoustic phonon scatterings are treated in accordance with the optical phonon scatterings with constant deformation potentials, which are expressed in Eq. (1). The corresponding information of inter-valley acoustic phonons and optical phonons are listed in Table 2.

$$begin{split}{S_{text{η} , ,,{ m b}', ,,{ m b}}}left( {{ {k}'} { m{|}} { {k}}} ight) = frac{pi }{{{ m{Omega }}varrho {omega _eta }}}{left( {{D_t}{K_eta }} ight)^2}left( {nleft( {hbar {omega _eta }} ight) + frac{1}{2} pm frac{1}{2}} ight)delta left( {{epsilon _{ m b'}}left( {{ {k}'} } ight) - {epsilon _{ m b}}left( { {k}} ight),, pm,, hbar {omega _eta }} ight)rleft( {eta ,nu left( {{ {k}'} } ight),nu left( { {k}} ight)} ight),end{split}$$

(1)

where Ω and ? are the normalized volume in k space and the mass density of silicon, respectively. η represents the phonon type. ω_η is the wave vector of phonons. $hbar $ω_η is the phonon energy, which is the source of heat generation. D_tK_η is the deformation potential constant. n($hbar $ω_η) is the number of phonons in the Bose-Einstein distribution, which is sensitive to temperature. $rleft( {eta ,nu left( {{k}' }
ight),nu left( { {k}}
ight)}
ight)$ is the selection rule function to select the phonon type and the parameters needed in the phonon scattering, which is listed in Table 2.

η	Phonon type	DtK (1010 eV/m)	$ hbar omega $ (meV)	r
1	TA	0.47	12.1	g
2	LA	0.74	18.5	g
3	LO	10.23	62.0	g
4	TA	0.28	19.0	r
5	LA	1.86	47.4	r
6	TO	1.86	58.6	r

Table2.
Optical phonon and inter-valley acoustic phonon in silicon.



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η	Phonon type	DtK (1010 eV/m)	$ hbar omega $ (meV)	r
1	TA	0.47	12.1	g
2	LA	0.74	18.5	g
3	LO	10.23	62.0	g
4	TA	0.28	19.0	r
5	LA	1.86	47.4	r
6	TO	1.86	58.6	r

The intra-valley acoustic phonon scattering is regarded as an elastic scattering due to its small phonon vector, which is expressed in Eq. (2).

$${S_{text{η} ,,,{ m b}',,, { m b}}}left( { {k'} { m{|}}{ k}} ight) = frac{{2pi {K_{ m B}}T{{ m{Xi }}^2}}}{{{ m{Omega }}hbar varrho {u^2}}}delta left( {{epsilon _{{ m b}'}}left( { {k'} } ight) - {epsilon _{ m b}}left( { k} ight)} ight){delta _{nu left( { {k'} ,,, { k}} ight)}},$$

(2)

where the deformation potential Ξ is 8.37 eV and the phonon group velocity is u = 9050 m/s for longitudinal phonons and 5230 m/s for transversal phonons. K_B and $hbar $ are the Boltzmann constant and Planck constant respectively. T is temperature.



The impacts of temperature on electrostatic properties and carrier transport are well considered in our simulator, which can be seen in Fig. 3.






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Figure3.
(Color online) (a) Intrinsic carrier density versus temperature. Data in Ref. [17] is shown for comparison. (b) Electro-phonon scattering rate versus kinetic energy at different temperatures. Data at T_A = 300 K in Ref. [18] is shown for comparison.




It is difficult to analyze thermal issues in modern packaged ICs due to the complicated interconnects and package structures^[32]. To solve this problem, thermal analysis in components of modern ICs are widely advancing by abstracting the other components into proper boundary conditions, such as thermal analysis in interconnects^{[32, 33]}, package structures^{[34, 35]} and devices^{[7, 22]}. In the thermal analysis of our work, the impacts of interconnect, package structure and substrate on devices are abstracted as the impact of T_A. In the simulated structure, the source (S), drain (D), gate (G) and substrate (B) are the four main heat dissipation paths while other boundaries are adiabatic. Si/Metal contact thermal resistance^[36] is used at the S/D/B contact. The summation of Si/metal contact thermal resistance and Si/SiO₂ contact thermal resistance^[37] is used at the G contact. The essential thermal parameters are listed in Table 3^[36–41]. The area of four contacts respectively are H_sdW_pitch for S/D, (2H_fin + W_fin + 4T_ox)L_g for G and (2L_sd + 2L_ext + L_g)W_pitch for B. The final heat flux percentages of the four heat dissipation paths are 61.23% (D), 21.85% (S), 8.63% (G) and 8.29% (S) when V_gs = V_ds = 0.7 V, T_A = 300 K, which meets the heat dissipation requirement of a normal working device^{[32, 42]}.

Silicon thermal conductivity (anisotropic)
ky in Region (1–6)	15 Wm?1K?1
kx, kz in Region (1–6)	10 Wm?1K?1
Silicon thermal conductivity (isotropic)
k in Region (7)	148 Wm?1K?1
Oxide thermal conductivity (isotropic)
Trench oxide (SiO2)	1.4 Wm?1K?1
Gate oxide (HfO2)	1.1 Wm?1K?1
Contact thermal resistance
Gate	2.5 × 10?4 cm2K/W
Source/Drain/Substrate	0.5 × 10?4 cm2K/W

Table3.
Thermal parameters used in this work.



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Silicon thermal conductivity (anisotropic)
ky in Region (1–6)	15 Wm?1K?1
kx, kz in Region (1–6)	10 Wm?1K?1
Silicon thermal conductivity (isotropic)
k in Region (7)	148 Wm?1K?1
Oxide thermal conductivity (isotropic)
Trench oxide (SiO2)	1.4 Wm?1K?1
Gate oxide (HfO2)	1.1 Wm?1K?1
Contact thermal resistance
Gate	2.5 × 10?4 cm2K/W
Source/Drain/Substrate	0.5 × 10?4 cm2K/W

Fig. 4 shows the simulated and experimental^[25] I_ds–V_ds curves of the 14 nm-node FinFET, which indicates that the MC results can well reproduce the experimental data.






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Figure4.
(Color online) Calibration of 14 nm-node Si nFinFET simulation results with DC experimental data.

3.
Results and discussions

3.1
Heat generation

Fig. 5 shows the average electron energy distribution along the transport direction at V_gs = 0.7 V, V_ds = 1 V and T_A = 300 K. It clearly demonstrates the existence of thermal non-equilibrium carriers at the drain end. A part of input power can be carried out by the thermal non-equilibrium carriers, which can eventually heat up MOL and BEOL.






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Figure5.
(Color online) The average electron energy distribution along the transport direction at V_gs = 0.7 V, V_ds = 1 V and T_A = 300 K. The thermal equilibrium carrier energy is 1.5 K_BT (0.0389 eV).




Fig. 6(a) shows the input power Q_input and the heat generation Q_heat under different V_ds at T_A = 220, 300, and 400 K. Here V_gs keeps 0.7 V. Q_input is calculated as I_dsV_ds and Q_heat is the total heat generation in the device region by counting the energy exchanged in electron-phonon interactions as in the phonon’s perspective. The figure shows that T_A has little impact on the Q_input in this situation, which is the result of the compensation of the increased carrier density and the degenerated carrier transport^[43]. However, the Q_heat is larger at a higher T_A, which is due to more serious electron–phonon interactions at a higherT_A. Fig. 6(b) shows the corresponding ratios of Q_heat in Q_input. The ratio decreases with the increasing V_ds. Under the same V_ds, a higher T_A leads to a larger ratio of input power turning into heat generation, which can lead to more serious SHE. With V_gs = 0.7 V, V_ds = 0.7 V at T_A = 300 K, the ratio is 67.7% and it implies that 32.3% of Q_input is carried out of the device region by thermal non-equilibrium carriers. When V_gs = 0.7 V and V_ds = 1 V at T_A = 220 K, the energy carried out by thermal non-equilibrium carriers can rise up to 40.9% of Q_input due to less electro–phonon interactions.



Fig. 7(a) shows the Q_input and Q_heat under different V_gs at T_A = 220, 300, and 400 K. Here V_ds keeps 0.7 V. The impact of T_A on Q_heat becomes smaller with the increase of V_gs. Fig. 7(b) shows the corresponding ratios of Q_heat in Q_input. The ratio decreases with the increasing V_gs. When V_gs = 1 V and V_ds = 0.7 V at T_A = 220 K, the ratio is 47.9% and 52.1% of Q_input is carried out of the device region by thermal non-equilibrium carriers. Both Figs. 6 and 7 indicate the existence of serious non-equilibrium transport in 14 nm-node FinFETs that should be necessarily concerned.






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Figure6.
(Color online) (a) The input power Q_input and heat generation Q_heat under different V_ds and (b) the corresponding ratios of Q_heat in Q_input at T_A = 220, 300, 400 K and V_gs = 0.7 V.






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Figure7.
(Color online) (a) The input power Q_input and heat generation Q_heat under different V_gs and (b) the corresponding ratios of Q_heat in Q_input at T_A = 220, 300, 400 K and V_ds = 0.7 V.

3.2
Impact of ambient temperature on SHE

The SHE of the 14 nm-node FinFET at different T_A is evaluated. The temperature distributions with the corresponding power densities along the transport direction at T_A = 220, 300, and 400 K are investigated. Comparisons of results at V_ds = 0.7 V with V_ds = 1 V under the same V_gs are shown in Figs. 8(a) and 8(b), and the comparisons of results at V_gs = 0.7 V with V_gs = 1 V under the same V_ds are shown in Fig. 8(c) and 8(d). From Figs. 8(a) and 8(b), we can see that the change of T_A leads to a larger difference in power density and temperature distribution at a larger V_ds, which reveals a more serious non-equilibrium transport exists at a larger V_ds. On the contrary, the change of T_A leads to a smaller difference at a larger V_gs, which is shown in Figs. 8(c) and 8(d). It indicates that there is a smaller difference in the non-equilibrium transport at a larger V_gs under different T_A. The increase of V_gs primarily increases the carrier density in the inversion layer.






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Figure8.
(Color online) (a) The average augments of lattice temperature and (b) the power densities along the transport direction comparing V_ds = 0.7 V and V_ds = 1 V at V_gs = 0.7 V, (c) the average augments of lattice temperature and (d) the power densities along the transport direction comparing V_gs = 0.7 V and V_gs = 1 V at V_ds = 0.7 V. T_A = 220, 300 and 400 K.




Fig. 9(a) shows the current densities with and without SHE with different V_ds at V_gs = 0.7 V, T_A = 220, 300, and 400 K and the corresponding current degradation percentages are shown in Fig. 9(b). The current degradation increases with the increase of V_ds. We can see that the current degradation is larger at a higher T_A, which indicates a more serious SHE. When V_gs = 0.7 V, V_ds = 0.7 V and T_A = 300 K, the current degradation percentage is 2.5% and it can be 3.5% when T_A = 400 K. Once V_gs = 0.7 V, V_ds = 1 V and T_A = 400 K, the current degradation percentage can be 4%.






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Figure9.
(Color online) (a) Comparison of current densities considering SHE with those not considering SHE under different V_ds and (b) the corresponding current degradation percentages caused by SHE at T_A = 220, 300, 400 K and V_gs = 0.7 V.




Fig. 10(a) shows the current densities with and without SHE under different V_gs at V_ds = 0.7 V, T_A = 220, 300, and 400 K. The corresponding current degradation by SHE is shown in Fig. 10(b). The current degradation increases with the increase of V_gs. When V_gs = 1 V, V_ds = 0.7 V and T_A = 400 K, the current degradation can reach to 8.9%, which implies serious SHE.



Due to its more serious SHE, we then choose the situation with fixed V_ds and different V_gs to continue our investigation.



The definition of ballistic factor is as follows^[44]:

$${B_{ m {sat}}} = frac{{{I_{ m {ON}}}}}{{{I_{ m {BL}}}}},$$

(3)

where I_BL is the ballistic current with no scattering events in the channel and I_ON is the normal device current with scattering events in the channel.



B_sat = 1 represents the full ballistic transport and smaller B_sat means more scattering events happening in the channel. Fig. 11(a) shows B_sat with and without SHE under different V_gs at T_A = 220, 300, 400 K and V_ds = 0.7 V. SHE leads to the increase of the local lattice temperature, which can lead to more scattering events and a smaller B_sat. This is clearly shown in Fig. 11(a). SHE can weaken the non-equilibrium transport to be more diffusive. Fig. 11(b) shows the degradation percentage of B_sat. The absolute value of B_sat degradation percentage increases with the increase of V_gs and it is larger at a larger T_A when considering the same V_gs. It also indicates that SHE is more serious at a larger T_A.






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Figure11.
(Color online) (a) Comparison of ballistic factor B_sat considering SHE with that not considering SHE under different V_gs and (b) the corresponding degradation percentages of B_sat by SHE at T_A = 220, 300, 400 K and V_ds = 0.7 V.




Fig. 12 compares the υ_inj and Q_top at ToB with different V_gs with and without SHE at T_A = 220, 300, 400 K and V_ds = 0.7 V. It shows that comparing with υ_inj, Q_top is less affected by T_A and the difference becomes smaller with the increasing V_gs. SHE can lead to a prominent degradation in υ_inj and the degradation is much larger at a larger T_A at the same V_gs. Therefore, the degradation in current is mainly caused by the degradation in υ_inj, which can explain the results in Fig. 10(b).






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Figure10.
(Color online) (a) Comparison of current densities considering SHE with those not considering SHE under different V_gs and (b) the corresponding current degradation percentage by SHE at T_A = 220, 300, 400 K and V_ds = 0.7 V.






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Figure12.
(Color online) (a) Injection velocity υ_inj and (b) sheet density Q_top at the top of barrier ToB^[45] under different V_gs with and without SHE at T_A = 220, 300, 400 K and V_ds = 0.7 V.




The relationship of T–T_A with Q_input is shown in Fig 13(a). Results at T_A = 220, 300, and 400 K when V_ds = 0.7 V are presented. T_peak–T_A and T_average–T_A increase with increasing of Q_input. At the same Q_input, we can see that T_peak–T_A and T_average–T_A increase with the increase of T_A. When Q_input = 90 μW at T_A = 300 K, T_peak–T_A is 100 K and T_average–T_A is 75 K. The relationship of the device thermal resistance (R_th) with Q_input is shown in Fig 13(b). We can see that R_th decreases with the growth of Q_input. Besides, a larger R_th is found at a larger T_A when considering the same Q_input. The probability of electron-phonon scattering is much larger at a larger T_A. Electron-phonon scattering are an inelastic scattering and by experiencing this scattering, particles will exchange their energy to the lattice. A larger T_A will lead to a larger part of Q_input turning into Q_heat and an increasing T_peak–T_A. Therefore, the R_th increases with T_A increases. The difference in R_th at different T_A becomes smaller with the growth of Q_input, which is the result of the undistinguished heat density distribution shown in Fig. 5(a). To characterize SHE in nanoscale devices, the modeling on R_th at different T_A is necessary in the device SHE investigation.






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Figure13.
(Color online) The relationship of (a) T–T_A and (b) thermal resistance R_th with Q_input at T_A = 220, 300, 400 K when V_ds = 0.7 V. T_peak and T_average respectively refer to the peak lattice temperature and the average lattice temperature.




Fig. 14 shows the average augment of lattice temperature at the gate oxide region (T_gate–T_A). T_peak–T_A is plotted for comparison. Results with T_A = 220, 300, and 400 K under different V_gs at V_ds = 0.7 V and different V_ds at V_gs = 0.7 V are presented. In actual application, a temperature sensor is often placed at the gate top to achieve device temperature^[46], which actually is T_gate. It shows that T_gate–T_A increases with the increasing of T_A. We can see that T_A will have a serious impact on the results achieved by the temperature sensor. Therefore, the impact of T_A should not be ignored.






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Figure14.
(Color online) The average augment of lattice temperature at the gate oxide region (T_gate–T_A) with T_A = 220, 300 and 400 K (a) under different V_gs at V_ds = 0.7 V and (b) under different V_ds at V_gs = 0.7 V. T_peak–T_A is plotted for comparison.

4.
Conclusion

The impacts of T_A on SHE in 14 nm-node nFinFETs are investigated in this work. Our electro-thermal coupled Monte Carlo simulation framework is useful to achieve the impact of the non-equilibrium transport and the non-local heat generation, which is important in analyzing SHE in nanoscale devices. The thermal non-equilibrium carriers carry out a part of Q_input, which eventually heats up the MOL and BEOL. An increase in V_gs can prominently increase heat generation in the channel and the drain side. However, an increase in V_ds only results in an obvious heat generation increment in the drain side. The increase in T_A can lead to more serious SHE, including a higher device temperature and larger degradation in current, ballistic factor and injection velocity, which are results of a larger heat generation in the device region. The increase in T_A can lead to an increment of the device thermal resistance. The impact of T_A should be carefully considered when investigating SHE in nanoscale devices.