1.
Introduction
Recently, passive ultra high frequency (UHF) radio frequency identification (RFID) has been considered as one of the most promising technologies for the advantages of small size, high data rate, and long operating distance[1, 2]. It is mainly used in the domain of monitoring, localization, and supervision[3], such as medicine management, logistics, and wireless sensing[4, 5].
RFID tag chips consist of three functional modules, namely, analog front-end, digital baseband, and non-volatile memory[6]. The analog front-end converts the received RF signals into stable DC voltage and digital data from the reader. Then, the power-on-reset (POR) signal and clock for digital baseband will be generated when the power supply is steady. The digital baseband manipulates the received data and outputs the response data. All required data are stored in non-volatile memories. Passive UHF RFID tags are entirely powered by the electromagnetic signal generated by the UHF RFID reader[7]. Some time is required for the power supply to reach a reliable, regulated level. During this period, the digital baseband needs to remain off, until receiving a start signal, which is provided by the POR circuit. A POR circuit provides a reset pulse to the baseband after the power supply reaches the operating voltage so that the baseband always functions correctly[8, 9].
In this paper, an ultra-low power POR circuit with simple architecture, self-adjustable delay time of reset pulse, and small capacitances is proposed for passive RFID tags. Section 2 analyses some conventional POR circuits and their problems. Section 3 explains the proposed circuit and its details. In Section 4, the simulation results and comparison with other papers will be presented. Finally, the conclusion of this paper will be given in Section 5.
2.
Conventional POR circuits
The conventional POR circuits usually include a delay unit and a pulse generation unit.
The circuit in Fig. 1(a)[10] consists of the RC network as the delay element and some logic devices as the pulse generator, which can change the rising edge into a low pulse. The fixed values of capacitance and resistance in the circuit result in fixed delay time, so that when the rising time of the power supply is long, the reset pulse may be generated before the power reaches its final value, which may cause system malfunction. Furthermore, the RC network requires large resistance and large capacitance to achieve the proper delay time. However, large capacitances and resistances are not allowed for the on-chip system due to limited chip areas[9]. Reference[11] proposed capacitor scale-up techniques to solve the large capacitance value issue. Unfortunately, it is not easy to be applied on POR circuits, because the steady power supply needed by the technique above clearly cannot be achieved during the power-up time[12]. Moreover, the capacitance can be charged by the power supply with a biased NMOS as the delay element[13], which has the same defect as the RC network mentioned above.
Fig. 1(b)[14, 15] shows another conventional POR circuit, which uses a diode-connected PMOS transistor and a biased PMOS transistor in series instead of the resistance in Fig. 1(a). This delay structure avoids large chip areas of resistances, and the diode-connected PMOS determines the voltage when the capacitor starts to be charged. Additionally, the capacitance protects the circuit from parasitic oscillations[16]. The pulse generator is composed of cross coupled inverters and a NOR gate. When power is up, both node A and node B are at a low level before the capacitor is fully charged, which leads to the high level of NOR gate output. Then either node A or node B shifts to a low level, and the output of the NOR gate becomes opposite. This process results in a high pulse as the reset signal. However, the rising edge of the high pulse is synchronized with power up, so we can only get a falling edge after power-on, instead of a reset pulse. Reversing the signal above by an inverter will not help either, for it can only change the ‘fake pulse’ into a rising edge. In this circuit, the application scope is limited because it is unable to generate a reset pulse after power-on.
Fig. 1(c)[12] shows the delay element includes a current generator, which consists of three diode-connected PMOS, and cascaded current mirrors. This circuit allows the power supply to charge the capacitance with low current to extend the delay time, instead of using a large capacitance. However, the current generator will keep generating currents during the entire powered period, causing static power consumption.
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Figure1.
Schematic of a conventional POR circuit.
Moreover, some circuits[17, 18] generate a reset pulse by a comparator, which results in a complex circuit structure.
A good POR circuit for passive RFID tags requires these very features. Static power consumption must be limited to a relatively low level, because the power supply of the chip is converted from an electrical wave, which is not unlimited. The delay time of the delay element should be able to widely self-adjust according to the rising time of the power supply. The chip area must be as small as possible. Finally, the reset pulse width must be longer than two or three clock cycles.
3.
Proposed novel POR circuit
Fig. 2 shows the diagram of the proposed POR circuit. This circuit is composed of two cascade delay elements, and four inverters. One of the inverters, INV3, is connected as a two-inputs logic gate, which is shown in Fig. 3.
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Figure2.
Diagram of the proposed POR circuit.
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Figure3.
Special connection and logic function of an inverter.
A schematic of the delay element[19] is shown in Fig. 4. Ideally, as the power supply gradually rises, the capacitance C1 couples the rising power supply voltage to node A, and the gate to the source voltage of the PM1 (Vgs1) remains zero. Since node A keeps rising and node B stays zero, the gate to source voltage of PM2 is gradually falling. Then, node A is discharged through PM2 by the subthreshold current at first and then the drain current. As a result, Vgs1 drops, and the capacitance C2 starts to be charged, leading to the delayed supply voltage signal. The delay time can be adjusted by modifying the PMOS sizes and capacitance values, or even cascading the delay element. The circuit has unique features including small values of capacitances and the ability to operate at a wide rising time of the power supply, and it can be cascaded to extend the delay time.
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Figure4.
Schematic of the delay element.
The proposed POR circuit is shown in Fig. 5. The first delay element Delay1 consists of three capacitances, i.e., C1, C2, C3, and three PMOS transistors, i.e., PM1, PM2, PM3. The extra pair of capacitance and PMOS equivalently improves the threshold voltage of PM1 in Fig. 4, for the reason of extending delay time. The second delay element Delay2 is composed of PM4, PM5, and C4, C5 with lower capacitance values compared with C1, C2, C3. The first inverter INV1 consists of one PMOS transistor and two NMOS transistors. It can detect whether the input voltage reaches a certain value, and then outputs a step signal. The certain voltage value above can be increased by diode-connected NMOS transistor NM2. INV2 is used for wave shaping. Similarly, INV3 has the same components as INV1, but the inverter power is supplied by a step signal delayed in power supply, to form a special two-input logic gate. The final inverter reverses and shapes the received signal and improves the drive capability of the POR signal.
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Figure5.
Schematic of the power-on-reset circuit.
The operation process of the circuit is shown as below. Initially, the delayed power supply signal is shaped from a ramp signal, i.e., D1 into a step signal, i.e., S1 by INV1 and INV2. Then, INV3 generates a high pulse by twice-delayed power supply signal D2 and pre-obtained signal S1 as inputs, following the logic shown in Fig. 3. Finally, INV4 reverses the high pulse into a low pulse, as the POR signal. The signal diagram of the POR circuit is shown in Fig. 6.
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Figure6.
Signal diagram of the POR circuit.
Since the POR circuit is designed for passive RFID tags, the power consumption of the POR circuit should be as low as possible. Normally, the power consumption includes dynamic power and static power. The dynamic power is composed of the short-circuit current during the inverter being turned over and the dissipation due to charging and discharging capacitances, and static power is mainly formed by the sub-threshold current of the branches. In the circuit proposed in this paper, no direct path between the power supply and the ground leads to zero static power consumption. So, the solution of the power issue should be focused on losing dynamic power consumption.
The dissipation due to charging and discharging capacitances Edyn can be calculated as
${E_{{ m{dyn}}}} = frac{{{C_{ m{L}}}V_{{ m{DD}}}^2}}{2} {n_{0 - 1}},$  | (1) |
with the number of output changing from low level to high level n0-1, and the load capacitance CL, and the supply voltage VDD, respectively. In this case, VDD is a determined value 1.8 V, and n0-1 also cannot be changed, but CL, which represents the parasitic capacitance of the next-stage device, fortunately can be reduced by reducing the size of devices.
The dissipation due to direct-path current Edp is
${E_{{ m{dp}}}} = {t_{{ m{sc}}}}{V_{{ m{DD}}}}{I_{{ m{peak}}}},$  | (2) |
where tsc represents the time the short-circuit current exists, and Ipeak is determined by the saturation current of MOS transistors. Ipeak can be reduced by using MOS transistors with smaller width to length ratio.
4.
Simulation results
The design and simulation were based on Cadence IC615 and MMSIM141, implemented in SMIC 0.18 μm RF technology.
Fig. 7 shows simulation results of power-on-reset signal output of the circuit with different rising times of power supply. When the power-on time is 0.01 μs, the reset signal is delayed by 0.59 μs and the pulse width is 1.25 μs, as shown in Fig. 7(a). Similarly, as shown in Figs. 7(b) and 7(c) the reset signal is delayed by 0.88 and 0.49 μs, and the pulse width is 2.05 and 29.03 μs when the power-on time is 1 and 100 μs, respectively. The values of the points that we choose as the end of the pulse are not 1.8 V (1.712, 1.698, and 1.733 V), because it is high enough to be considered as a ‘1’ by the digital baseband, and it will reach the power supply voltage as 1.8 V eventually. A pair of invertors can improve the waveform of the POR output, with additional dynamic consumption. For the sake of low-power design, we chose not to. As mentioned in the description of the delay element (Fig. 4), the delay time of the POR signal can be adjusted by the capacitance and W/L of the PMOS in the first delay element, which means that we can increase the capacitance or reduce the W/L of PMOS if the delay times in Fig. 7 are not long enough. Results show that the proposed POR circuit operates properly over wide ranges of rising time of power supply with appropriate delay times and pulse widths. In other words, the reset pulse is always generated after the power supply stabilizes at its final value, compared with a conventional POR circuit with the RC network.
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Figure7.
Simulation results of POR signal output with (a) 0.01 μs, (b) 1 μs, and (c) 100 μs rising times of power supply.
The proposed POR circuit shows a different delay time and pulse width under different process corners. As shown in Fig. 8, the delay times in different process corners are 0.45, 0.88, and 2.17 μs, and the pulse widths are 1.00, 2.05, and 5.93 μs, when the corners are fast NMOS fast PMOS model (ff), typical model (tt), and slow NMOS slow PMOS model (ss), respectively. The delay times and pulse widths are long enough for the baseband.
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Figure8.
Simulation results of POR signal output with 1 μs rising time of power supply under ff, tt, and ss corners.
Fig. 9 shows the results of multiple POR signals. The delay time of the second POR signal was reduced from 2.64 to 1.97 μs and the pulse width was reduced from 7.78 to 1.76 μs. The delay time and pulse width of the third POR signal are 2.11 and 1.80 μs, which are close to the second one’s. The results above indicated that the POR circuit has the ability to regenerate a POR signal after the power supply is briefly powered off.
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Figure9.
Simulation results of POR signal after power supply is briefly powered off.
Fig. 10 shows the simulation results of the circuit power consumption when the rising time of the power supply is 10 μs. The dynamic power consumption has a maximum value of 4.59 μA on the falling edge and 2.60 μA on the rising edge of the reset pulse. It is quite acceptable, since the digital baseband has not yet operated.
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Figure10.
Simulation results of power consumption with 10 μs rising time of power supply.
Fig. 11 shows the simulation results of static current curve, indicating that the static power consumption is 29.5 pA with the 1.8 V supply voltage. It is low enough to be considered as zero static power consumption.
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Figure11.
Simulation results of static power.
The simulation results of the passive RFID analog front-end with the proposed POR circuit are shown in Fig. 12. The waveform of the input RF signal and outputs of voltage regulator, POR signal generator, clock generator, and demodulator, indicate that the analog front-end, including the POR circuit operates properly. The 900 MHz RF input signal with ASK modulated digital data, is converted into DC voltage as the power supply of the chip, and demodulated as the input signal of the digital baseband. Meanwhile, the POR signal and the 2 MHz clock signal are generated when the power supply reaches the steady value.
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Figure12.
Simulation results of analog front-end.
Table 1 shows the comparison with other published POR for passive RFID tags.
| Parameter | Ref. [20] | Ref. [12] | Ref. [14] | Ref. [18] | This work |
| Supply voltage (V) | 1.0 | 1.8 | 1.0 | 1.0 | 1.8 |
| POR self-adjust according to PO | No | No | No | Yes | Yes |
| Quiescent current (nA) | 150 | 1000 | 345 | 5000 | 0.0295 |
Table1.
Comparison with other published POR for passive RFID tags.
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| Parameter | Ref. [20] | Ref. [12] | Ref. [14] | Ref. [18] | This work |
| Supply voltage (V) | 1.0 | 1.8 | 1.0 | 1.0 | 1.8 |
| POR self-adjust according to PO | No | No | No | Yes | Yes |
| Quiescent current (nA) | 150 | 1000 | 345 | 5000 | 0.0295 |
5.
Conclusion
This paper presents a novel POR circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of the reset pulse. Simulation results show that the circuit functions well under different process corners with a wide rising time of the power supply from 0.01 to 100 μs. The circuit can generate a POR signal after the power supply is briefly powered off and operates properly in the RFID analog front-end. The power consumption of the circuit is acceptable for passive RFID tags.
