1.
Introduction
Bandgap reference (BGR) circuits are essential blocks for high voltage gate driver integrated circuits (HVIC), and the voltage accuracy plays a significant role in determining the performance of all subsequent circuits which depend on an accurate and stable reference[1, 2]. Any variations in the reference voltage will directly affect the performance of the overall system. Since the HVICs work under the wider temperature range, developing a temperature-compensated reference is crucial.
In order to achieve high-precision CMOS reference, several curvature compensation techniques have been developed in Refs. [3–8]. The piecewise-linear curvature-compensation technique has been proposed in Refs. [3–6]. In these approaches, a nonlinear curvature-corrected current is generated and added to the output of a first-order BGR when the operating temperature is higher than a pre-determined value, but the accuracy is limited at a wider temperature range. In Ref. [7], high-order nonlinearities are cancelled by incorporating two different types of resistors with opposite TC. However, intensive trimming is needed to match the resistor ratios, which will increase the circuit complexity and cost. The multiple temperature trimming technique in Ref. [8] achieves high precision performance but is not favored because of its complicated circuit implementation.
In this paper, we propose a novel temperature compensating method for canceling high-order nonlinearities by using the voltage difference of MOS transistors operating in a saturate region to compensate the nonlinearities of base-emitter voltage of the bipolar transistor (VBE). The PSRR are enhanced by employing a novel voltage pre-regulator circuit to suppress the supply noise over a broad frequency range, which costs low headroom and thus the circuit can operate in a broad supply voltage range.
2.
Conventional bandgap reference
In a conventional bandgap reference circuit, as shown in Fig. 1, the op-amp and current mirror (M1 and M2) forces nodes V1 and V2 to be at the same potential, thus generating the desired current ICTAT through R2 (R1 = R2) and IPTAT through R3 and Q2. Vref is generated by the sum of IPTAT and ICTAT multiplied by the output resistor R4.
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Figure1.
Conventional bandgap reference circuit.
$${I_{{ m{PTAT}}}} = frac{{Delta {V_{{ m{BE}}}}}}{{{R_3}}},$$  | (1) |
$${I_{{ m{CTAT}}}} = frac{{{V_{{ m{BE}}}}}}{{{R_2}}},$$  | (2) |
$${V_{{ m{ref}}}} = ({I_{{ m{CTAT}}}} + {I_{{ m{PTAT}}}}){R_4} = left(frac{{{V_{{ m{BE}}}}}}{{{R_2}}} + frac{{Delta {V_{{ m{BE}}}}}}{{{R_3}}} ight){R_4}.$$  | (3) |
The difference in base-emitter voltage between Q1 and Q2 (ΔVBE) can be written as:
$$Delta {V_{{ m{BE}}}} = {V_{ m{T}}}ln N = frac{{kT}}{q}ln N ,$$  | (4) |
where VT is the thermal voltage, N is the emitter-area ratio of Q2 and Q1, T is the actual working temperature, k is Boltzmann constant, and q is the charge of an electron. We can conclude that the current IPTAT generated by ΔVBE across the resistor is linear with temperature from Eqs. (1) and (4).
The base–emitter voltage of the bipolar transistor (VBE) can be expressed as[9, 10]:
$${V_{{ m{BE}}}} = {V_{{ m{g}}0}} - frac{T}{{{T_0}}}left( {{V_{{ m{g}}0}} - {V_{{ m{BE}}0}}} ight) - left( {eta - delta } ight){V_{ m{T}}}ln {frac{T}{{{T_0}}}},$$  | (5) |
where Vg0 is the bandgap voltage of the silicon at 0 K, the value of it is about 1.2 V, T is the actual working temperature, T0 is specified reference temperature, VBE0 represents the base–emitter voltage of the bipolar transistor (VBE) at T0, η is the process related parameter with value ranging from 3.6 to 4 and δ is the order of the temperature dependence of the collector current. If the collector current is PTAT (proportional to absolute temperature), we substitute δ = 1 and if the collector current is temperature independent we substitute δ = 0[9]. Since the collector current is PTAT in most BGRs, the value of δ in Eq. (5) is 1. VT is equal to thermal voltage kT/q, k is Boltzmann's constant, and q is the charge of an electron. The VTln(T/T0) item demonstrates a high-order nonlinearity of VBE, which should be reduced. Transforming VT we can obtain the following equation:
$${V_{ m{T}}} = frac{{kT}}{q} Rightarrow frac{{{V_{ m{T}}}}}{T} = frac{{{V_{{{ m T}0}}}}}{{{T_0}}} Rightarrow {V_{ m{T}}} = frac{{{V_{{{ m T}0}}}}}{{{T_0}}}T,$$  | (6) |
where VT0 represents the thermal voltage at T0. Substituting Eq. (6) in Eq. (5) and using a Taylor series expansion in Eq. (5), VBE can be rewritten in the form of:
$$begin{split}{V_{{ m{BE}}}}left( T ight) = ,, & {V_{{ m{BE}}0}} - frac{{{V_{{ m{g}}0}} - {V_{{ m{BE}}0}} + left( {eta - delta } ight){V_{{ m{T}}0}}}}{{{T_0}1!}}left( {T - {T_0}} ight) & -frac{{left( {eta - delta } ight){V_{{ m{T}}0}}}}{{{T_0}^22!}}{left( {T - {T_0}} ight)^2} + frac{{left( {eta - delta } ight){V_{{ m{T}}0}}}}{{{T_0}^33!}}{left( {T - {T_0}} ight)^3} + cdot cdot cdot .end{split}$$  | (7) |
From Eqs. (2) and (7), we can conclude that the current ICTAT generated by VBE across the resistor has many nonlinear terms. A conventional bandgap reference circuit uses ΔVBE to cancel the linear item of VBE. However, from Eq. (7) and Eq. (4) we can see that VBE contains many high-order items while ΔVBE is linear with T, thus such a method only compensates for only the linear parts of VBE while the remaining nonlinearities, second up to higher order items, still exist. These high-order items limit the accuracy of Vref.
3.
Proposed bandgap reference circuit
3.1
Compensation of nonlinearities
As previously mentioned in Section 2, ICTAT generated by VBE across the resistor has many nonlinear terms while IPTAT generated by ΔVBE across the resistor is linear with temperature. In order to compensate the nonlinearities of ICTAT, a nonlinear current INL which is generated by ΔVGS across the resistor is proposed in this paper. Combine ICTAT, IPTAT and INL, the high-order nonlinear terms of ICTAT can be well compensated to achieve high-order curvature compensation. The compensation method of the proposed BGR core circuit is illustrated in Fig. 2.
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Figure2.
The compensation method of the proposed BGR core circuit.
As shown in Fig. 3, the gate source voltage of two MOS transistors operating in a saturated region can be written as follows:
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Figure3.
The gate?source voltage of two MOS transistors.
$${V_{{ m{GS}}1}} = sqrt {frac{{2{I_1}}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {W/L} ight)}}} + {V_{{ m{th}}}},$$  | (8) |
$${V_{{ m{GS}}2}} = sqrt {frac{{2{I_2}}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {K times W/L} ight)}}} + {V_{{ m{th}}}},$$  | (9) |
where I1 and I2 are bias current flow through transistor M1 and M2 respectively, W and L are the channel width and channel length of M1 respectively, K is the ratio of the W/L of M2 and M1, μn represents n-type carrier mobility and it is negative related to temperature. Let I1 = I2 = I = k1Tm, μn = k2T?n, k1 and k2 are parameters independent of temperature, m and n are temperature-independent numbers and values of them are about 1.5. Subtracting VGS2 from VGS1 gives the following expression:
$$begin{split}Delta {V_{{ m{GS}}}} & = {V_{{ m{GS}}1}} - {V_{{ m{GS}}2}} = sqrt {frac{{2I}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {1 - sqrt {frac{1}{K}} } ight)& = sqrt {frac{{2{k_1}}}{{{k_2}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {1 - sqrt {frac{1}{K}} } ight){T^{frac{{m + n}}{2}}}.end{split}$$  | (10) |
Since the value of m + n is between 2 and 4, the voltage ΔVGS is positively correlated to temperature. The first order, second order and third order derivative of voltage ΔVGS can be expressed in the following form respectively:
$$frac{{{ m d}Delta {V_{{ m{GS}}}}}}{{ m d}T} = {k_3}frac{{m + n}}{2}{T^{frac{{m + n - 2}}{2}}} > 0,$$  | (11) |
$$frac{{{{ m d}^2}Delta {V_{{ m{GS}}}}}}{{{ m d}{T^2}}} = {k_3}frac{{m + n}}{2}frac{{m + n - 2}}{2}{T^{frac{{m + n - 4}}{2}}} > 0,$$  | (12) |
$$frac{{{{ m d}^3}Delta {V_{{ m{GS}}}}}}{{{ m d}{T^3}}} = {k_3}frac{{m + n}}{2}frac{{m + n - 2}}{2}frac{{m + n - 4}}{2}{T^{frac{{m + n - 4}}{2}}} < 0,$$  | (13) |
$${k_3} = sqrt {frac{{2{k_1}}}{{{k_2}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {1 - sqrt {frac{1}{K}} } ight).$$  | (14) |
Using a Taylor expansion for ΔVGS we can obtain equation:
$$Delta {V_{{ m{GS}}}} = {a_0} + frac{{{a_1}}}{{1!}}left( {T - {T_0}} ight) + frac{{{a_2}}}{{2!}}{left( {T - {T_0}} ight)^2} + frac{{{a_3}}}{{3!}}{left( {T - {T_0}} ight)^3} + cdots,$$  | (15) |
$${a_0} = {left. {Delta {V_{{ m{GS}}}}} ight|_{T = {T_0}}},$$  | (16) |
$${a_1} = {left. {frac{{{ m d}Delta {V_{{ m{GS}}}}}}{{ m d}T}} ight|_{T = {T_0}}},$$  | (17) |
$${a_2} = {left. {frac{{{{ m d}^2}Delta {V_{{ m{GS}}}}}}{{{ m d}{T^2}}}} ight|_{T = {T_0}}},$$  | (18) |
$${a_3} = {left. {frac{{{{ m d}^3}Delta {V_{{ m{GS}}}}}}{{{ m d}{T^3}}}} ight|_{T = {T_0}}}.$$  | (19) |
Compared with the Taylor expansion for voltage VBE in Eq. (7), it is concluded that the coefficients of Taylor expansion of VBE and ΔVGS are opposite. As a result, voltage ΔVGS can cancel the second-order item of voltage VBE completely and offset the third-order item and higher-items of voltage VBE in some degree.
3.2
Voltage pre-regulator circuit
In this paper, a voltage pre-regulator circuit is introduced as a local supply voltage of a bandgap core circuit to boost the supply voltage suppression performance. The pre-regulated voltage should be less sensitive to the power supply and temperature because any variations in the pre-regulated voltage will directly affect the performance of the subsequent bandgap core circuit.
A simplified circuit topology of the voltage pre-regulator circuit is illustrated in Fig. 4. It consists of a reference generator, an operational amplifier, a MOS transistor M1, two resistors R1 and R2 and a bandgap reference core circuit. The op-amp, M1, R1 and R2 constitute a negative feedback loop to regulate the pre-regulated voltage Vreg. When the voltage Vreg rises, the potential of node VF increases as well, thus the output voltage of op-amp V1 increases. Then the voltage Vreg decreases since M1 is a common-sense amplifier. Finally, the voltage Vreg will stabilize near a fixed voltage value. The op-amp forces nodes Vref1 and VF to be at the same potential, so the pre-regulated voltage can be expressed as:
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Figure4.
Circuit topology of the proposed voltage pre-regulator.
$${V_{{ m{reg}}}} = left( {1 + frac{{{R_1}}}{{{R_2}}}} ight){V_{{ m{ref}}1}}.$$  | (20) |
The reference voltage Vref1 is generated by a first-order temperature compensated reference voltage generator and it is approximately independent of temperature. The voltage Vref1 is given by:
$$begin{split}{V_{{ m{ref}}1}}& = {I_{ m{b}}} {R_3} + {V_{{ m{GS}}3}} = Delta {V_{{ m{GS}}3,2}} + {V_{{ m{GS}}3}} & =sqrt {frac{{2{I_{ m{b}}}}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {2 - frac{1}{{sqrt k }}} ight) + {V_{{ m{TH}}0}} - {k_{{ m{th}}}}left( {T - {T_0}} ight),!!!!end{split}$$  | (21) |
where W and L are the channel width and channel length of M3 respectively, k is the ratio of the W/L of M2 and M3, μn represents n-type carrier mobility and it is negative related to temperature, VTH0 represents the VTH voltage at the temperature T0, kth represents the temperature coefficient of the opening voltage VTH, T0 is the specified reference temperature, and T is the actual working temperature. Let Ib = kbTm, μn = kuT?n, kb and ku be parameters independent of temperature, m and n are temperature-independent numbers and the values of them are about 1.5. Substituting Ib and μn in Eq. (21) and the first order derivative of voltage Vref1 can be written as:
$$frac{{{ m d}{V_{{ m{ref}}1}}}}{{{ m d}T}}{ m{ = }}sqrt {frac{{2{k_{ m{b}}}}}{{{k_{ m{u}}}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {2 - frac{1}{{sqrt k }}} ight)frac{{m + n}}{2}{T^{frac{{m + n - 2}}{2}}} - {k_{{ m{th}}}}.$$  | (22) |
The temperature coefficient of the reference Vref1 can be approximately zero by setting the first order derivation of Vref1 at zero at T1 (?40 to 125 °C).
A small-signal power supply rejection ratio analysis is performed to illustrate the principle of the pre-regulated circuit deeply. We can obtain the following expressions by analyzing the relationship of voltage and current among nodes in the small-signal model.
$${V_{ m{F}}} = frac{{{R_2}}}{{{R_1} + {R_2}}}{V_{{ m{reg}}}},$$  | (23) |
$${V_1} = A{V_{ m{F}}},$$  | (24) |
$$frac{{{V_{{ m{dd}}}} - {V_{{ m{reg}}}}}}{{{R_{{ m{o}}1}}}} + {g_{{ m{m}}1}}left( {{V_{{ m{dd}}}} - {V_1}} ight) = frac{{{V_{{ m{reg}}}}}}{{left( {{R_1} + {R_2}} ight)//{R_{{ m{BGR}}}}}},$$  | (25) |
where gm1 is the transconductance of the transistor M1, RO1 is the output impendence of the transistor M1, and RBGR represents the effective impedance from the pre-regulated voltage Vreg to the ground node of the bandgap reference core circuit. A represents the open-loop gain of the op-amp. The power supply rejection ratio (PSRR) of the voltage Vreg can be derived from the relational expressions above:
$$begin{split} { m {PSRR}}{_{V{ m{reg}}}} &= 20log left( {frac{{{V_{{ m{reg}}}}}}{{{V_{{ m{dd}}}}}}} ight)& = 20log left[ {frac{{{g_{{ m{m}}1}} + frac{1}{{{R_{{ m{O}}1}}}}}}{{{g_{{ m{m}}1}}Afrac{{{R_2}}}{{{R_1} + {R_2}}} + frac{1}{{{R_{{ m{O}}1}}}} + frac{1}{{left( {{R_1} + {R_2}} ight)//{R_{{ m{BGR}}}}}}}}} ight] & approx 20log left[ {frac{1}{A}left( {1 + frac{{{R_1}}}{{{R_2}}}} ight)} ight].end{split}$$  | (26) |
From Eq. (26), the higher the open-loop gain A of the op-amp is, the lower the PSRRVreg is. The PSRR of the reference voltage Vref can be expressed as follows:
$${ m {PSRR}}{_{{ m{Vref}}}} ={ m {PSRR}}{_{{ m{Vreg}}}} times { m {PSRR}}{_{{ m{Vref - Vreg}}}},$$  | (27) |
where PSRRVref-Vreg is the PSRR of Vref to the pre-regulated voltage Vreg. It is concluded that the power supply voltage suppression performance of the bandgap reference voltage is improved by approximately A times and the supply noise is suppressed significantly by employing the proposed voltage pre-regulator circuit.
4.
Circuit realization
The implementation of the proposed bandgap reference circuit is shown in Fig. 5. The voltage pre-regulator circuit generates a pre-regulated voltage to supply the BGR core circuit. Transistors N1–N4, P3, P4 and R1 constitute the biasing and reference voltage generator circuit. As a biasing circuit, it can provide a stable biasing current Ib, which does not change with the supply voltage. As a reference voltage generator circuit, it can provide the differential amplifier with a low temperature coefficient reference voltage (Vref1). Transistors P5, P6, N5–N7 constitute a two-input differential amplifier, and the compensating capacitor (CM) is used to ensure the stability of the feedback loop under a wide range of operating conditions and parameter variations. The pre-regulating technique greatly reduces the power supply voltage noise and fluctuations in the bandgap reference core circuit, and thus improves the supply voltage suppression performance and linear adjustment performance significantly.
As shown in Fig. 5, Transistors N11–N14, P17, P18 constitute the INL generating circuit. Transistors N11, N12, P17, P18 generate a constant current mirror. If the sizes of N11, N12 are equal and those of P17, P18, nodes V3 and V4 are forced to be at the same potential, thus the difference in gate-source voltage ΔVGS between N13 and N14 is converted to nonlinear current INL by dividing resistor R7.
$${V_{{ m{GS}}13}} = sqrt {frac{{2{I_{{ m{NL}}}}}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {W/L} ight)}}} + {V_{{ m{th}}}},$$  | (28) |
$${V_{{ m{GS}}14}} = sqrt {frac{{2{I_{{ m{NL}}}}}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {K times W/L} ight)}}} + {V_{{ m{th}}}},$$  | (29) |
where W and L are the channel width and channel length of N13 respectively, K is the ratio of the W/L of N14 and N13, μn represents n-type carrier mobility and it is negative related to temperature. Let INL = k1Tm, μn = k2T?n, k1 and k2 are parameters independent of temperature, m and n are temperature-independent numbers and values of them are about 1.5. Subtracting VGS14 from VGS13 gives the following expression:
$$begin{split}Delta {V_{{ m{GS}}}} = {V_{{ m{GS}}13}} - {V_{{ m{GS}}14}} = sqrt {frac{{2{I_{{ m{NL}}}}}}{{{mu _{ m{n}}}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {1 - sqrt {frac{1}{K}} } ight) = sqrt {frac{{2{k_1}}}{{{k_2}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {1 - sqrt {frac{1}{K}} } ight){T^{frac{{m + n}}{2}}}.end{split}$$  | (30) |
The nonlinear temperature compensating current INL is created through the voltage ΔVGS across the resistor R7.
$${I_{{ m{NL}}}} = frac{{Delta {V_{{ m{GS}}}}}}{{{R_7}}}.$$  | (31) |
As can be seen in Fig. 5, the addition of CTAT current and PTAT current generated in the first-order current-mode BGR circuit is mirrored by P20 and the nonlinear corrected current INL is mirrored by P19. The sum of ICTAT and IPTAT and INL runs through R7 to generate the output voltage Vref. The output voltage Vref can be written as:
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Figure5.
The implementation of the proposed bandgap reference circuit.
$${V_{{ m{ref}}}} = left( {{I_{{ m{CTAT}}}} + {I_{{ m{PTAT}}}} + {I_{{ m{NL}}}}} ight) {R_8} = left( {frac{{{V_{{ m{BE}}}}}}{{{R_4}}} + frac{{Delta {V_{{ m{BE}}}}}}{{{R_6}}} + frac{{Delta {V_{{ m{GS}}}}}}{{{R_7}}}} ight){R_8}.$$  | (32) |
The Vref can be expressed as a function of T by substituting Eqs. (4), (5), (6) and (30) into Eq. (32):
$$begin{split}{V_{{ m{ref}}}} =& - frac{{{R_8}}}{{{R_4}}}frac{{{V_{{ m{g}}0}} - {V_{{ m{BE}}0}} - left( {{R_4}/{R_6}} ight){V_{{ m{T}}0}}ln left( N ight) + left( {eta - 1} ight){V_{{ m{T}}0}}}}{{{T_0}}} T& - frac{{{R_8}}}{{{R_4}}}frac{{left( {eta - 1} ight){V_{{ m{T}}0}}}}{{{T_0}}}Tln left( {frac{T}{{{T_0}}}} ight) + frac{{{R_8}}}{{{R_7}}}{k_3}{T^{frac{{m + n}}{2}}} + frac{{{R_8}}}{{{R_4}}}{V_{{ m{g}}0}},end{split}$$  | (33) |
$${k_3} = sqrt {frac{{2{k_1}}}{{{k_2}{C_{{ m{ox}}}}left( {W/L} ight)}}} left( {1 - sqrt {frac{1}{K}} } ight).$$  | (34) |
The first order and second order derivative of voltage Vref can be expressed in the following form:
$$begin{split}frac{{{ m d}{V_{{ m{ref}}}}}}{{{ m d}T}} = &- frac{{{R_8}}}{{{R_4}}}frac{{{V_{{ m{g}}0}} - {V_{{ m{BE}}0}} - left( {{R_4}/{R_6}} ight){V_{{ m{T}}0}}ln left( N ight) + left( {eta - 1} ight){V_{{ m{T}}0}}}}{{{T_0}}}& - frac{{{R_8}}}{{{R_4}}}frac{{left( {eta - 1} ight){V_{{ m{T}}0}}}}{{{T_0}}}ln left( {frac{T}{{{T_0}}}} ight) + frac{{{R_8}}}{{{R_7}}}{k_3}frac{{m + n}}{2}{T^{frac{{m + n - 2}}{2}}},end{split}$$  | (35) |
$$frac{{{{ m d}^2}{V_{{ m{ref}}}}}}{{{ m d}{T^2}}} = - frac{{{R_8}}}{{{R_4}}}frac{{left( {eta - 1} ight){V_{{ m{T}}0}}}}{{{T_0}}}frac{1}{T} + frac{{{R_8}}}{{{R_7}}}{k_3}frac{{m + n}}{2}frac{{m + n - 2}}{2}{T^{frac{{m + n - 4}}{2}}}.$$  | (36) |
If the stationary point and inflection point of the temperature curve of the reference voltage Vref are set as T1 and T2 respectively, we can obtain the following expression:
$${left. {frac{{{ m d}{V_{{ m{ref}}}}}}{{ m d}T}} ight|_{T = {T_1}}} = 0,$$  | (37) |
$${left. {frac{{{{ m d}^2}{V_{{ m{ref}}}}}}{{{ m d}{T^2}}}} ight|_{T = {T_2}}} = 0.$$  | (38) |
In order to attain a lower temperature coefficient over the temperature range from ?40 to 125 °C, the values of T1 and T2 are supposed to be within the temperature range (?40 to 125 °C). The value of key resistors (R4–R8) can be inferred from the above relational expression and the current IPTAT, ICTAT and INL.
5.
Results and discussion
The proposed BGR was designed in CSMC 0.5 μm 600 V BCD process and the layout is shown in Fig. 9. The robustness of the proposed BGR is verified by a corner simulation. Table 1 shows the simulated results of transistor corners. Fig. 6 shows the simulated and measured temperature characteristics. As shown in Table 1 and Fig. 6, the proposed BGR achieves TC of 0.144 ppm/°C in the best corner simulation (ff) and 0.159 ppm/°C in the worst corner simulation (ss). The measured temperature characteristic of the proposed BGR is 0.19 ppm/°C. Fig. 7 shows the simulated and measured PSRR performance. As shown in Table 1 and Fig. 7, the PSRR is slightly affected by transistor corners. The best case is ?125.10 dB @ DC(tt) and ?59.75 @ 100 kHz(ff). PSRR of ?116.85 dB @ DC and ?50.63 @ 100 kHz is achieved in the worst case (ss). The measured PSRR is ?123 dB @ DC and ?56 dB @ 100 kHz.
| Parameter | tt | ff | ss |
| TC (ppm/°C) | 0.147 | 0.144 | 0.159 |
| PSRR (dB) @ DC | ?125.10 | ?123.24 | ?116.85 |
| PSRR (dB) @ 100 kHz | ?57.44 | ?59.75 | ?50.63 |
Table1.
Performance at transistor corners.
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| Parameter | tt | ff | ss |
| TC (ppm/°C) | 0.147 | 0.144 | 0.159 |
| PSRR (dB) @ DC | ?125.10 | ?123.24 | ?116.85 |
| PSRR (dB) @ 100 kHz | ?57.44 | ?59.75 | ?50.63 |
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Figure6.
(Color online) Simulated and measured temperature characteristics.
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Figure7.
(Color online) Simulated and measured PSRR performance.
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Figure9.
(Color online) Layout of the proposed BGR circuit.
Fig. 8 shows reference voltage versus supply voltage at room temperature. It depicts that the circuit will deteriorate when the supply voltage is lower than 2.8 V. The proposed BGR has a line regulation performance of 0.017%/V in a range of different supply voltages (2.8–20 V).
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Figure8.
(Color online) Measured Vref versus supply voltage.
Table 2 compares the performance of the BGR described in this paper to that of previously published BGRs. The BGR proposed in this paper shows the best performance in terms of TC and PSRR. However, the minimum power supply of the proposed BGR is higher than that in Refs. [11–17], which is mainly limited by the threshold of the MOS transistor of this process.
| Parameter | Ref. [11] | Ref. [12] | Ref. [13] | Ref. [14] | Ref. [15] | Ref. [16] | Ref. [17] | Ref. [18] | Ref. [19] | This work |
| Supply voltage (V) | 1.3–1.8 | 1.2–1.8 | 1.3–2.6 | 1.8–3.5 | 1.2 | 1.3–1.8 | 1.2 | 3.6 | 5 | 5 |
| Ref. voltage (V) | 1.238 | 1.09 | 1.1402 | 1.25 | 0.735 | 0.547 | 0.767 | 1.23 | 1.2937 | 0.9006 |
| Temp. range (°C) | 0–110 | ?40 to 120 | ?55 to 125 | ?20 to 80 | ?40 to 120 | ?40 to 140 | ?40 to 120 | ?40 to 130 | ?40 to 125 | ?40 to 125 |
| Measured TC (ppm/°C) | 26 | 147 | 4.1 | 5.5 | 4.2 | 1.67 | 3.4~6.9 | 11.8 | 4.1 | 0.19 |
| Line regulation (%/V) | 0.08 | N/A | 0.03 | 0.045 | N/A | 0.08 | 0.054 | N/A | 0.0137 | 0.017 |
| PSRR (dB) | ?46@ 100 kHz | ?62@ 100 kHz | ?54@ 100 kHz | N/A | ?30@ 100 kHz | N/A | ?40@ 100 kHz | ?31.8@ 10 Hz | ?81.72@ DC | ?56@ 100 kHz, –123@DC |
| Technology | 0.18 μm CMOS | 0.18 μm CMOS | 0.18 μm CMOS | 0.18 μm CMOS | 0.13 μm CMOS | 0.18 μm CMOS | 0.18 μm CMOS | 0.5 μm CMOS | 0.5 μm CMOS | 0.5 μm CMOS |
Table2.
Comparison with other published results.
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| Parameter | Ref. [11] | Ref. [12] | Ref. [13] | Ref. [14] | Ref. [15] | Ref. [16] | Ref. [17] | Ref. [18] | Ref. [19] | This work |
| Supply voltage (V) | 1.3–1.8 | 1.2–1.8 | 1.3–2.6 | 1.8–3.5 | 1.2 | 1.3–1.8 | 1.2 | 3.6 | 5 | 5 |
| Ref. voltage (V) | 1.238 | 1.09 | 1.1402 | 1.25 | 0.735 | 0.547 | 0.767 | 1.23 | 1.2937 | 0.9006 |
| Temp. range (°C) | 0–110 | ?40 to 120 | ?55 to 125 | ?20 to 80 | ?40 to 120 | ?40 to 140 | ?40 to 120 | ?40 to 130 | ?40 to 125 | ?40 to 125 |
| Measured TC (ppm/°C) | 26 | 147 | 4.1 | 5.5 | 4.2 | 1.67 | 3.4~6.9 | 11.8 | 4.1 | 0.19 |
| Line regulation (%/V) | 0.08 | N/A | 0.03 | 0.045 | N/A | 0.08 | 0.054 | N/A | 0.0137 | 0.017 |
| PSRR (dB) | ?46@ 100 kHz | ?62@ 100 kHz | ?54@ 100 kHz | N/A | ?30@ 100 kHz | N/A | ?40@ 100 kHz | ?31.8@ 10 Hz | ?81.72@ DC | ?56@ 100 kHz, –123@DC |
| Technology | 0.18 μm CMOS | 0.18 μm CMOS | 0.18 μm CMOS | 0.18 μm CMOS | 0.13 μm CMOS | 0.18 μm CMOS | 0.18 μm CMOS | 0.5 μm CMOS | 0.5 μm CMOS | 0.5 μm CMOS |
6.
Conclusion
A high-order curvature-compensated CMOS bandgap reference (BGR) topology with low TC and high PSRR has been proposed. The presented circuit is designed and simulated in CSMC 0.5 μm 600 V BCD process. The experimental results show that the output reference voltage Vref is 900.6 mV, and the TC is as low as 0.19 ppm/°C over a temperature range of 165 °C (?40 to 125 °C). The proposed BGR achieves PSRR of ?123 dB @ DC and ?56 dB @ 100 kHz. In addition, the circuit demonstrated very good line regulation performance for a broad range of supply voltages. The line regulation at room temperature is 0.017%/V in the supply range of 2.8–20 V.
