1.
Introduction
Power amplifiers, which consume the most energy in the T/R module, are the key components in a radar phased array system. Wide operation band, high power added efficiency, small area, and single-chip integration are the major characteristics for power amplifier design. In the X–Ku band phased array system, the wideband power amplifier is required to have excellent gain flatness and flat output power over the entire X–Ku band.
Many types of wideband PA have been proposed in published articles[1–11]. A stacked technique using the SOI process could achieve wideband power amplifier design, but it cannot integrate with the bulk CMOS process, and it is not suitable for single-chip integration[1]. A Darlington cascode structure is used in Ref. [2] to achieve a 4–17 GHz wideband power amplifier, but it has only 10 dB limited gain and low peak PAE of 15%. Recently, transformer based matching networks have been widely used in wideband power amplifier design[3–9], in which transformer and inductor based matching networks are used for all of the matching networks. However, these works focus on achieving flat wideband matching of all matching networks, which cannot release the potential of the wideband characteristic of TMN (transformer based matching network). In Ref. [4], a 21.6–41.6 GHz power amplifier using TMNs is designed in 65 nm CMOS. This work introduces different design strategies for wideband matching of output matching and inter-stage/input matching, but it has caused 4 dB in-band ripple and achieves less than one octave bandwidth. So, how to design a wideband PA with more than one octave bandwidth and small in-band ripple is still not addressed in Ref. [4].
In this work, we demonstrate a wideband power amplifier with a remarkable 77% bandwidth, covering the X–Ku-band. To achieve more than an octave bandwidth and excellent gain flatness, a novel gain fluctuation compensation technique is proposed. In the inter-stage matching network, a high coupling coefficient k transformer with a high quality factor Q matching network will broaden the bandwidth with reasonable merit of ripple. Meanwhile, in the output/input stage, a high k transformer with a low Q matching network makes the two pole frequencies merge together in the center of the working frequency, which can compensate for the ripple of an inter-stage matching network. Consequently, the proposed PA can achieve a wideband flat gain and flat output power over the band of interest, and the proposed compensation technique has been verified by chip measurements.
Section 2 introduces the theory of TMN and the proposed gain fluctuation compensation technique. Section 3 describes the detailed design of the proposed power amplifier. Section 4 shows the measurement results and a comparison with other works. Section 5 will draw the conclusions of the work in this paper.
2.
Theory of transformer based matching network
The basic form of a transformer based matching network (TMN) is shown in Fig. 1, which consists of two parallel RLC tanks in the primary and secondary sides respectively, and a coupling coefficient k between them.
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Figure1.
Transformer based matching network.
To ease the calculation, we define angular frequencies and quality factors of primary and secondary sides as:
$left{ begin{gathered} {omega _1}{ m{ = }}frac{1}{{sqrt {{L_1}{C_1}} }}, hfill {omega _2}{ m{ = }}frac{1}{{sqrt {{L_2}{C_2}} }}. hfill end{gathered} ight.$  | (1) |
$left{ begin{gathered} {Q_1}{ m{ = }}{omega _0}{R_1}{C_1}, hfill hfill {Q_2}{ m{ = }}{omega _0}{R_2}{C_2}. hfill end{gathered} ight.$  | (2) |
Next, according to the difference between an inter-stage matching network and an output matching network, different matching methods versus Q value will be discussed in the following parts.
2.1
Inter-stage matching issues
In the inter-stage matching network, the Q (> 10) of the secondary side is normally high because the load is a high impedance consisting of a small gate resistance (~2–3 Ω) in series with gate capacitance. The unsymmetrical tanks at the primary and secondary sides, and the highQ at the secondary side make the design of the inter-stage matching network difficult. This is the major issue in the wideband design of inter-stage matching. In Ref. [3], a parallel resistor is added to reduce the Q, but it will significantly sacrifice the gain and power. In Ref. [4], the asymmetrical magnetically-coupled resonator matching network, which sacrifices gain is used to broaden the bandwidth, but it is difficult to achieve more than an octave bandwidth.
In this work，the inter-stage matching with reasonable ripple is permissible due to the gain fluctuation compensation technique we proposed. This greatly reduces the design difficulty of wideband matching. The design of the inter-stage matching network can be simplified as following. Firstly, the small gate resistance is ignored in order to simplify the inter-stage matching network as in Fig. 2. In this condition, we make the resonate frequencies of the primary side equal to the secondary side
m{ = }};{omega _1};{
m{ = }};{omega _2})$
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Figure2.
Simplified inter-stage matching network.
$begin{split}&frac{{{V_2}}}{{{I_1}}}{ m{ = }}&frac{{{{s}}M{omega _0}^4{Q_{ m{1}}}{Q_2}}}{{({{{s}}^2}{Q_1} + s{omega _0} + {omega _0}^2{Q_1})({{{s}}^2}{Q_2} + s{omega _0} + {omega _0}^2{Q_2}) - {s^4}{k^2}{Q_1}{Q_2}}} ,end{split}$  | (3) |
where M is the mutual inductance of the primary coil and secondary coil, and Q1 and Q2 are the quality factors of primary and secondary RLC tanks respectively. From Eq. (3), we know that the circuit has two pole frequencies as:
$left{ begin{gathered} {omega _ { m{H}}} = frac{{{omega _0}}}{{2{Q_1}(1 - k)}}sqrt {4{Q_1}^2(1 - {{k}}) - 1} hfill {omega _ { m{L}}} = frac{{{omega _0}}}{{2{Q_{ m{2}}}(1 + k)}}sqrt {4{Q_{ m{2}}}^2(1 + k) - 1} hfill end{gathered} ight..$  | (4) |
When
$left{ begin{gathered} {omega _ { m{H}}} = frac{{{omega _{ m{0}}}}}{{sqrt {{{1 - k}}} }} hfill {omega _ { m{L}}} = frac{{{omega _{ m{0}}}}}{{sqrt {{{1 + k}}} }} hfill end{gathered} ight..$  | (5) |
From Eq. (5), it is obvious that a high k can broaden the bandwidth of the inter-stage matching network. Fig. 3 depicts the simulation results of the normalized passive gain of the inter-stage matching network versus k, which tells us: to achieve a bandwidth larger than one octave, a large k (~0.75) transformer should be used, but meanwhile a wider band will result in a larger gain fluctuation (~2 dB with an ideal transformer).
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Figure3.
(Color online) Normalized passive gain versus k when Q of secondary side is high (> 10).
2.2
Output matching condition
Different from the inter-stage matching network, in the transformer based output matching network, the Q values of both primary and secondary sides are low due to transistors’ low output impedances and 50 Ω load impedance. Therefore, the two sides of the transformer are made to be symmetrical and critical coupling conditions[12] are as follows:
$left{ begin{gathered} {omega _0} = {omega _1} = {omega _2}, hfill {{{n}}^2} = frac{{{L_{ m{p}}}}}{{{L_ { m{S}}}}} = frac{{{R_1}}}{{{R_2}}}, hfill Q = {Q_1} = {Q_2} hfill , end{gathered} ight.$  | (6) |
where n is the turn ratio of primary coil and secondary coil. The transfer impedance can be simplified from Eq. (3) as:
$frac{{{V_2}}}{{{I_1}}} = frac{{{{s}}M{omega _0}^4{Q^2}}}{{{{({{{s}}^2}Q + s{omega _0} + {omega _0}^2Q)}^2} - {s^4}{k^2}{Q^2}}}.$  | (7) |
The two pole frequencies are simplified from Eq. (4) as
${omega _ { m{H,L}}} = frac{{{omega _0}}}{{2Q(1 pm k)}}sqrt {4{Q^2}(1 pm {{k}}) - 1} .$  | (8) |
It can be calculated that two pole frequencies will merge together to achieve the flattest gain response with condition (9), which has been studied previously in Eq. [4], and then there will be only one pole frequency in the middle of the working frequency band.
${{{k}}^2}(1 + {Q^2}) = 1.$  | (9) |
So when Q is small enough to satisfy condition (9)，the two pole frequencies will surely merge together. Accordingly, there are two design methods for wideband matching proposed in this work：
Methods 1: Adding a parallel capacitor in the RLC tank of the primary side to increase the Q value, and two-pole frequencies will be separated and can be calculated from Eq. (8). Fig. 4 shows the relationship between the normalized passive gain and the k value when Q equals to 2. From Fig. 4, we can learn that to achieve more than one octave bandwidth, a large k (~0.7) should be used with nearly 1 dB in-band ripple in an ideal transformer.
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Figure4.
(Color online) Normalized passive gain versus k when Q equals to 2.
Methods 2: Making the two pole frequencies of the proposed output matching network merge together, and the gain of the center frequency will be higher than the edge of the bandwidth of interest, which is beneficial to compensate for the in-band gain ripple of the inter-stage matching network.
Fig. 5 shows the relationship between gain and ripple of the proposed two design methods. Method 1 can slightly broaden the 1 dB bandwidth, while it will also bring much loss in the center frequency of interest and cause large in-band gain ripple of the whole PA. Method 2 can achieve less loss in the center frequency, which is able to compensate the gain fluctuation of the inter-matching network and achieve better gain flatness. So, we choose Method 2 in this work to compensate for the gain ripple of the inter-stage matching network.
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Figure5.
(Color online) Normalized passive gain of Method 1 (Q = 1.6) and Method 2 (Q = 0.8) @ k is fixed at 0.75.
3.
Wideband PA design
Fig. 6 shows the schematic of the proposed two stage wideband PA, which consists of driver amplifier (DA), power amplifier (PA), and matching networks. To meet the requirement of output power, the sizes of power transistors and driver transistors are chosen as 6 × 30 × 2 μm/60 nm and 6 × 30 × 1 μm/60 nm respectively. Crossed coupled neutralization capacitors CN1 and CN2 are used for both stages to simultaneously improve the gain and stability[13–16], which are chosen as 110 and 55 fF respectively. TMNs are the most important parts of the wideband PA design, which will be described particularly in the following according to the analysis in the previous parts.
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Figure6.
The proposed wideband X–Ku-band PA.
The output matching network is always the first matching network concerned for a PA design, because the maximum output power and PAE are heavily dependent on the output matching network. Fig. 7 shows the equivalent circuit of the single-ended output matching network. Copt in parallel with Ropt are used to build up the equivalent optimal load impedance of the output stage, and a load-pull simulation has been done to get the optimal load impedance. In this design, the conjugate of the optimal load impedance approximately equals to a 42 ? resistor Ropt in parallel with a 240 fF capacitance Copt, which means the Q value of the primary is small enough to satisfy condition (9). According to the analysis in the previous section, adding parallel capacitance will bring the loss and make the gain of the center frequency lower than that of two pole frequencies, which will make the wideband PA have low PAE and large gain ripple, as described in Method 1.
In this work, in order to compensate for the gain ripple of the inter-stage matching network, the output matching network makes two pole frequencies merge together, as described in Method 2. A transformer with high coupling coefficient k will be needed to transform 50 Ω load impedance to the optimal loading impedance. According to the critical coupling condition (6), we can get:
$left{ begin{gathered} frac{{{C_ { m{opt}}}}}{{{C_ { m{L}}}}} = frac{{{R_ { m{L}}}}}{{{R_ { m{opt}}}}}, hfill frac{{{L_ { m{p}}}}}{{{L_ { m{s}}}}} = frac{{{R_ { m{opt}}}}}{{{R_ { m{L}}}}} .hfill end{gathered} ight.$  | (10) |
The parameters of transformer and capacitor CL are shown in Fig. 7. According to the parameters of coil inductance and k of the output matching transformer, the structure and size of transformer can be designed, as shown in Fig. 9(a). The transformer has a spiral-type geometry to achieve a high Q factor. Only the 3.4 μm top metal layer is used for the windings, and the underpass lines are realized with the lower metal layer. The linewidth of the proposed transformer is 6 μm and metal spacing is 3 μm. Fig. 10(a) shows the normalized passive gain of the output matching network with the proposed transformer, from which we can see that the proposed matching network achieves 1.4–2 dB insertion loss within the frequency range of 8–19 GHz.
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Figure7.
Output matching network.
Fig. 8 shows the equivalent single-ended circuit of the inter-stage matching network, which consists of output impedance Ro,d (142 ?) in parallel with Co,d (120 fF) of driver transistors and input impedance Rs,p (nearly 3 ?) in series with Cp (250 fF) of power transistors. The input capacitance of the power amplifier stage is nearly twice the output parasitic capacitance of the driver amplifier stage, and we can get the transformer parameters of coil inductance and k according to Eq. (5), as shown in Fig. 8. Fig. 9(b) depicts both the structure and size of the inter-stage matching transformer with 3 μm linewidth and 5 μm metal spacing. Fig. 10(b) shows the normalized passive gain of the inter-stage matching network, which demonstrates that the designed inter-stage matching network has 2 dB ripple.
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Figure8.
Inter-stage matching network.
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Figure9.
(Color online) The transformers of (a) output matching network and (b) inter-stage matching network.
In the input matching network, to improve input return loss and compensate for the gain ripple of the inter-stage matching network, a 200 ? paralleled resistor R1 is added to reduce the Q value. The design technique can be nearly the same as the one used in the design of the output matching network. Fig. 10(c) shows the normalized passive gain of the input matching network, which tells us that the proposed input matching network achieves 1.5–2.3 dB insertion loss between 8–18 GHz and can compensate for the larger in-band ripple of the inter-stage matching network.
Fig. 10(d) shows the simulated gain of the proposed wideband PA, which tells us that the wideband PA achieves gain of 21.5–22.5 dB with only 1 dB ripple from 7.5–18.5 GHz, and verifies that the gain fluctuation of the inter-stage matching network can be efficiently compensated by the proposed design methods.
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Figure10.
Normalized passive gain of (a) output matching network, (b) inter-stage matching network, and (c) input matching network. (d) The simulation gain of wideband PA.
4.
Implementation and measurements
The wideband PA is fabricated in the TSMC 65 nm CMOS process. The die micrograph of the PA is shown in Fig. 11 with a core area of 0.88
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Figure12.
(Color online) The simulated and measured S-parameters of the wideband PA.
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Figure11.
(Color online) Chip photograph of the wideband PA.
The large signal performance of the designed wideband PA is measured by an Agilent E8257D PSG 20-GHz analog signal generator and an E4440A PSA 26-GHz spectrum analyzer. Fig. 13 shows the measured results of gain, output power, and PAE of the PA at 13 GHz. The PA achieves a saturated output power (PSAT) and P1 dB of 14.6 and 11.3 dBm respectively, with a peak PAE of 23%. Fig. 14 shows the measured output power and PAE versus frequency, which demonstrates that the proposed power amplifier achieves 13–14.6 dBm flat output power and 17%–23% peak PAE between 7.5–15.5 GHz, and once again verifies the proposed wideband matching method. It can also be seen from Fig. 14 that the proposed wideband power amplifier achieves only 1.5 dB output power ripple, which is suitable for wideband operation.
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Figure13.
(Color online) Measured gain, POUT, PAE against input power at 13 GHz.
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Figure14.
(Color online) Measured large signal CW performance versus frequency.
Table 1 summarizes the measured performance of the proposed PA, which is compared with other state of the art wideband PAs. From Table 1, it can be seen that the proposed wideband PA shows the highest fractional bandwidth and the smallest in-band ripple, while the PAE is higher than Refs. [3,5,6]. It means that the proposed method has demonstrated the effectivity of gain fluctuation compensation for wideband PA, although the bandwidth (7.5–15.5 GHz) with 1.5 dB ripple is a little bit less than the X–Ku band due to the inaccuracy of passive modelling at high frequency. PAE of Ref. [4] is better than that of the proposed wideband PA, but it has also caused larger in-band gain ripple (4 dB). As a tradeoff design of wideband PA, the proposed wideband PA demonstrates better gain flatness (1.5 dB) over 77% fractional bandwidth at a central frequency of 13 GHz. As a matter of fact, further design optimization for the target band of interest and higher PAE has been on-going and will be manufactured very soon with the potential proposed method.
| Parameter | This work | JSSCC15[3] | ASSCC16[4] | MWCL17[5] | MTT11[6] |
| CMOS Tech (nm) | 65 | 28 | 65 | 65 | 180 |
| Supply (V) | 1.1 | 1 | 1 | 1.2 | 3.6 |
| fc (GHz) | 13 | 53 | 32 | 15 | 9.5 |
| Frac. BW (%) | 77 | 51 | 63 | 34 | 52 |
| Gain (dB) | 21.2 | 13 | 20.8 | 20.6 | 25.3 |
| Ripple (dB) | 1.5 | 3 | 4 | 3 | 3 |
| P1 dB (dBm) | 11.3 | 12 | 12.9 | 11.6 | 20.2 |
| PSAT (dBm) | 14.6 | 13.3 | 15.3 | 13.9 | 21.5 |
| PAEMAX (%) | 23 | 16 | 32 | 20 | 20.3 |
| Area (mm2) | 0.2 | 0.066 | 0.11 | 0.586* | 0.63 |
| *with PAD | |||||
Table1.
Performance comparison of the wideband power amplifier with previously reported literatures.
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| Parameter | This work | JSSCC15[3] | ASSCC16[4] | MWCL17[5] | MTT11[6] |
| CMOS Tech (nm) | 65 | 28 | 65 | 65 | 180 |
| Supply (V) | 1.1 | 1 | 1 | 1.2 | 3.6 |
| fc (GHz) | 13 | 53 | 32 | 15 | 9.5 |
| Frac. BW (%) | 77 | 51 | 63 | 34 | 52 |
| Gain (dB) | 21.2 | 13 | 20.8 | 20.6 | 25.3 |
| Ripple (dB) | 1.5 | 3 | 4 | 3 | 3 |
| P1 dB (dBm) | 11.3 | 12 | 12.9 | 11.6 | 20.2 |
| PSAT (dBm) | 14.6 | 13.3 | 15.3 | 13.9 | 21.5 |
| PAEMAX (%) | 23 | 16 | 32 | 20 | 20.3 |
| Area (mm2) | 0.2 | 0.066 | 0.11 | 0.586* | 0.63 |
| *with PAD | |||||
5.
Conclusion
This paper presents the design and implementation of a wideband power amplifier in a 65 nm RF CMOS process. A novel gain fluctuation compensation technique to achieve lower amplitude ripple is proposed and verified by chip measurement. With the assistance of the proposed technique, the power amplifier achieves 21–22.5 dB flat gain with 1.5 dB ripple, and 13–14.6 dBm flat saturated output power with a 23% max PAE from 7.5 to 15.5 GHz. At a supply voltage of 1.1 V, the power consumption of the proposed power amplifier is 123.2 mW. The proposed wideband PA is suitable for integration with an X–Ku-band radar phased array, which requires excellent gain flatness.
