1.
Introduction

Modern wireless communication networks usually apply complicated modulation schemes in order to increase data throughput in limited frequency bandwidth. Nevertheless, it is required that the signals being used and those being introduced have high peak-to-average power ratios (PAPRs) and wide bandwidths. However, high PAPRs poses severe linearity constraints on the power amplifiers, forcing a large output back-off (OBO) power operation to ensure the acceptable linearity^[1]. Unfortunately, this scenario makes the traditional power amplifier very poor in efficiency, especially at large back-off power^[2].



To improve efficiency at large OBO power level, Doherty power amplifiers (DPA) have been widely used due to high efficiency at the back-off power region^[3–14]. However, the conventional Doherty power amplifier cannot realize the proper load modulation effect due to the transistor parasitic parameters, resulting in both bandwidth and efficiency performance of DPA being much lower, which cannot effectively amplify the modern communication system broadband modulation signal. In this paper, a method for enhancing bandwidth and efficiency of DPA based on symmetric devices is proposed. A prototype based on identical GaN HEMTs is implemented for verification. Measurement results fully validate the effectiveness of the proposed architecture.

2.
Analysis of the conventional and the proposed DPA

As shown in Fig. 1, a classic DPA contains two sub-amplifiers, namely the class-AB biased carrier amplifier and the class-C biased peaking amplifier. The two cells are connected to each other with an input power splitter and a load modulation network. As the most important part of a DPA, the load modulation network consists of two λ/4 impedance transformers to achieve proper load modulation.






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Figure1.
Simplified schematic diagrams for the conventional DPA.




As mentioned above, for the sake of simplicity, the sub-amplifiers are often assumed as ideal current sources with no parasitics for theoretical analysis. Under these scenarios, λ/4 transmission lines are directly connected to the carrier and peak power amplifier outputs, and the impedance modulation occurs directly at the transistor’s current generator plane. However, a practical power amplifier, parasitic inductance and capacitance are not negligible. In addition, the load impedance of the transistor generally has a lower impedance value, and it needs to be converted the impedance of the output port. Load modulation happens at the common point Z_J, and then output matching networks (OMN) provide the carrier and peak amplifiers with optimal impedances required. Therefore, the performance that is designed by conventional DPA design method will decrease dramatically, especially in the back-off power region. It is necessary to improve the conventional design method for enhancing the performance of DPA. The configuration of the proposed DPA structure is shown in Fig. 2.






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Figure2.
Simplified schematic diagrams for the proposed DPA.




For the carrier amplifier, the OMN_C converts Z_{C, H} to the optimal load impedance Z_{opt, C, H} in the high-power region. The load impedance of the transistor die (current generator plane) is R_opt after taking the parasitics of the transistor into consideration. Z_{opt, C, H} can be obtained from load-pull technique. In the low-power region, the peaking amplifier is turn off, and the OMN_C will match Z_{C, L} to Z_{opt, C, H}, which is a value described by a constant VSWR circle as the circle center. The specific position is determined by the phase of OMN_C’s scattering parameter S₂₁. In other words, it is necessary to add an offset line with proper electrical length θ_C to the output of the OMN_C to make the load impedance reach 2R_opt, which finally ensures large output power and high efficiency of the DPA. The characteristic impedance Z_OC of the offset line is generally set to Z_{C, H} to keep the impedance matching intact in the high-power region. Therefore, in order to realize perfect load modulation, the electrical length of the output circuit of the carrier amplifier must be an integer multiple of 180°. The total electrical length of the output of carrier amplifier with the λ/4 impedance transformers is

$${theta _{ m {C,total}}} = frac{pi }{2} + npi, ,, ,,, n = 1,2,3... $$

(1)

For the peaking amplifiers, the output impedance of the peaking amplifiers is not open in the low-power regions due to the parasitic parameter, an offset line must be added after its output matching network OMN_P to convert the output impedance to the high impedance region, thereby reducing power leak, and to ensure the DPA back-off efficiency and power. The output impedance at the die of the peak amplifier is close open in the back-off power region. In order for the output impedance of the peak amplifier to be still open at the common point, the total electrical length of the output circuit of the peak amplifier must be

$${theta _{ m {P,total}}} = npi, ,, n = 1,2,3...$$

(2)

3.
Simulation design and measurement results

3.1
Simulation design

In this paper, a DPA based on the proposed strategy is designed using identical 10-W Cree CGH40010F GaN HEMT devices. ADS Simulations are conducted based on the model provided by the supplier. The carrier amplifier is biased at V_GS = ?2.7 V and V_DS = 28 V, corresponding to class-AB mode. On the other hand, the two peaking amplifiers are biased at V_GS = ?5 V and V_DS = 32 V, corresponding to the class-C mode. The design uses asymmetrical power supply mode that make the output currents of sub-amplifiers equal at saturation. It should be emphasized that in the methodology, a precise large-signal model of the selected device is required. Fortunately, a precise model of the parasitic network for the widely used CGH40010F has been derived and reported in Ref. [15]. Based on the parasitic network model, the large-signal model of CGH40010F is as shown in Fig. 3.






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Figure3.
(Color online) A commercial large-signal model of Cree CGH40010F.




The final completed schematic of the proposed DPA is shown in Fig. 4. A wideband equal power splitter is designed to systematically enhance the bandwidth. In order to reduce the output matching circuit complexity and enhance the bandwidth, the total output length of the carrier amplifier circuit is designed to be 270°, and the total output length of the peak amplification output circuit is 180°. In order to ensure efficiency of the DPA in the back-off power region, power superimposed of the carrier and peaking amplifier are realized in phase at the back-off power.






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Figure4.
(Color online) Complete schematic of the proposed DPA.

3.2
Measurement results

In order to experimentally validate the proposed design strategy, a DPA is implemented using Cree 10-W GaN HEMTs CGH40010F on a Rogers RO4350B substrate of thickness 30 mil, dielectric constant of 3.48, and a loss tangent of 0.0037. To achieve good heat dissipation, grounding performance and suppressing the thermal memory effect, the circuit board and transistor is welded to the copper substrate by the solder paste. The photograph of the fabricated DPA is shown in Fig. 5.






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Figure5.
(Color online) Photograph of the fabricated circuit.




The S-parameter of designed DPA measurement and simulation results are presented in Fig. 6. The small-signal gain are above 13 dB over the bandwidth (1.9?2.4 GHz) while input reflection coefficients are smaller than ?14 dB. Figs. 7 and 8 gives the measurement results of DPA under continuous wave (CW) signal in terms of output powers, drain efficiencies, gains and drain efficiencies at saturation and 6-dB back-off power in the frequency band from 1.9 to 2.4 GHz. As can be seen, the proposed DPA achieves a saturated drain efficiency of 63%–71%, saturated output powers of 44.2–45 dBm. The saturated gains are more than 9 dB, higher than 51% efficiency is obtained at 6-dB back-off power over the 500 MHz band. The measured drain efficiency profiles versus the output power at different frequency points are depicted in Fig. 9. It can be clearly observed that the proposed DPA approximately follows the classic Doherty type efficiency profiles at all the frequencies. To evaluate the linearization performance, taking the frequency of 2 GHz for example, Fig. 10 shows the measured ACPR for 5-MHz WCDMA modulated signal. The proposed PA has ACPR levels between ?36.2 and ?35.3 dBc at the lower and upper bands at about 6-dB back-off power, respectively. Table I lists the comparison of some published DPA performance and this work.






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Figure6.
(Color online) Measured and simulated S parameter of the proposed DPA versus frequency.






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Figure7.
(Color online) Measured and simulated peak powers, gains and drain efficiencies versus frequency at saturation power.






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Figure8.
(Color online) Measured and simulated gains and drain efficiencies versus frequency at 6-dB back-off power.






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Figure9.
(Color online) Measured drain efficiency profiles versus output power.






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Figure10.
(Color online) Measured ACPR for 5-MHz WCDMA modulated signal at 2 GHz.

Parameter	Frequency (GHz)	Bandwidth (%)	DE @ saturation (%)	DE @ 6 dB back-off (%)	Pout (dBm)
Ref. [2]	1.5?2.5	50	55?75	> 42	42?44.5
Ref. [3]	1.5?2.4	46.2	49?68	> 43	≥ 42
Ref. [4]	0.7?0.95	30	53?67	> 48	≥ 43
Ref. [5]	3?3.6	18.2	55?66	> 38	43?44
Ref. [6]	1.96?2.46	23	50?60	> 40	39.5?41.7
Ref. [7]	1.67?2.41	36.3	53?72	> 43	39?42
Ref. [8]	1.8?2.3	24.4	63?74	> 50	34
This work	1.9?2.4	23.3	63?71	> 51	44.2?45

Table1.
Doherty power amplifiers performance comparison.



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Parameter	Frequency (GHz)	Bandwidth (%)	DE @ saturation (%)	DE @ 6 dB back-off (%)	Pout (dBm)
Ref. [2]	1.5?2.5	50	55?75	> 42	42?44.5
Ref. [3]	1.5?2.4	46.2	49?68	> 43	≥ 42
Ref. [4]	0.7?0.95	30	53?67	> 48	≥ 43
Ref. [5]	3?3.6	18.2	55?66	> 38	43?44
Ref. [6]	1.96?2.46	23	50?60	> 40	39.5?41.7
Ref. [7]	1.67?2.41	36.3	53?72	> 43	39?42
Ref. [8]	1.8?2.3	24.4	63?74	> 50	34
This work	1.9?2.4	23.3	63?71	> 51	44.2?45

4.
Conclusion

A method for bandwidth and efficiency enhancement of DPA using symmetric devices has been proposed in this work. For demonstration, a DPA was fabricated based on the proposed configuration has been achieved with drain efficiency higher than 51% at 6-dB back-off power over the operational bandwidth.