1.
Introduction

Current mode active building blocks offer a wide dynamic range, good linearity and higher bandwidth with low supply voltage over their voltage mode counterparts. Various low voltage analog techniques including bulk driven, self-cascode, sub-threshold MOSFETs, and floating gate MOSFETs^[1–3] exist in the literature to design low voltage current mode based systems while meeting design specifications. FGMOSFET is the most suitable technique for low voltage low power analog applications as it reduces or removes the dependency on threshold voltage.



One of the vital blocks of the current mode signal processing family is the current differencing transconductance amplifier (CDTA)^[4]. CDTA is a versatile block operating over a broad range of frequencies and can be used to realize both linear and non-linear applications such as current limiter^[5], filters^[6–15], arithmetic functions^{[16, 17]}, oscillators^[18–20], and rectifiers^{[21, 22]}. Transconductance (g_m) of CDTA plays a crucial role in aforementioned applications to meet design requirements of the circuits. High transconductance or variable transconductance over a wide range of CDTA is desired instead of introducing passive components to the circuit. Various CDTA implementations^{[14, 15, 23–25]} exist in the literature and the drawbacks of these realizations are high supply voltage, low transconductance, narrow linear operating range, and high power dissipation.



Hence, this paper aims to design a high performance CDTA using FGMOSFETs operating at lower supply voltage with reduced power consumption, good linearity, and higher transconductance in comparison to existing CDTAs.



This paper is organized as follows. Section 2 covers the proposed implementation of CDTA operating at lower supply voltage. The applications of proposed FGMOS CDTA are mentioned in Section 3 followed by simulation results and comparison under Section 4. Finally, the conclusion is given in Section 5. The description of FGMOS technique is given in Appendix A.

2.
Proposed FGMOS based current differencing transconductance amplifier

The symbol and implementation of the FGMOS based CDTA circuit is depicted in Figs. 1 and 2. CDTA is comprised of two stages: current differencing stage (CDS) followed by a second stage of the transconductance amplifier. CDS senses the differential input current at terminals p and n and gives voltage due to impedance at terminal z. I_z is the difference of currents at terminals p and n. Transconductance amplifier stage (TA) converts that input voltage, V_z coming from the first stage into output currents at terminals x+ and x-. The transconductance of conventional TA and CDTA after small signal analysis^[26] can be given as






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Figure1.
Symbol of CDTA.






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Figure2.
FGMOS based CDTA.

$${g_{ m{m}}} = sqrt {frac{{2mu {c_{{ m{ox}}}}W{I_{ m{B}}}}}{L}},$$

(1)

where W/L is aspect ratio and I_B is biasing current.

$$frac{{{I_{{ m{x}} + }}}}{{{V_{ m{z}}}}} = {G_{ m{m}}} = {g_{ m{m}}},$$

(2)

The novel low voltage low power FGMOS based CDTA utilizes only two FGMOSFETs in the current mirror of the transconductance amplifier stage. The current mirror based on FGMOS is implemented by a method given in Ref. [27]. In this circuit, M_FG15 and M_FG18 are FGMOS transistors and the rest of the transistors are MOS transistors. The input linear range of the circuit increases due to the property of the FGMOS technique in addition to high transconductance and low power dissipation. The operation and current equation of the floating gate MOSFET is given in Appendix A.



The transconductance of FGMOS transistors FGM15 and FGM16 can be given by Eqs. (3) and (4) under certain conditions that channel sizes, drain currents, and drain-to-source voltages are identical to conventional MOSFET.

$${g_{ m{m}{ m{fg}}15}} = {g_{ m{m}15}}frac{{{C_1}}}{{{C_1} + {C_2}}},$$

(3)

$${g_{ m{m}{ m{fg}}18}} = {g_{ m{m}18}} frac{{{C_{ m{1}}}}}{{{C_1} + {C_2}}},$$

(4)

where $k = frac{{{C_1}}}{{{C_1} + {C_2}}}$ is the capacitance ratio.



The small signal model of TA is given in Fig. 3 and voltage V_g16 can be given as






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Figure3.
Small signal model of transconductance amplifier.

$${v_{{ m{g}16}}} = - {g_{ m{m}13}} frac{{{V_{ m{z}}}}}{2}left( {{r_{ m{o}13}}left| {{r_{ m{o}15}}} ight|frac{1}{{{g_{ m{m}{ m{fg}}15}}}}} ight).$$

(5)

As the factor $frac{1}{{k{g_{
m{m}15}}}}$ is quite small, so Eq. (5) can be rewritten as

$${v_{{ m{g}16}}} = - frac{{{V_{ m{z}}}}}{2} left( {frac{{{g_{ m{m}13}}}}{{{g_{ m{m}{ m{fg}}15}}}}} ight).$$

(6)

The expression for v_g19 is

$${v_{{ m{g}}19}} = {g_{ m{m}14}} frac{{{V_{ m{z}}}}}{2}left( {{r_{ m{o}14}}left| {{r_{ m{o}18}}} ight|frac{1}{{{g_{ m{m}{ m{fg}}18}}}}} ight).$$

(7)

As ${r_{
m{o}14}}left| {{r_{
m{o}18}}}
ight| gg frac{1}{{k{g_{
m{m}18}}}}$, thus Eq. (7) can be reduced to

$${v_{{ m{g}}19}} = frac{{{V_{ m{z}}}}}{2} {frac{{{g_{{ m{m}}14}}}}{{{g_{{ m{mfg}}18}}}}} ,$$

(8)

Voltage V_g21 is given by Eq. (9)

$${v_{{ m{g}}21}} = - {g_{{ m{m}}19}} {v_{{ m{g}}19}}.$$

(9)

Due to the small value of $frac{1}{{{g_{{
m{m}}22}}}}$ and using Eq. (9) above, Eq. (10) can be given as

$${v_{{ m{g}}21}} = - {v_{{ m{g}}19}} {frac{{{g_{{ m{m}}19}}}}{{{g_{{ m{m}}22}}}}} = - frac{{{V_{ m{z}}}}}{2} {frac{{{g_{{ m{m}}14}}}}{{{g_{{ m{mfg}}18}}}}} {frac{{{g_{{ m{m}}19}}}}{{{g_{{ m{m}}22}}}}}.$$

(10)

The output current I_x+ can be given by Eq. (11) according to the small signal model of TA.

$${I_{{ m{x}} + }} = { m{}} - {g_{{ m{m}}16}}{v_{{ m{g}}16}} - {g_{{ m{m}}21}}{v_{{ m{g}}21}}.$$

(11)

Using the above reduced equations of v_g16 and v_g21

$${I_{{ m{x}} + }} = {g_{{ m{m}}16}}frac{{{V_{ m{z}}}}}{2} {frac{{{g_{{ m{m}}13}}}}{{k{g_{{ m{m}}15}}}}} + {g_{{ m{m}}21}}frac{{{V_{ m{z}}}}}{2} {frac{{{g_{{ m{m}}14}}}}{{k{g_{{ m{m}}18}}}}} {frac{{{g_{{ m{m}}19}}}}{{{g_{{ m{m}}22}}}}} .$$

(12)

Considering that, M₁₃–M₁₄, M₁₅–M₁₆, M₁₈–M₁₉ and M₂₁–M₂₂ are perfectly matched,

$${g_{{ m{m}}13}} = {g_{{ m{m}}14}},$$

(13)

$${g_{{ m{m}}15}} = {g_{{ m{m}}16}},$$

(14)

$${g_{{ m{m}}18}} = {g_{{ m{m}}19}},$$

(15)

$${g_{{ m{m}}21}} = {g_{{ m{m}}22}}.$$

(16)

Thus, the equation can be reduced to

$${I_{{ m{x}} + }} = frac{{{V_{ m{z}}}}}{2}left( { {frac{{{g_{ m{m}}}}}{k}} + {frac{{{g_{ m{m}}}}}{k}}} ight) = frac{{{g_{ m{m}}}{V_{ m{z}}}}}{k},$$

(17)

$${G_{ m{m}}} = frac{{{g_{ m{m}}}}}{k}.$$

(18)

It can be seen that transconductance has been increased by factor k if compared with transconductance of conventional CDTA given in Eq. (2). The transconductance can be tuned with values of C₁ and C₂.



Hence, the proposed FGMOS based CDTA offers various lucrative features such as increased transconductance, lower supply voltage, reduced power dissipation, and wider linearity range.

3.
Applications of FGMOS based CDTA

3.1
Quadrature oscillator using MOS resistor

A current mode quadrature oscillator using FGMOS based CDTA is presented in this section. g_m1 and g_m2 are the transconductance of FGMOS based CDTA blocks 1 and 2, respectively. A parallel combination of a resistor R and a capacitor C₁ is connected to the z terminal of the first unit and C₂ is connected to the z terminal of the second amplifier as shown in Fig. 4.






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Figure4.
Quadrature oscillator using FGMOS CDTA and MOS resistor.




Resistor R has been implemented using two NMOS transistors, one is operating in the linear region and another in the saturation region. The features of the NMOS transistors based resistor are less silicon area occupation, higher linearity as the non-linear term present in the drain current equation of an NMOS transistor working in linear mode got cancelled by the drain current of another transistor operating in saturation mode and tunablility. The equivalent resistance of NMOS transistors can be determined from the drain current equations of NM₁ and NM₂ mentioned below:

$${I_1} = {k_1}left( {left( {{V_{ m{c}}} - {V_{{ m{tn}}1}}} ight){V_{ m{z}}} - frac{{V_{ m{z}}^2}}{2}} ight),$$

(19)

$${I_2} = {k_2}left( {frac{{V_{ m{z}}^2}}{2}} ight).$$

(20)

The condition to be fulfilled for proper operation is |V_in| = V_DS1 < V_GS1 ? V_tn1 where k₁ is the transconductance parameter and V_tn1 is the threshold voltage of M₁. The value of V_c should be selected greater than threshold voltage V_tn1.

$${I_{ m{R}}} = kleft[ {left( {{V_{ m{c}}} - {V_{{ m{tn}}1}}} ight){V_{ m{z}}}} ight].$$

(21)

The transconductance parameters of both transistors are assumed to be the same k₁ = k₂ = k. The non-linear term of current I₁ got cancelled by I₂ and equivalent resistance is

$$R = { m{}}frac{{{V_{ m{z}}}}}{{{I_{ m{R}}}}} = frac{1}{{kleft( {{V_{ m{c}}} - {V_{{ m{tn}}1}}} ight)}}.$$

(22)

This equivalent resistance is tunable by the value of V_c and is used in realization of resistor R in the quadrature oscillator.



After the routine analysis of the circuit, the characteristic equation of the quadrature oscillator is

$${s^2}R{C_1}{C_2} + s{C_2}left( {1 - {g_{{ m{m}}1}}R} ight) + {g_{{ m{m}}1}}{g_{{ m{m}}2}}R = 0.$$

(23)

According to Eq. (23), the oscillations condition and its frequency are

$${g_{{ m{m}}1}}R = 1,$$

(24)

$${f_{ m{o}}} = frac{1}{{2pi }}sqrt {frac{{{g_{{ m{m}}1}}{g_{{ m{m}}2}}}}{{{C_1}{C_2}}}} .$$

(25)

It can be seen that the condition of oscillation and frequency are independent of each other where the oscillation condition can be programmed by R and frequency can be tuned by g_m2. The sensitivity analysis of the circuit is

$$S_{{ m{gm}}1}^{{ m{fo}}} = { m{}}S_{{ m{gm}}2}^{{ m{fo}}} = S_{{ m{C}}1}^{{ m{fo}}} = S_{{ m{C}}2}^{{ m{fo}}} = 0.5,$$

(26)

which is found to be advantageous to the circuit.

3.2
Schmitt trigger circuit

Fig. 5 illustrates the Schmitt trigger circuit based on the proposed FGMOS based CDTA. Only a single CDTA block is utilized to implement the Schmitt trigger operation. The maximum value of output current (I_out) will reach up to ± I_B3. The expression for I_out is






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Figure5.
Schmitt trigger using FGMOS CDTA.

$${I_{{ m{out}}}} = left{ {begin{array}{*{20}{c}}{ - I_{ m {B3}},;;{I_{{ m{in}}}} geqslant {I_{{ m{x}} - }}},{I_{ m {B3}},;;{I_{{ m{in}}}} leqslant {I_{{ m{x}} - }}}.end{array}} ight.$$

(27)

4.
Simulation results and comparison

The simulations of FGMOS based CDTA and its applications are carried out using SPICE and TSMC CMOS 0.13 μm technology. The aspect ratios of all transistors are given in Table 1. The supply voltage is ±1.4 V and biasing currents are set to I_B1 = I_B1 = 85 μA, I_B3 = 100 μA. The macro model to realize FGMOSFETs is given in appendix A.

Transistor	Aspect ratio
M1–M6	8
M7–M10	5
M11–M12	10
M13–M14	10
M15–M20	5
M21–M24	4
NM1, NM2	5

Table1.
Aspect ratios of the FGMOS CDTA transistors.



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Transistor	Aspect ratio
M1–M6	8
M7–M10	5
M11–M12	10
M13–M14	10
M15–M20	5
M21–M24	4
NM1, NM2	5

The DC transfer characteristics of FGMOS based CDTA are given in Fig. 6. It is clear that the input linear range is from –-130 to +130 μA. The current transfer characteristics are shown in Figs. 7 to 10 for I_z/I_p, I_z/I_n, I_x+/I_p and I_x+/I_n with the measured bandwidth of the proposed FGMOS based CDTA at biasing current for I_B3 = 100 μA. The transconductance of the proposed circuit with respect to frequency is depicted in Fig. 11.






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Figure6.
(Color online) DC transfer characteristics of FGMOS CDTA.






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Figure7.
(Color online) Current gain I_z/I_p for I_B3 = 500 μA.






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Figure10.
(Color online) Current gain I_x-/I_p for I_B3 = 500 μA.






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Figure11.
(Color online) Transconductance of FGMOS CDTA.




The transconductance range and power dissipation of FGMOS based CDTA for the given variation in biasing current I_B3 from 50 to 500 μA are given in Table 2. The minimum value of g_m is 1.2 mA/V for I_B3 = 50 μA whereas the maximum achieved value is 6.21 mA/V at I_B3 = 500 μA. The power dissipation varies from 0.442 to 2.60 mW for this I_B3 range. It can be seen that the transconductance measured for the proposed block is quite higher than the conventional CDTA implementation^[25], which ranges from 0.414 to 1.20 mA/V for I_B3 varying from 50 to 500 μA. Fig. 12 displays the variation in the transconductance of the FGMOS CDTA with respect to temperature. There are minor changes in the value of transconductance as temperature is varying from 75 to ?25 °C, which will not affect the performance of the FGMOS CDTA.






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Figure8.
(Color online) Current gain I_z/I_n for I_B3 = 500 μA.






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Figure9.
(Color online) Current gain I_x+/I_p for I_B3 = 500 μA.

Exisitng CDTA[25]				FGMOS CDTA
Biasing current (μA)	Gm (mA/V)	Power dissipation (mW)		Biasing current (μA)	Gm (mA/V)	Power dissipation (mW)
50	0.414	1.50		50	2.30	0.442
100	0.612	2.07		100	3.74	0.517
200	0.844	3.18		200	4.71	0.670
300	0.994	4.29		300	5.47	0.873
400	1.1	5.40		400	5.72	1.26
500	1.20	6.51		500	6.21	2.60

Table2.
Comparison of transconductance and power dissipation.



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Exisitng CDTA[25]				FGMOS CDTA
Biasing current (μA)	Gm (mA/V)	Power dissipation (mW)		Biasing current (μA)	Gm (mA/V)	Power dissipation (mW)
50	0.414	1.50		50	2.30	0.442
100	0.612	2.07		100	3.74	0.517
200	0.844	3.18		200	4.71	0.670
300	0.994	4.29		300	5.47	0.873
400	1.1	5.40		400	5.72	1.26
500	1.20	6.51		500	6.21	2.60

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Figure12.
(Color online) Variation in transconductance w.r.t temperature.




The summarized simulation results are given in Table 3. The linear range of the proposed CDTA is ±130 μA at a supply voltage of ±1.4 V. The maximum value of transconductance of 6.21 mA/V at I_B3 = 500 μA with adjustable range from 1.1 to 6.21 mA/V for I_B3 range 20?500 μA. The ?3 dB bandwidth for all current transfer ratios is also mentioned in Table 3.

	Parameter	Simulation result
	Supply voltage (γ)	±1.4
	Technology (μm)	0.13
	Power dissipation (mW)	2.60
	Bias currents	IB1 = 85 μA, IB2 = 85 μA, IB3 = 100 μA
	Iz/Ip (?3 dB bandwidth)	2.01 GHz
	Iz/In (?3 dB bandwidth)	1.77 GHz
	Ix+/Ip (?3 dB bandwidth)	82 MHz
	Ix+/In (?3 dB bandwidth)	71.9 MHz
	Max. value of transconductance	6.21 mA/V
	CDTA linear range	?130 to +130 μA
	TA linear range at IB3 = 500 μA	?300 to +300 μV

Table3.
Summary of simulation results of FGMOS CDTA.



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	Parameter	Simulation result
	Supply voltage (γ)	±1.4
	Technology (μm)	0.13
	Power dissipation (mW)	2.60
	Bias currents	IB1 = 85 μA, IB2 = 85 μA, IB3 = 100 μA
	Iz/Ip (?3 dB bandwidth)	2.01 GHz
	Iz/In (?3 dB bandwidth)	1.77 GHz
	Ix+/Ip (?3 dB bandwidth)	82 MHz
	Ix+/In (?3 dB bandwidth)	71.9 MHz
	Max. value of transconductance	6.21 mA/V
	CDTA linear range	?130 to +130 μA
	TA linear range at IB3 = 500 μA	?300 to +300 μV

Table 4 compares the proposed FGMOS based CDTA with existing ones. It is quite clear that the proposed active block is operating at lower supply voltage (±1.4 V) and dissipates low power (2.60 mW) with good features such as wide linearity range (±130 μA) as compared to other CDTA implementations. The maximum transconductance measured (6.21 mA/V) is also comparable to the CDTA realization mentioned in Ref. [24].

Parameter	Ref. [14]	Ref. [15]	Ref. [24]	Ref. [25]	FGMOS CDTA
Supply voltage (eV)	±2.5	±1.8	±2	±2.5	±1.4
Technology (μm)	0.35	0.35	0.18	0.5	0.13
Power dissipation (mW)	4.4	6.31	4.60	6.51	2.60
Max. value of transconductance (mA/V)	?	?	7.32	1.20	6.21
CDTA linear range (μA)	±60	±80	±100	?	±130

Table4.
Comparison of FGMOS CDTA with existing CDTAs.



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Parameter	Ref. [14]	Ref. [15]	Ref. [24]	Ref. [25]	FGMOS CDTA
Supply voltage (eV)	±2.5	±1.8	±2	±2.5	±1.4
Technology (μm)	0.35	0.35	0.18	0.5	0.13
Power dissipation (mW)	4.4	6.31	4.60	6.51	2.60
Max. value of transconductance (mA/V)	?	?	7.32	1.20	6.21
CDTA linear range (μA)	±60	±80	±100	?	±130

The quadrature oscillator circuit is designed using two FGMOS based CDTAs, a MOS resistor and two capacitors. For simulation, the aspect ratios of N_M1 and N_M2 are 5 : 1. Fig. 13 shows the equivalent resistance of the resistor ranging from 0.54 to 1.68 k? if control voltage V_c is varied from 0.6 to 1.6 V.






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Figure13.
(Color online) Equivalent resistance of MOS resistor.




The transconductance values of both CDTAs are kept 6.21 mA/V at a bias current of 500 μA and the values of capacitors C₁ and C₂ are 100 pF. The resistor is set to 1.5 k? to meet the condition of oscillation. The theoretical frequency of oscillation is 9.8 MHz. The transient response of both output currents I_o1 and I_o2 is depicted in Fig. 14 illustrating the amplitude of 72 μA. Both the output currents are quadrature to each other.






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Figure14.
(Color online) Current outputs of quadrature oscillator.




The transient result of the Schmitt trigger implemented using FGMOS based CDTA is shown in Fig. 15. A sinusoidal input current of amplitude 130 μA and frequency 1 MHz is applied to the n terminal of the active block. A square waved output current is observed at the x-terminal with saturation levels of ±100 μA verifying the operation of a Schmitt trigger. Thus, both units are validating the effectiveness of the proposed CDTA variant.






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Figure15.
(Color online) Transient response of Schmitt trigger.

5.
Conclusion

FGMOS based CDTA is realized for low voltage low power analog signal processing applications. The proposed FGMOS CDTA operates at the lower supply voltage of ±1.4 V with power dissipation of 2.60 mW, which is remarkably low. A wider input linear range is achieved with maximum transconductance value of 6.21 mA/V. Two applications of the proposed variant of active block are presented such as quadrature oscillator using the MOS resistor and Schmitt trigger. The efficacy of the proposed CDTA and its applications are validated by simulations. The suggested blocks are beneficial for low voltage analog signal processing applications.

Appendix A

Floating gate MOSFET



Floating gate MOSFET (FGMOSFET) is a variant of MOSFET for low voltage analog design. A floating gate is formed using two layers of polysilicon to form the first and secondary gates. It has N number of inputs on the floating gate. Fig. A1 shows the FGMOS with N input and its equivalent circuit considering all capacitances and connections.






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FigureA1.
(a) Floating gate MOSFET with N inputs. (b) Equivalent circuit floating gate MOSFET.




The capacitance of FGMOSFET can be given as a sum of all capacitances C_N where it ranges from 1 to N including capacitance at the floating gate as well as parasitic capacitance present in the MOSFET. The voltage at the floating gate is V_FG and expressed in Eq. (A2) after assuming that there is isolation at the floating gate and V_i are the input voltages and Q_FG is the amount of charge trapped in FGMOS while fabricating it.

$$hspace*{fill} {C_{ m{T}}} = {C_{{ m{GB}}}} + {C_{{ m{GD}}}} + {C_{{ m{GS}}}} + { m{}}mathop sum limits_{i = 1}^N {C_{ m{N}}},hspace*{fill}tag{A1}$$

$$hspace*{fill} {V_{{ m{FG}}}} = mathop sum limits_{i = 1}^N frac{{{C_{{i}}}}}{{{C_{ m{T}}}}} + frac{{{C_{{ m{GSVD}}}}{ m{}}}}{{{C_{ m{T}}}}} + frac{{{C_{{ m{GSV}}{ m{S}}}}{ m{}}}}{{{C_{ m{T}}}}} + frac{{{Q_{{ m{FG}}}}}}{{{C_{ m{T}}}}}. hspace*{fill}tag{A2}$$

The current of the FGMOS transistor operating in linear and saturation regions are expressed as






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FigureA2.
Model of floating gate MOSFET with two inputs.

$$hspace*{fill}begin{split} {I_{text{D}}} =& frac{{mu {C_{{text{ox}}}}W}}{{2L}}left[ {left( {sumlimits_{i = 1}^N {frac{{{C_{{i}}}{V_{text{i}}}S}}{{{C_{text{T}}}}}} + frac{{{C_{{text{GD}}}}{V_{{text{DS}}}}}}{{{C_{text{T}}}}}} ight.} ight. hfill & left. {left. { + frac{{{C_{{text{GB}}}}{V_{{text{BS}}}}}}{{{C_{text{T}}}}} + frac{{{Q_{{text{FG}}}}}}{{{C_{text{T}}}}} - {V_{text{T}}}} ight){V_{{text{DS}}}} - {{frac{{{V_{{text{DS}}}}}}{2}}^2}} ight] ,end{split} hspace*{fill}tag{A3a}$$

$$hspace*{fill} {I_{ m{D}}} = frac{{mu {C_{{ m{ox}}}}W}}{{2L}}{left( {mathop sum limits_{i = 1}^N frac{{{C_{{i}}}{V_{ m{i}}}S}}{{{C_{ m{T}}}}} + frac{{{C_{{ m{GD}}}}{V_{{ m{DS}}}}{ m{}}}}{{{C_{ m{T}}}}} + frac{{{C_{{ m{GB}}}}{V_{{ m{BS}}}}{ m{}}}}{{{C_{ m{T}}}}} + frac{{{Q_{{ m{FG}}}}}}{{{C_{ m{T}}}}} - {V_{ m{T}}}} ight)^2}.hspace*{fill}tag{A3b}$$

(A3b)

The aspect ratio and threshold voltage of FGMOS are W/L and V_T, and V_S, V_D, V_B are terminal voltages of FGMOS at terminals.



If we assume that the sum of all capacitances C_i is very large compared to parasitic capacitances CGD, CGB and QFG, then Eqs. (A3a) and (A3b) can be simplified as

$$hspace*{fill} {I_{ m{D}}} = frac{{mu {C_{{ m{ox}}}}W}}{{2L}}left( {left( {mathop sum limits_{i = 1}^N frac{{{C_{{i}}}{V_{ m{i}}}S}}{{{C_{ m{T}}}}} - {V_{ m{T}}}} ight){V_{{ m{DS}}}} - {{frac{{{V_{{ m{DS}}}}}}{2}}^2}{ m{}}} ight),hspace*{fill}tag{A4a}$$

(A4a)

$$hspace*{fill}{I_{ m{D}}} = frac{{mu {C_{{ m{ox}}}}W}}{{2L}}{left( {mathop sum limits_{i = 1}^N frac{{{C_{{i}}}{V_{ m{i}}}S}}{{{C_{ m{T}}}}} - {V_{ m{T}}}} ight)^2}.hspace*{fill}tag{A4b}$$

(A4b)

The macro model of the FGMOS transistor^{[1, 27]} given in Fig. A2 is used to simulate it to overcome the issue of dc convergence. A resistor of large value is connected in parallel with each capacitor to form floating gate inputs and the condition to be fulfilled is R_i = 1/(kC_i) = 1000 G? where k is the transconductance parameter and C_i is the respective input capacitance value.