Author(s): Zhang, Z (Zhang, Zhao); Liu, LY (Liu, Liyuan); Qi, N (Qi, Nan); Liu, J (Liu, Jian); Wu, NJ (Wu, Nanjian)
Source: JAPANESE JOURNAL OF APPLIED PHYSICS Volume: 59 Special Issue: SG Article Number: SGGL05 DOI: 10.35848/1347-4065/ab709c Published: APR 1 2020
Abstract: This paper presents a 20 GHz low-phase-noise low-power LC voltage-controlled oscillator (VCO). It adopts a fully differential tuning varactor, a coarse and a fine capacitor array to cover wide tuning range with a small tuning gain to reduce the amplitude-to-phase noise conversion, A layout floorplan is proposed to reduce the impact of the parasitic resistance of the interconnect and thus improve the Q of the LC tank in the VCO. Hence, the phase noise can be reduced without increasing power consumption. Post-layout simulation results show that the VCO with the proposed layout floorplan can get the phase noise reduction from 1.6 to 3.3 dB compared to the VCO with other layout floorplans in the case of the same power consumption. Implemented in a 65 nm CMOS process, the prototype achieves 17.6-24.3 GHz frequency range, -124 dBc/Hz@10 MHz phase noise at 20.1 GHz carrier frequency, 4.9 mW DC power, and -193.3 dB figure-of-merit. (C) 2020 The Japan Society of Applied Physics
Accession Number: WOS:000519630000127
Conference Title: International Conference on Solid State Devices and Materials (SSDM)
Conference Date: SEP 02-05, 2019
Conference Location: Nagoya Univ, Nagoya, JAPAN
Conference Sponsors: Japan Soc Appl Phys
Conference Host: Nagoya Univ
ISSN: 0021-4922
eISSN: 1347-4065
Full Text: https://iopscience.iop.org/article/10.35848/1347-4065/ab709c