1.
Introduction
SiC power devices are one of the most popular devices in power devices because of the superior properties of 4H-SiC, such as a wide bandgap and a high critical electric field. The 4H-SiC MOSFETs as unipolar devices, have been the primary focus of research, and extensively investigated. However, the drift-layer resistance of unipolar devices increases as the blocking voltage, which are not suitable for the use of ultra high voltage applications[1, 2]. In this case, 4H-SiC bipolar devices such as IGBTs become an attractive choice to replace the 4H-SiC MOSFETs because of their low on-resistance caused by the conductivity modulation[3, 4].
Since the early 2000 s, Cree has reported on SiC IGBTs with high blocking voltage. The earlier SiC IGBTs were fabricated with a p-channel, because n-channel IGBTs use p-type SiC substrates that introduce a high resistance in series with the device[5]. However, n-channel IGBTs exhibit more values in practical use, particularly in low-frequency switching applications[6].
So the development of n-channel 4H-SiC IGBTs with ultra-high voltage is quite desirable. In our study, considering large-resistance p-type SiC substrates, we grew all critical epitaxial layers on an n-type SiC substrate[7]. When we finish fabricating top-side structure, we remove the n-type SiC substrate by grinding. So the p+ substrate is replaced by a thin p+ epitaxial layer. The on-state characteristics of the n-channel 4H-SiC IGBT showed a current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V. The blocking voltage was 13 kV with the leakage current of 10 μA.
2.
Device design and fabrication
Fig. 1 shows a schematic cross-sectional structure of the fabricated n-channel 4H-SiC IGBT. The device is very similar to the 4H-SiC n-channel MOSFET, especially the top side structure. The main difference between n-channel MOSFETs and n-channel IGBTs is the backside structure, which adds an extra p–n junction. So the surface fabrication processes used in n-channel MOSFETs can be used in n-channel IGBTs[8].
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Figure1.
Schematic cross-sectional structure of the fabricated n-channel 4H-SiC IGBT.
First, all critical epitaxial layers were grown on n-type 4H-SiC substrates (~350 μm): a 120 μm 2 × 1014 cm?3 n- drift layer, followed by a 5 μm 1 × 1018 cm?3 n+ field-stop (F-S) buffer layer and 10 μm 1 × 1019 cm?3 p+ collector layer. The F-S buffer was designed so that the high electric field of drift layer could drop to zero in a short distance, so the depletion region would not penetrate into the p+ collector. The thick epitaxial layer comprised the n? drift layer with doping concentrations of 2 × 14 cm?3 and F-S buffer to achieve a blocking voltage of 13 kV.
Similar to the surface fabrication process of the n-channel 4H-SiC MOSFET, the silicon dioxide (SiO2) served as the mask for the p-well, n+ emitter and p+ implantation. The p-well and p+ implantation were formed by multiple ion implantation of aluminum（Al）with different doses and energies respectively. The n+ emitter was formed by multiple ion implantations with nitrogen (N) ions. After the p-well and the n+ emitter implants, MOS channel length was formed whose actual length depended on Al ions and N ions horizontal expansion. All the implants were annealed for 30 min in argon (Ar) at 1650 °C with the graphite-cap technique.
Following the acid cleaning of wafer surface, the gate oxide was formed in the oxidation oven at 1175 °C for 180 min. A nitric oxide (NO) annealing technique at 1175 °C for 60 min was then used to reduce gate oxide interface trap density[9–11]. The oxide thickness is around 50 nm. After that, the poly-silicon as the gate electrode was deposited on the gate oxide. Ohmic contacts were formed by depositing nickel (Ni) as the n+ emitter contact. After the surface-side fabrication, the n-type substrate was removed by grinding. Considering that the elevated temperatures during the fabrication process of usual backside ohmic contact would damage the surface structure, laser annealing was used to form the collector ohmic contact. At last, the n-channel IGBT was fabricated and ready for testing.
3.
Results and discussion
Fig. 2 shows a blocking characteristic of the 4H-SiC n-channel IGBT with an active area of 1.06 mm2 at room temperature. The device has JTE edge termination[12–14]. During the measurement, the device is immersed in Flourinert oil. The blocking voltage of the n-channel IGBT is 13 kV with the leakage current of 10 μA at a gate voltage of 0 V.
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Figure2.
(Color online) A blocking characteristic of the 4H-SiC n-channel IGBT at room temperature, measured at VGS of 0 V.
Fig. 3 shows the on-state characteristics of the 4H-SiC n-channel IGBT at room temperature. At a collector voltage of 12.5 V and VG of 20 V, the collector current density is 24 A/cm2. A differential specific on-resistance is 140 mΩ·cm2 at this bias point. We also note that an “inflection point” exists at the Vc of 9 V and the collector current increases rapidly after this bias point. A reasonable explanation is that the conductivity modulation is taking place after this point, which will reduce the resistance of n? drift layer. The reason is the JFET resistance, formed by depletion regions extending into the drift layer, as shown in Fig. 4. The actual width of JFET region is reduced by the depletion regions extending, which causes a larger JFET resistance and prevents most of the channel electrons from entering the drift layer. But the holes from backside are still injected by the collector. The conductivity modulation does not occur until the collector voltage is large enough, and more holes were injected from the backside. The channel electrons enter the drift layer and the collector current increases rapidly. In Fig. 3, we also note that the curve interval is shortened at high gate voltage, because the channel electron mobility is a function of the surface electric field, and the increase of the gate voltage will decrease the channel electron mobility.
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Figure3.
(Color online) On-state characteristics of the 4H-SiC n-channel IGBT at room temperature.
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Figure4.
The actual width of JFET region is reduced by the depletion regions extending into the drift layer.
To confirm the explanation, the field-effect channel mobility (μFE)–VG characteristics at drain voltage (VD) = 0.1 V for lateral n-channel SiC-MOSFETs were obtained[15] and shown in Fig. 5. The channel resistivity is a function of the channel electron mobility, and the resistivity decreases when the mobility increases. In Fig. 5, we can see that the μFE peak value of 20 cm2/(V·s) was achieved at VG of 20 V, which is a positive parameter for the μFE in SiC devices. It was noted that the channel resistances accounted for a small proportion of the total resistance. The resistance of the JFET region is so large that it dominates the total resistance. To improve the on-state capability, the concept of carrier storage layer (CSL)[16], which is a moderately doped n-type layer placed near the blocking junction will be used to reduce the JFET resistance in our future work.
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Figure5.
The field-effect channel mobility (μFE)–VG characteristics at VD of 0.1 V for lateral n-channel SiC-MOSFETs.
4.
Summary
A SiC n-IGBT with a drift layer thickness of 120 μm was fabricated successfully, demonstrating a blocking voltage of 13 kV with the leakage current of 10 μA. The n-IGBTs showed a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage (VG) was 20 V and a differential specific on-resistance was 140 mΩ·cm2. Because of the large resistance of the JFET region, the on-state characteristics of the 4H-SiC n-channel IGBT are not ideal. A carrier storage layer (CSL) will be used to minimize the effects of the JFET resistance in our future work.
