1.
Introduction

Diamond has been considered as the ultimate semiconductor material due to its outstanding properties^[1]. However, the lack of large area substrate and suitable dopants has severely obstructed the wide application of the single crystal diamond (SCD)^[2–4]. The two dimensional hole gas (2DHG) at a hydrogen terminated diamond (H-diamond) surface induced by atmospheric adsorbates^[5] or solid-state acceptor transfer doping^[6–8] has been widely used to develop diamond electronic devices. Currently, the H-diamond field effect transistors (FETs) have achieved the cut-off frequency (f_T) of 53 GHz^[9] and the maximum oscillation frequency (f_MAX) of 120 GHz^[10], and the high breakdown voltage of more than 1 kV has also been realized^[11]. As one of the transfer doping dielectrics^[12], a 10-nm-thick MoO₃ layer deposited on H-diamond surface could induce a 2DHG with a sheet hole density as high as 10¹⁴ cm^?2[13]. We have reported the SCD MOSFET with the MoO₃ gate dielectric deposited on an H-diamond surface preserving atmospheric-adsorbate-induced 2DHG very recently^[14]. The device shows a low on-resistance (R_ON) and a high transconductance compared with the diamond MOSFETs with other dielectrics such as HfO₂^[15], and ZrO₂^[16]. However, the transfer doping effect is not evidently shown. What is more, the extracted permittivity of MoO₃ is quite low compared with the previously reported data^[17]. We have suggested there may be aluminum oxide at the interface between MoO₃ and the aluminum gate metal.



In this paper, we report the device characteristics of the SCD MOSFET with MoO₃ gate dielectric and gold gate metal, and make a comparison with our Al/MoO₃-gated device to investigate the characteristics of MoO₃ and verify the existence of aluminum oxide at the Al/MoO₃ interface.

2.
Experiment details

The SCD was grown on a HPHT (100) seed in a microwave plasma chemical vapor deposition (MPCVD) chamber with only methane and hydrogen introduced in the growth. In order to achieve the stable thermal exchange between the diamond sample and the water chiller during growth, the seed was brazed on a molybdenum holder using a 25-μm-thick gold layer. Before growth the seed was etched in the hydrogen plasma atmosphere with the addition of 2% oxygen for one hour. The purity of the hydrogen and methane used in this experiment was 6N and 5N5, respectively. During growth the pressure was maintained in 320 mbar, while the growth temperature and microwave power were in the range of 900–925 °C and 3.8 kW, respectively. The total gas flow rate and methane concentration were 200 sccm and 6%, respectively. After growth, the as-grown SCD was cut from the seed by laser and polished to achieve the surface root mean square (RMS) roughness below 1 nm. The quality of the CVD grown SCD was characterized by an X-ray diffractometer (XRD).



Based on the grown SCD plates, we have fabricated the H-diamond MOSFETs. Fig. 1 shows a schematic diagram of the device fabrication processes. Firstly, the substrate was immersed in the H₂SO₄/HNO₃ (1 : 1) mixture at 250 °C for one hour to remove the non-diamond phase and obtain the oxygen terminated diamond (O-diamond) surface. Then the samples were kept in hydrogen plasma for 10 min at 900 °C to generate a hydrogen-terminated surface, and then cooled down to room temperature in a H₂ gas flow. Before any device fabrication process, we measured the sheet resistivity, carrier concentration and carrier mobility of the H-terminated diamond substrate by using HL5500 equipment. Two substrates for Al and Au gated devices show similar electrical properties. The substrate for the FETs with Au gate metal shows the carrier mobility, carrier concentration and sheet resistivity of 106 cm²/(V·s), 5.90 × 10¹² cm^?2 and 9.91 kΩ, respectively. The substrate for the FETs with Al gate metal shows the carrier mobility, carrier concentration and sheet resistivity of 103 cm²/(V·s), 5.67 × 10¹² cm^?2 and 10.68 kΩ, respectively. After this, a 100-nm-thick layer of gold was deposited on the H-diamond surface by thermal evaporation to prevent the surface from contacting the photoresist during the device process^[18]. At the same time, the gold layer provides an ohmic contact due to the unpinned nature of the H-terminated diamond surface and the proper work function of the gold^[19]. After active-region lithography and wet etching of gold in a KI/I₂ solution, the diamond surfaces around the outside edges of the devices were exposed to low power oxygen plasma treatment to form the isolation regions due to pinning the Fermi-level of the O-terminated surface at approximately 1.7 eV above the valence band edge^[20]. After the gate window lithography followed by Au selective wet etching, source and drain contacts of the devices are formed, and the lateral etching of gold below the photoresist gives rise to the gap between the source (or drain) and the gate metal yet to be deposited. Then the 40-nm-thick MoO₃ and 100-nm-thick layer of gold deposition and lift-off were performed to form the gates of the devices. Finally, the H-diamond MOSFET with the gate length of 6 μm was achieved. The direct current characteristics were measured at room temperature by using a Keithley 4200 semiconductor parameter analyzer.






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Figure1.
(Color online) Schematic diagram of the device fabrication processes.

3.
Result and discussions

The picture of the CVD grown SCD after cutting from seed and polishing carefully is shown in the inset of Fig. 2. The single crystal diamond with the maximum width about 10 mm has been achieved, which is the biggest one among reported results as far as we know. The full width at half maximum of the (004) rocking curve is measured to be 37.91 arcsec (Fig. 2), which is comparable to the result of the electronic grade single crystal diamond (34.98 arcsec) commercially obtained from Element Six Ltd. After hydrogen plasma treatment, the surface of the sample was characterized by an atomic force microscope (AFM). The result is shown in Fig. 3. The RMS roughness of the post H-diamond surface is 0.522 nm. We also obtained the AFM morphology of the MoO₃ layer with the thickness of 10 and 40 nm. The results are shown in Fig. 4. The 10-nm-thick MoO₃ shows the RMS roughness of 0.302 nm, and some pit depths to 3.9 nm exist in the layer. The 40-nm-thick MoO₃ layer shows the RMS roughness of 0.240 nm.






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Figure2.
(Color online) XRD result of (004) rocking curve of the CVD grown SCD.






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Figure3.
(Color online) Surface morphology of the SCD after hydrogen plasma treatment.






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Figure4.
Surface morphology of the (a) 10 nm and (b) 40 nm MoO₃ layer.




The output characteristics of the transistor with a gate length of 6 μm (Fig. 5) demonstrate a saturation drain current (I_Dsat) of ?30 mA/mm and an on-resistance (R_ON) of 71.05 Ω·mm at the V_GS of ?1.5 V. Compared with our diamond MOSFET with 4-μm Al/MoO₃ gate^[14], the I_Dsat value is at the same level, and the R_ON value is even lower. Note that drain current appears at the V_DS = 0 V, and it indicates the presence of gate leakage current.






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Figure5.
(Color online) Output characteristics of the H-diamond MOSFET.




We measured the gate current–voltage (I_G–V_G) characteristics of the gate–drain diode (Fig. 6). A relatively high gate leakage current is demonstrated for both forward and reverse bias, and the current is about four orders of magnitude higher than the Al/MoO₃-gated transistor, though the MoO₃ layer used in this report has a four times thickness (40 nm). We have conjectured that maybe the MoO₃ dielectric was fairly leaky. To test the MoO₃ dielectric further, on a corner of this diamond sample we have deposited a 40-nm-thick MoO₃ layer on the FETs with all the device processes mentioned in part 2 finished, and measured the leakage current across the device isolation region with the MoO₃ layer on an O-diamond surface. The distance between the gold electrodes, the drain for a FET and the source for a neighboring FET, was 20 μm. The measured current is below 10^?7 A at the voltage of 5 V, and it is at the same level with the leakage of the device isolation region with no MoO₃ layer deposited, so the MoO₃ layer on the O-diamond surface does not bring observable extra leakage.






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Figure6.
(Color online) Gate current–voltage characteristics of the MoO₃/H-diamond MOS structure.




Based on all these phenomena observed on H-diamond MOSFET with MoO₃ gate dielectric and gold or aluminum gate metal, we suggest that the MoO₃ dielectric on O-diamond surface shows a much better insulating property than the prototype on H-diamond. This difference indicates there should be a surface transfer doping effect of the MoO₃ layer on H-diamond even when the atmospheric-adsorbate induced 2DHG was preserved after MoO₃ deposition in our cases. The effect leads to electrons transferring to the MoO₃ layer from H-diamond surface, and so the conductivity of the MoO₃ layer increases. Then the much lower leakage of Al/MoO₃/H-diamond MOS structure than that of the Au/MoO₃/H-diamond structure could be attributed mainly to the appearance of unintentionally introduced aluminum oxide as an insulating layer at the interface between aluminum and the MoO₃ layer.



The lower R_ON of the Au/MoO₃-gated diamond MOSFET may indicate higher hole density in the channel because the sheet hole density for the MoO₃ transfer doped H-diamond will increase with the increasing thickness of the MoO₃ layer^[13]. Meanwhile, the transfer characteristic of the transistor shows the maximum transconductance (g_mmax) of 15 mS/mm, and the threshold voltage (V_TH) of 1.4 V (Fig. 7). That is to say, only about 50 % g_mmax reduction occurred for our MoO₃-gated MOSFET with the gold gate compared with the one with the aluminum gate at the same gate voltage (g_mmax = 29 mS/mm at V_GS = ?1.5 V)^[14]. Based on the changes of gate length, MoO₃ layer thickness and V_TH and the same device process, this also supports that the hole density in the channel increases in the Au/MoO₃-gated diamond MOSFET.






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Figure7.
(Color online) Transfer characteristics of the H-diamond MOSFET.




In order to make a contrastive study of the interface between Al/MoO₃ and Au/MoO₃, we fabricated the Au/MoO₃/Au and Al/MoO₃/Au structure with the same thickness of metal and oxide. Then, we measured the I–V characteristics of the structure. The results are shown in Fig. 8. The Au/MoO₃/Au structure shows an almost symmetrical I–V curve (Fig. 8(a)), and the current is higher than the Al/MoO₃/Au structure (Fig. 8(b)). In addition, the shape of the I–V curve of the Au/MoO₃/Au structure is almost the same with the gate current of our FET. However, the value of the current is lower than the gate leakage current. There is no transfer doping effect existing in the metal–MoO₃–metal structure. Thus, the current of the metal–MoO₃–metal structure is very low.






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Figure8.
(Color online) The I–V curve of (a) Au/MoO₃/Au and (b) Al/MoO₃/Au structure.




Based on the above analyses, we can conclude that aluminum oxide exists in the interface between the Al and MoO₃, which contributes to the low gate leakage current of the Al gate devices. In order to obtain the direct evidences for the generation of aluminum oxide between Al/MoO₃ layers, we deposited the Al (20 nm)/MoO₃ (40 nm) on the insulated substrate. Then we measured the Al surface, the inner of the Al metal and the interface between Al and MoO₃ by using X-ray photoelectron spectroscopy. We etched the Al metal using argon plasma in order to obtain the inner of Al and the interface between Al/MoO₃ layers. The results of the XPS spectrum are shown in Fig. 9. The spectra obtained at the interface is similar to the result obtained at the Al surface and is different with the inner of the Al. Fig. 10 shows the spectrum of Al peaks. We can see clearly the difference of the peaks. At the surface and the interface, there is higher peak intensity at a high binding energy. At the surface of Al, the Al is exposed to the air atmosphere. Thus, the Al at the surface will be oxidized to aluminum oxide. The result in the interface is similar to the surface, which indicates the presence of aluminum oxide at the interface. The aluminum oxide at the interface is originally from the reaction of Al and the oxygen in MoO₃.






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Figure9.
(Color online) XPS results of the Al metal surface, inner of the Al metal and the interface between Al and MoO₃.






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Figure10.
(Color online) Spectrum of the Al related peaks of (a) the Al metal surface, (b) the inner of the Al metal, and (c) the interface between Al and MoO₃.

4.
Conclusion

The SCD with the maximum width about 10 mm has been grown by MPCVD and the quality of the CVD grown SCD is relatively high. Based on the CVD grown SCD, the H-diamond MOSFET with Au/MoO₃ gates were fabricated. The device with a 6-μm Au/MoO₃ gate shows lower on-resistance, quite high current, transconductance and high gate leakage current compared with the prototype with a 4-μm Al/MoO₃ gate already reported by our group. We have directly demonstrated the existence of aluminum oxide in the interface between Al and MoO₃ by X-ray photoelectron spectroscopy measurement, and there should be a surface transfer doping effect of the MoO₃ layer on H-diamond even though the atmospheric-adsorbate induced 2DHG was preserved after MoO₃ deposition.