1.
Introduction
Ge is a promising channel material for MOSFETs due to its significantly higher electron and hole mobility than Si and the compatibility with CMOS processes[1, 2]. High mobility Si-based Ge MOSFETs have been achieved widely[3–5]. GOI, similar to Si on insulator (SOI), also provides significant advantages over bulk Ge in CMOS circuits due to the reduction of leakage currents and parasitic capacitance[6]. Moreover, Ge is also an attractive semiconductor for Si-based photonics[7–9]. Ge has a direct bandgap of 0.8 eV, which has a great potential in developing Si-based near-infrared photodetectors. Si-based normal-incidence[10, 11] and waveguide Ge photodetectors[12] have been achieved with high performance. Based on the Franz-Keldysh (FK) effect[13, 14] and quantum-confined Stark effect[15], high speed Si-based Ge optical modulators were reported. Besides, Ge is a pseudo-direct bandgap material which allows Ge to be a promising candidate for light emission[16–18]. Compared with bulk Ge, GOI is a desirable system for Si-based photonics due to the good optical confinement.
In the past decade, numerous techniques have been performed to fabricate GOIs. Layer transfer is the most commonly technique to obtain large size GOIs. Similar to the fabrication process of SOI, a thin Ge layer is cut from Ge wafer by H+ implantation and bonded to the Si-based insulator substrate[19–21]. GOIs with 100–200 mm diameter and 50–200 nm thickness were achieved by this technique[22]. However, the fabrication process of layer transfer is highly complex. Surface cleaning, hydrophilic treatment, and thermal matching between Si and Ge need further optimization efforts; if not, they would often cause serious problems in the bonding and annealing steps. Oxidation-induced Ge condensation is an effective technique to obtain ultrathin high strained GOIs by selective oxidation of Si atoms from low Ge content SiGe epitaxial layer on SOI substrate[23]. 7 nm-thickness GOIs with 1.1% compressive strain[24] and 12 nm-thickness GOIs with 0.67% tensile strain[25] were reported respectively. The hole mobility of MOSFETs based on the GOIs can reach 410 cm2V?1s?1[26]. However, the complex process, high temperature budget (1050 °C/3 h), and Ge condensation induced crystal defects limit the application of this technique[27]. Al-induced crystallization of amorphous-Ge at low temperature has also been performed to fabricate GOI[28]. This method has more advantages in using some substrates which have limited temperature budget, such as glass or plastic substrates. However, this method is a time consuming process and has difficulties in achieving high quality.
Recently, a novel technique to fabricate GOI has been described, in which single crystal Si was used as a crystal seed for epitaxial growth. This method realized the fabrication of high quality defect-free single crystal Ge strips on insulators, which has enabled monolithic integration of Ge transistors with Si transistors on a Si substrate. This paper introduces the RMG technique and reviews the recent efforts and progress in RMG including fundamental researches (growth dimension, growth mechanism, growth orientation, concentration distribution, and strain status of the GOIs) and device applications (MOSFETs and photodetectors).
2.
Rapid melt growth
In 2004, Liu et al. from Stanford University firstly proposed the RMG technique[29], similar to Czochralski crystal growth, to fabricate high quality GOI by melting and crystallizing patterned Ge which is encapsulated by self-aligned micro-crucibles on Si substrates. Fig. 2(a) shows the cross-sectional schematic of RMG. Like a ‘necking effect’ in a nanoscale selective epitaxial growth process[30], this technique enables one to terminate the lattice mismatch induced dislocations in the seeding region and necking region. In the epitaxial growth region, the GOI has an excellent crystal quality with the defect density lower than 5 × 105 cm?2[31]. The surface roughness is found to be the same as that of the initial Ge film. High-resolution cross-sectional transmission electrical microscopy (TEM) pictures of the GOI and the Ge/SiO2 interface are shown in Fig. 1, which indicate the high quality of the GOI and the interface. Selective area diffraction (SAD) in the inset shows that the orientation of GOI, which is perpendicular to the Ge/SiO2 interface, is (001). This orientation is the same as that of the Si substrate.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-1.jpg'" class="figure_img" id="Figure1"/>
Download
Larger image
PowerPoint slide
Figure1.
(a) High-resolution TEM picture for the Ge stripe after crystallization. Its associated SAD pattern is in the inset. (b) High-resolution TEM picture for the Ge/bottom SiO2 interface.
The main process steps of RMG are shown in Fig. 2(b). (1) An insulator layer is grown on a Si substrate. Usually, the insulator layer is SiO2 or Si3N4, which has a high thermal stability. (2) The insulator layer is patterned and wet/dry etched to open seed windows through it. (3) An amorphous/polycrystalline Ge film is deposited on the substrate to cover seed windows and insulator layer. Thickness of the Ge film should be thicker than that of the insulator layer, which avoids disconnection of molten Ge in the necking region undergoing the annealing process. (4) Ge film is patterned into stripes. Every stripe has a head in contact with the Si substrate in a seed window. (5) A thick oxide cap layer is deposited to cover the Ge stripes, in which it suppresses agglomeration and evaporation of the molten Ge strips. (6) Rapid thermal annealing (RTA) is used for heating the wafer up to the temperature which is higher than the melting point of Ge for a few seconds. In the cooling process, molten Ge strips crystallize to single crystal GOIs starting from the seeding region. Obviously, all fabricating processes of RMG are simple and compatible with CMOS processes.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-2.jpg'" class="figure_img" id="Figure2"/>
Download
Larger image
PowerPoint slide
Figure2.
(a) Cross-sectional schematics of the RMG. (b) Process steps of RMG.
3.
Characterizations
3.1
Growth dimension
Size of a GOI is an important parameter for application, for a large size GOI has more fabrication flexibility than that of a smaller size one. Unfortunately, the width of the GOI grown by RMG is squeezed by the high interface energy between liquid Ge and the insulator layer, for molten Ge tends to aggregate and break the micro-crucible structure which surrounds it (see Fig. 3(a)). However, this phenomenon could be significantly depressed by reducing the width of the GOI. In this way, the width has to shrink to smaller than 5 μm[32], however, it is still large enough to fabricate integrated microelectronics and photonics devices. Figs. 3(b) and 3(c) show the optical micrographs of stable GOIs with width of 2 and 5 μm, respectively. The reported minimum width of the GOI is 130 nm[33], which indicates that RMG also has the potential to realize nanostructure materials, such as nanowires. The thickness of the GOI is more competitive than the width of it. Until now, GOIs with thicknesses of 22–950 nm have been achieved[33–36]. For integrated photonics devices, such as photodetectors, this thickness is thick enough to couple and absorb near infrared light effectively. In spite of this, the thickness is not thin enough for ultrathin MOSFETs. As the thickness of the GOI is smaller than 22 nm, the GOI is not only more likely to break in the necking region, because of the existence of the insulator below it, but also has intense lattice rotation along the stripe[34]. These phenomena would prevent the GOI from having high quality and application. However, the former phenomenon could be depressed by using an ultrathin insulator layer or SOI substrate, which reduce the step in the necking region. The latter phenomenon, lattice rotation, will be discussed later. The length of the GOI is dominated by the velocity of lateral growth and spontaneous nucleation. The length could be increased by using a suitable insulator layer and oxide cap layer, which depress the spontaneous nucleation process. Materials of the insulator layer including SiO2[32, 35], Si3N4[29, 37], HfO2[38], and La2O3[38] have been studied. When Si3N4 is used as the insulator layer, the length of the GOI even reaches 1 cm[37]. This length of the GOI could meet almost all requirements of applications.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-3.jpg'" class="figure_img" id="Figure3"/>
Download
Larger image
PowerPoint slide
Figure3.
(Color online) Optical micrographs of GOIs with different sizes. (a) GOI circle with diameter of 100 μm. (b) GOI stripes with width of 2 μm. (c) GOI stripes with width of 5 μm.
In spite of the limitation of width, several structures were developed to increase the integrated density of the GOI. In all approaches, using a GOI stripe array is the simplest way to increase density. Abdul et al. have studied the GOI stripe array with various widths and spacing[34]. The study’s result shows that stripe spacing as narrow as 0.5 μm is enough to depress agglomeration between adjacent stripes (3 μm width) and keep the GOI stripe array stable. However, in this method, GOI stripes in an array are independent of each other, which is not very practical for application. Therefore, GOI meshes are developed to overcome the problem. These GOI meshes including the square mesh and hexagonal mesh were not only achieved on Si (001), but in Si (110) and Si (111) substrate as well[39, 40]. The size of the GOI mesh could reach 500 × 250 μm2 by optimizing the shape and the size of the mesh. These GOI meshes would facilitate Ge based advanced devices on the Si platform.
As we know, the GOI stripe array and GOI mesh are two-dimension in-plane structures. The further three-dimension structure, vertically multiply stack structure, has also been realized by two steps RMG[41]. The below layer is SiGe on insulator (SGOI) which is fabricated by the first step RMG. Using the SiGe layer as a seed, the upper GOI layer is formed by the second step RMG. Moreover, vertically multiply stack GOI structure by one step RMG has been achieved by our group. The schematic structure and cross-sectional scanning electron microscope (SEM) images are shown in Figs. 4(a) and 4(b), respectively. To measure characterizations of the GOIs, the top Ge stripe was moved aside to show the bottom GOI (see Fig. 4(c)). In Fig. 4(d), the electron backscattered diffraction (EBSD) shows that the top GOI and bottom GOI have the same (001) orientation as the Si seed. This vertically multiply stack structure has a potential in three-dimensional integrated circuits with various functional devices on the Si platform. In the future, more and more novel structures will be designed to realize different functions.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-4.jpg'" class="figure_img" id="Figure4"/>
Download
Larger image
PowerPoint slide
Figure4.
(Color online) (a) Schematic structure of the vertically multiply stack GOI. (b) Cross-sectional SEM image of the GOI. (c) SEM image of the GOI. (d) EBSD image of the GOI.
3.2
Growth mechanism
Although the process steps of RMG are simple, the growth mechanism of the RMG is not as apparent as its process. Since RMG has emerged, explorations of its growth mechanism are getting started. In 2005, Liu et al. used a crystallization calculation to calculate the nucleation rate and growth velocity of the Ge in RMG[35]. These rates not only depend on sizes of the Ge, but also sensitive to the material of the insulator. Fig. 5 shows the calculational heterogeneous nucleation rate, homogeneous nucleation rate, and growth rate of a GOI at different temperatures, which were calculated by our group. The size of the GOI in the calculation is 0.2 × 2 × 50 μm3. The insulator layer is SiO2. The calculational result shows that there is a heterogeneous nucleation dominated temperature window where the homogeneous nucleation is depressed. The calculational result also shows the maximum growth velocity of the heterogeneous nucleation even more than 1 m/s, which provided the theoretical support for growth of an ultra-long GOI stripe. However, this calculation is based on a simplified mode which does not consider the nonuniformity of the concentration and temperature in the GOI stripe.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-5.jpg'" class="figure_img" id="Figure5"/>
Download
Larger image
PowerPoint slide
Figure5.
(Color online) Calculational heterogeneous nucleation rate, homogeneous nucleation rate, and growth rate of a GOI at different temperatures.
In 2010, Tanaka et al. proposed growth mechanisms based on solidification temperature and latent heat[32], which were widely accepted by many researchers. They used quartz substrates and poly Si seeds to grow GOIs by RMG and found Si–Ge mixing at the seeding region was the most important factor to trigger lateral growth. Without a Si seed, only poly-Ge grains with several μm diameter were obtained. This result also excludes an assumption that thermal flow from the liquid SiGe or Ge region to the Si substrate through the seeding window is a possible factor to be a trigger for RMG[42]. They found the growth force could be divided into two parts. In one part near the seeding region, the gradient of Si fraction induced by Si–Ge mixing creates a solidification temperature spatial gradient along the GOI stripe, which provides a driving force for lateral growth (see Fig. 6(a)). This growth mechanism was strongly supported by many subsequent experiments. Based on this principle, GOI[43], SGOI[44], and GeSn on insulator[45] were realized by self-organized seeding lateral growth. In the other part far from the seeding region, the latent heat of solidification forms a temperature gradient at the growth front of the solid–liquid interface, which provided a driving force for lateral growth of a pure Ge stripe (see Fig. 6(b)). This growth mechanism was testified by their GOI mesh growth experiment[39], where GOI mesh was demonstrated by control of the heat-flow using the optimized shape and size of the mesh. However, the growth mechanisms proposed by Tanaka et al. are mainly based on experiments, and the further theoretical mode and calculation are still missing, which needs more efforts to complete.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-6.jpg'" class="figure_img" id="Figure6"/>
Download
Larger image
PowerPoint slide
Figure6.
Growth mechanism of GOI. (a) Near seeding region. (b) Far from seeding region.
3.3
Growth orientation
As we know, carries mobility is sensitive to crystal orientation. Electron and hole mobility of Ge show the highest values in (111) and (110) orientations, respectively[46]. Future high speed MOSFETs would require a GOI with various orientations. Therefore, it is important to study and control the growth orientation of a GOI. The orientation of the GOI grown by RMG is mainly determined by orientation of seeds. Using a different substrate with different orientation to obtain the GOI with a corresponding orientation have been reported widely[29, 39, 47]. Moreover, not only can single crystal Si substrate be used for seeds, but poly-Si and even amorphous Si can also work as seeds in RMG. In these situations, orientations of the GOI become more interesting. Using poly-Si as seeds, most of the GOI stripes show (001) orientation, which agree well with that of crystal grains in the poly-Si[48]. Fig. 7(a) shows the same results which were obtained by our group. This phenomenon shows that, like single crystal seeds, orientation of crystal grains in the poly-Si also controls that of the GOI stripes. However, using amorphous Si as seeds, the initial spontaneous nucleation site near the seeding region works as a seed to guide the lateral growth of a molten Ge stripe[43]. Fig. 7(b) shows the EBSD image of the GOIs grown by amorphous Si seeds. Different single crystal GOI stripe shows different orientation and no preferential orientation is observed, for orientation of the initial spontaneous nucleation site is almost random. However, SGOI grown by self-organized seeding lateral growth shows an opposite result, which mostly shows GOI (110) orientation at the end of the stripe[44, 49]. This phenomenon is attributed to minimization of the interfacial energy between SiGe and the underlying Si3N4 films. This contradiction of the preferential orientation in the different experiments could be induced by different lengths of stripe or annealing process, which needs further experiments to make it clear.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-7.jpg'" class="figure_img" id="Figure7"/>
Download
Larger image
PowerPoint slide
Figure7.
(Color online) (a) EBSD image of the GOIs using poly-Si seed. (b) EBSD image of the GOIs using amorphous Si seeds.
Actually, the GOI grown by RMG does not always have an accurate orientation as same as that of the seed. Sometimes, the GOI stripes have a tendency to exhibit a crystal rotation along the growth direction[50]. There are mainly two reasons which are used for explaining the mechanism of the rotation. Firstly, this rotation is induced by minimizing of Ge/SiO2 interface free energy in the growth process. This explanation is supported by the following phenomenon. (1) Compared with Si (001) and Si (110) substrate, significant rotation is only observed for the GOI stripes aligned to the (112) direction on Si (111) substrate[47, 51]; (2) compared with thick Ge stripes, thinner Ge stripes are more likely to show large rotation[34]; (3) the rotation can be depressed by using thicker Ge films and narrower Ge stripes[50, 52], which reduces the width/thickness rate. However, interfacial free energy between Ge (001) and SiO2 layers is regarded as the lowest among all Ge/SiO2 interfaces, the rotation can also be observed in GOI (001) grown by Si (001) substrate[50, 53], which cannot be explained by the first explanation. Secondly, the rotation is attributed to the lattice mismatch which is induced by Si–Ge mixing. This explanation is supported by the phenomenon which intense rotation usually is observed in the forward section of the GOI stripe where it has a steep gradient of Si content[50, 53, 54]. Similar behavior was found in GeSn on insulator grown by RMG[55]. Rotation was observed in the backward section of the GeSn stripe, where has a deep gradient of Sn content. Additionally, remarkable rotation often is observed in the GOI grown by higher temperature annealing[50, 53], for the Si–Ge mixing is enhanced (see Fig. 8(a)). However, this reason cannot explain the rotation which occurred in the backward section without lattice mismatch. Moreover, our group have studied the rotation of the GOI stripes with different cooling rates and found the cooling rate was a crucial parameter to effect the rotation[53]. Fig. 8(b) shows the relationship between average cooling rate and the maximum lattice rotation along the GOI stripes. The rotation can be depressed by decreasing the cooling rate in the crystallization of the GOI stripes, which implied that the thermal stress induced by the high cooling rate is also one of the possible reasons for the rotation. Therefore, we think the rotation of the GOI is not a simple behavior driven by a single reason. It also needs comprehensive study to reveal the mechanism.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-8.jpg'" class="figure_img" id="Figure8"/>
Download
Larger image
PowerPoint slide
Figure8.
(Color online) (a) Lattice rotation along GOI stripes relative to the origin at soaking temperatures of 924, 945, 957, 967, and 977 °C. (b) Relationship between the average cooling rate in the crystallization of Ge and the maximum lattice rotation along the GOI stripes.
3.4
Concentration distribution
Characterizations such as lattice constant, band structure, and carries mobility highly depend on an alloy’s concentration. Because of intense Si–Ge mixing in the seeding region, a laterally graded Si fraction is created in the forward section of the GOI stripes. These laterally graded lattice constants are causing special interest for integration of functional materials. Therefore, Si diffusion kinetics during RMG and Si fraction distribution along the GOI stripes should be studied profoundly. However, the first study of Si fraction distribution in RMG is not from growth of GOI, but from growth of SGOI by Matsumura et al.[56]. This study was motivated by two similar experiments of SGOI growth by RMG, which exhibited different Si fraction profiles along the SiGe stripes[54, 57]. One of the Si fraction profiles has a concave shape, and another is a convex shape. To explain the difference between two experiments, Matsumura et al. investigated SiGe segregation kinetics of RMG in SiGe stripes and found the Si fraction profiles highly depend on the cooling rate and length of GOI stripes. Laterally graded SiGe profiles obeying the Scheil equation are obtained for all samples with low cooling rate and/or short lengths. For samples with high cooling rate and long length, anomalous two-step-falling profiles are obtained. Instead of the segregation coefficient by effective segregation coefficient, an improved Scheil equation is used for fitting the anomalous two-step-falling profiles.
Subsequently, Bai et al. studied the Si fraction distribution in the GOI grown by RMG[58]. The length of the Ge stripe is only 25 μm and the heating/cooling rates are controlled to be around 20 °C/s to ensure thermal equilibrium, where Si atoms and Ge atoms are uniform in the molten region. This study found that the Si fraction of the GOI in the seeding region is determined by the solidus concentration at soaking temperature and the final average Si fraction of the whole stripe is controlled by the liquidus concentration at the soaking temperature, which could be found in the Si–Ge phase diagram (Fig. 9(a)). In this study, the length of the Ge stripe is very short, so it is easier to satisfy the thermal equilibrium condition. Fig. 9(b) shows the laterally graded Si fraction profiles of the GOI stripes and the fitting curves which are calculated by the Scheil equation. The Si fraction profiles are in good agreement with its calculational curves. A similar result is also obtained in the GOI stripe with short length and low cooling rate by our group. However, in the GOI stripe with long length and high cooling rate, anomalous two-step-falling Si fraction profiles are observed, which are similar to the former SiGe experiments by Matsumura et al.[56]. These two-step-falling profiles can also be explained by the former mechanism in the growth of SGOI. Moreover, the Scheil equation is not only used for predicting the Si fraction profiles, but it is also used for the other materials in the GOI stripes, such as Sn[55, 59] and phosphorus[60], which extend the application of RMG widely.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-9.jpg'" class="figure_img" id="Figure9"/>
Download
Larger image
PowerPoint slide
Figure9.
(a) Si–Ge phase diagram. (b) Si fraction profiles and calculational curves of GOIs with different lengths. The annealing temperature is 985 °C.
3.5
Strain status
To enhance the performance of a GOI, introducing strain is a good choice. Usually, most of the GOI grown by RMG resulted in tensile strain (~0.25%), which is induced by the thermal expansion difference between Ge and Si[32, 61, 62]. This tensile strain can be increased by increasing the soaking temperature. A tensile strain as high as 0.4% was demonstrated in the GOI by Masahiro et al. using an optimized RMG process[61]. Due to the tensile strain, a direct band gap shrinkage of 45 meV and enhanced luminescence of the GOI were achieved. It is known that a Ge layer grown on a Si substrate should be compressive strain due to 4.2% lattice mismatch. It is expected the GOI grown by RMG should also be compressive strain due to continuous growth from Si. However, compressive strain in the GOI induced by lattice mismatch of Ge and Si has not been observed. Recently, our group found that with increased soaking temperature, the tensile strain of the GOI was decreased[63, 64]. Fig. 10(a) shows strain of the GOI stripes (with SiO2 micro-crucible) annealed at various temperatures. When the annealing temperature is higher than the melting point of Ge, the strain of the GOI stripe tends to stabilization. The average strain of most GOI stripes is lower than 0.03% (almost close to the bulk Ge). This phenomenon was also observed in previous works by Balakumar et al.[31]. We further studied the strain distribution of the GOI strips with/without the SiO2micro-crucible, and found the thermal tensile strain could be removed by removing the SiO2 micro-crucible of the GOI (see Fig. 10(b)). The strain free GOI is induced by the offset between thermal tensile strain and compressive strain. This compressive strain was induced by Si–Ge lattice mismatch along the GOI stripe. The reason for the different strain status (tensile strain or strain free) of the GOI observed in different groups is still unknown. It would be attributed to the different annealing condition and length of the GOI, which needs further investigation.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-10.jpg'" class="figure_img" id="Figure10"/>
Download
Larger image
PowerPoint slide
Figure10.
(Color online) (a) Strain of the GOI stripes (with SiO2 micro-crucible) annealed at various temperatures (910–990 °C/s). (b) Strain of the GOI stripes (SiO2 micro-crucible was removed) annealed at various temperatures (910–990 °C/s).
4.
Applications
4.1
MOSFETs
High performance electronic devices are one of the main applications of the GOI. Since Liu et al. firstly proposed the RMG technique, their group began to fabricate MOSFETs by using the GOI stripes[65]. The first GOI MOSFET grown by RMG has a p-channel and a top-gate structure. The effective hole mobility of the GOI MOSFET is about 120 cm2V?1s?1. Soon after that, they reported monolithic integration of GOI p-MOSFETs with Si n-MOSFETs on Si substrate[66]. CMOS inverters consisting of the Si n-MOSFET and the GOI p-MOSFET were obtained. However, both drain leakage currents and on/off rates in the GOI p-MOSFETs are not as good as those of similar devices made on bulk Ge wafer. These problems are mainly attributed to drain-body junction leakage and trapped charges in buried oxide and/or interface states, which can lead to conduction paths between source and drain. To overcome the problems, they further fabricated the GOI MOSFET by using FinFET structure[33] and gate-all-around (GAA) structure[67], respectively. The drain leakage currents were reduced significantly by the enhanced gate control. In the GAA structure, the MOSFET shows a high performance, for an on/off ratio of 3.3 × 105, effective hole peak mobility of about 220 cm2V?1s?1, and the subthreshold swing of71 mV/dec were achieved.
Moreover, other groups also reported GOI MOSFETs grown by RMG. Suzuki et al. demonstrated a high performance back-gate GOI MOSFET[68]. Unlike the MOSFETs reported by the former group, the Ge channel in the back-gate GOI MOSFET did not use an implantation or metallization process which would bring defects. A low off-leakage current of 1 × 10?7 μA/μm, a high on/off ratio of 106, and high low-field hole mobility of 480 cm2V?1s?1 were achieved. This low off leakage and high on/off were attributed to Ge/Si hetero-junctions in the source and drain. Until now, this is the highest record of the GOI MOSFETs grown by RMG. Our group also fabricated GOI MOSFETs with a back-gate. The insulator layer is 63 nm-thick Si3N4 which worked as a gate dielectric. Width, length, and thickness of the GOI channel are 2, 20, and 80 nm, respectively. The ID–VD characteristics, the ID–VG characteristics, and schematic structure of the device are shown in Fig. 11. The device exhibited a very good p-type FET operation with a holes inversion mode. The linear, nonlinear, and saturation regions can be observed clearly. A good switching performance is obtained with an on/off current ratio about 103. The off-leakage current is about 10?4 μA/μm. The peak hole mobility of the MOSFET is about 400 cm2V?1s?1.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/6/PIC/17100021-11.jpg'" class="figure_img" id="Figure11"/>
Download
Larger image
PowerPoint slide
Figure11.
(Color online) (a) ID–VD characteristics of the device at gate bias ranging from ?2 to ?10 V in ?1 V step. (b) ID–VG characteristics of the device with drain bias ranging from ?0.02 to ?0.2 V in ?0.02 V step. The inset is the schematic of the back-gate MOSFET.
4.2
Photodetectors
GOI grown by RMG also is a potential structure in fabricating photodetectors. In 2004, the first GOI photodetector grown by RMG was reported by Liu et al. as well[65]. The GOI photodetector consisted of an array of five parallel p-i-n diodes with 1 μm width and 5 μm intrinsic length. A photodetector responsivity value exceeding 160 mA/W at 850 nm and full width half maximum (FWHM) impulse response less than l00 ps were demonstrated. GOI grown by RMG also has the ability to integrate with other structure. Tang et al. fabricated a nanometer-scale near-infrared GOI photodetector by RMG with a half-wave Hertz dipole antenna to concentrate the radiation[69]. This structure gives a polarization contrast of a factor of 20 in the resulting photocurrent in the subwavelength GOI photodetector, which has an active volume of only 720 nm3.
Soon after that, Assefa et al. demonstrated CMOS integrated high-speed MSM GOI waveguide photodetectors[70]. Although the original photodetector can operate at 40 Gbps, the light responsivity was less than satisfactory. After optimizing the size of Si and GOI waveguide to increase light coupling, relative high light responsivities of 0.41 and 0.14 A/W for 1.31 and 1.5 μm wavelength were achieved in latter photodetectors[71]. Interestingly, their MSM GOI waveguide photodetector can also work as an avalanche photodetector (APD) by reducing the spacing between finger electrodes[72]. Amplification noise was reduced by 70% due to nanophotonic and nanoelectronic engineered nanometer scale optical and strongly non-uniform electrical fields within the Ge amplification layer. The APDs with an avalanche gain of over 10 dB and 3-dB bandwidth over 30 GHz were achieved at a bias voltage of only 1.5 V.
The quality of the Ge stripe grown by RMG is much better than that of Ge films directly grown on Si substrate. Therefore, high quality self-aligned microbonded Ge on Si could be realized by removing the SiO2 micro-crucible of the GOI. Tseng et al. fabricated Ge/Si PIN waveguide photodete- ctors[73, 74] and metal-semiconductor-metal photodetectors by using this self-aligned microbonded Ge on Si[75]. In spite of the high crystal quality, microbonded Ge on Si also suffers from interface problems. The dark currents of these photodetectors are mainly attributed to the trap states localized near the Si/Ge interfacial layer, which are comparable to those of the conventional Ge/Si waveguide photodetectors. However, a high bandwidth of 17 GHz and a responsivity of 0.7 A/W at the reverse bias of ?6 V are achieved.
5.
Summary and outlook
In summary, RMG is a novel technique to fabricate GOI, which has been proposed for a decade. In this paper, we have introduced the RMG technique and presented a thorough review of recent efforts and progress on the RMG including fundamental researches and device applications. The growth dimension, width, length, thickness, and their limitations of the GOI were discussed. Several structures such as array, mesh, and vertically multiply stack which were used for increasing the integrated density were reviewed. For the growth mechanism, two main reasons including Si–Ge mixing and latent heat were discussed. For growth orientation, the orientation control and the crystal rotation were reviewed, and possible reasons for the rotation including Ge/SiO2 interface free energy and lattice mismatch were discussed. For concentration distribution, the different Si fraction profiles induced by different annealing processes were discussed. The Scheil equation was introduced for predicting the Si fraction profiles. For strain status, the thermal tensile strain and the compressive strain due to lattice mismatch was discussed. These results show the GOI grown by RMG is a promising material for the next-generation of integrated circuits. The GOI waveguide photodetectors with high responsivity and high speed are reviewed, which indicates GOI grown by RMG is also a potential structure in fabricating optoelectronic circuits. However, the subsequent works for the RMG research would focus on the Ge/insulator interface problem, which deteriorates the performance of the GOI devices. Moreover, RMG is a powerful technique which not only can be used for fabricating group IV materials on insulators such as GOI, SGOI, and GSOI, but can be used for growing group III–V materials on insulators as well. Primary experiments of GaAs and GaSb on insulators grown by RMG on Si substrate have been reported, which provide a new approach to integrate group III–V materials and group IV materials on Si. We believe that in future, more and more materials, devices, and applications would be realized by RMG.
