1.School of Physics and Information Engineering, Shanxi Normal University, Linfen 041004, China 2.Key laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China 3.Shaanxi Province Key Laboratory of Thin Films Technology & Optical Test, Xi’an Technological University, Xi’an 710032, China
Fund Project:Project supported by the National Natural Science Foundation of China (Grant No. 62004119) and the Applied Basic Research Plan of Shanxi Province, China (Grant No. 201901D211400).
Received Date:15 June 2021
Accepted Date:18 July 2021
Available Online:17 August 2021
Published Online:05 November 2021
Abstract:The nanowire gate-all-around (GAA) structures with the nearly ultimate channel electrostatic integrity of the gate field can exhibit the best immunity to the short channel effect and drain-induced barrier lowering. Moreover, owing to the enhanced control efficiency of gate over the tunneling junction, the GAA-TFET also gives improved subthreshold swing and on-state current. Despite the excellent device performance, an accurate model is very significant for the practical application. Compared with the numerical methods which are usually time consuming and computationally inefficient, an analytical model could accelerate the device investigation and circuit design process. Even though some tunneling current models have already been reported for nanowire tunneling field-effect-transistors (TFETs), the model of the terminal capacitance is still an issue for nanowire TFETs. The capacitance is of great significance for the transient simulation. In this paper, a physical and analytical potential model considering both the source depletion region and the channel mobile charges, is developed for the GAA-TFETs. The results from the model are verified with the numerical simulations, and the excellent agreement between the two results indicates the validation of the proposed model. Based on the potential model, the terminal charge model and the capacitance model are further developed and also verified by the numerical simulations. The main inflection and variation of the terminal charges and capacitances with the biases can be predicted by our model. Besides, both the model results and the numerical simulations both demonstrate that the gate charge is dominated mainly by the drain charges and the contribution of the source charges can be almost neglected. This also leads to the very small gate-source capacitance and very large Miller capacitance in the TFET device. This will be detrimental to the performance of TFET-based digital circuits but can be mitigated with the hetero-oxide gate structure. The second order effects, such as the quantum confinement and traps, are ignored in this paper and can be taken into the core model in the future work. It should also be noted that there is no iterative process involved during the model derivation, thus the developed model can be easily applied to the widely used SPICE platform and will be useful in designing and investigating the GAA-TFET based circuits. Keywords:tunneling field-effect-transistor/ band-to-band tunneling/ nanowire/ capacitance model
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2.1.电势模型
图1(a)为一个n型GAA-TFET的三维结构示意图, 其中纳米线的半径R = 7.5 nm, 采用HfO2作为栅氧化层, 介电常数εox = 22, 厚度为Tox = 2 nm, 栅金属功函数为4.2 eV. 图1(b)是GAA-TFET沿纳米线直径方向的剖面图, 本文主要关注器件核心物理机理的分析, 在模型推导过程中, 暂不考虑短沟道效应等二次非理想效应的影响, 因此器件栅长设置相对较长, 为Lg = 50 nm[7]. 源区、沟道和漏区的掺杂浓度分别为NS = 1 × 1020 cm–3(P型), NC = 1 × 1015 cm–3 (N型) 和ND = 5 × 1019 cm–3 (N型). 器件剖面图可划分为3个区域, 分别为源耗尽区I区、沟道耗尽区II区以及沟道积累区III区, 其中I区和II区的宽度分别为LI和LII. 图 1 (a) GAA-TFET的三维结构示意图; (b) GAA-TFET沿沟道方向的剖面示意图; (c) GAA-TFET垂直于沟道方向的剖面示意图 Figure1. (a) Three-dimensional structure of GAA TFETs. Schematic cross section of an n-type GAA TFET (b) along the channel and (b) normal to the channel direction.