1.Key Laboratory of Advanced Transducers and Intelligent Control System of Ministry of Education, Taiyuan University of Technology, Taiyuan 030024, China 2.College of Physics and Optoelectronics, Taiyuan University of Technology, Taiyuan 030024, China 3.Guangdong Provincial Key Laboratory of Photonics Information Technology, Guangzhou 510006, China 4.School of Information Engineering, Guangdong University of Technology, Guangzhou 510006, China
Fund Project:Project supported by the National Natural Science Foundation of China (Grant Nos. 61731014, 61671316), the Natural Science Foundation of Shaanxi Province, China (Grant No. 201801D121145), and the Shanxi Scholarship Council of China (Grant No. 2017-key-2)
Received Date:03 August 2020
Accepted Date:02 September 2020
Available Online:23 February 2021
Published Online:05 March 2021
Abstract:Boolean networks (BNs) are nonlinear systems and each BN has a simple structure, thus it is easy to construct large networks. The BNs are becoming increasingly important as they have been widely used in many fields like random number generation, gene regulation, and reservoir computing. In recent years, autonomous Boolean networks (ABNs) have been proposed and realized by actual digital logic circuit. The BNs each have a clock or selection device to determine the update time of each node. Unlike BNs, ABNs have no device to control the update mechanism, and the update of each node is determined by response characteristics of the logic gate that make up the node, which leads to continuous and complicated outputs. Time series with different complexities including periodic and chaotic sequences can be generated by the ABNs, which is very meaningful in different applications.Research on the regulation of ABNs’ output is of big significance. Non-ideal response characteristics of the logic gates and time delay on the link are two major factors which can regulate the output state. Many studies focus on time delay on the link and indicate that the large delay inconsistency leads to complex outputs.In this paper, in order to study the regulation of ABNs’ output, it is demonstrated that the response characteristics of the logic gate can be continuously adjusted by the parameters in the ABNs’ equations. Then the effects of logic gates’ response characteristics on ABNs’ outputs are studied by simulation. The simulation results indicate that the ABNs’ outputs can transform between periodic and chaotic state with the change of logic gates’ response characteristics. Moreover, the interrelationship between logic gates’ response characteristics and propagation delays along the links is reinvestigated. The results show that the high complexity series space is extended by the fast logic gates’ response characteristics. Also the effects of different logic gates’ response characteristics on the ABNs’ output are compared, and the results indicate that node 2 has a good performance on the regulation of ABNs’ output while node 1 and node 3 show small effect on the ABNs’ output.It is concluded that the complexity of the ABNs’ output can be regulated by the logic gates’ response characteristics, and the high complexity series’ generation can be promoted by the fast logic gates’ response characteristics. This conclusion is conducive to the logic gates’ selection in random number generation, gene regulation, reservoir computing and other applications. Keywords:autonomous Boolean network/ chaos/ logic gates’ response characteristics/ permutation entropy
全文HTML
--> --> --> -->
2.1.单节点异或非逻辑门模型
图1为异或非逻辑门示意图, u1, u2为输入信号, yout为输出信号. 实际逻辑器件中, 异或非逻辑门无法对输入信号做瞬时响应, 当输入信号u1, u2维持时间较短时, 异或非逻辑门将不能完全响应, yout不能产生对应的输出波形, 本文称这一特性为逻辑器件响应特性, 在本文的研究中, 对任一给定的信号维持时间为?tu的输入信号, 输出信号脉冲幅值和脉冲宽度的不同表征了器件响应特性的不同, 输出信号幅值越大、脉冲宽度越宽表明器件响应越快, 能响应更窄的输入信号. 图 1 异或非逻辑门示意图 Figure1. The schematic illustration of the XNOR logic gate.
${\tau _{{\rm{lp}}}}\frac{{{\rm{d}}{y_{{\rm{out}}}}\left( t \right)}}{{{\rm{d}}t}} = - {y_{{\rm{out}}}}\left( t \right) + {U_1}\left( t \right) \odot {U_2}\left( t \right), $
为了更详细直观地观察输出波形随器件响应特性的变化规律, 选取5个输入信号, 如图4(a)所示, u2完全相同均为低电平0 V, u1, j表示u1的j种不同波形, 其低电平0 V保持时间分别为0.1, 0.2, 0.3, 0.4, 0.5 ns. 观察τlp从0.01 ns增大至5.00 ns时输出脉冲的幅值ymax和宽度?tY的变化, τlp调节步进为0.05 ns. 如图4(b)所示为ymax随τlp的变化曲线, 曲线有明显凹点, 凹点之前ymax随着τlp的变大迅速减小, 且减小的速度越来越快, 凹点之后减小的速度降低曲线趋于平缓. 图4(c)为?tY随着τlp的变化曲线, 可以看出, 对于同一个输入信号随着参数τlp的增大响应脉冲宽度?tY逐渐减小, 最终降为0 ns, 表明此时逻辑器件不能输出正确的响应(此例中为高电平). 仿真结果表明模型参数τlp能够对逻辑器件的响应特性进行连续调节, 因此本文中将参数τlp称为器件响应特性参数, 下文中通过调节τlp研究逻辑器件响应特性对自治布尔网络输出的影响. 图 4 异或非逻辑门输出脉冲幅值和宽度随τlp变化曲线 (a) 输入波形图; (b) 输出脉冲幅值ymax随τlp变化曲线; (c) 输出脉冲宽度?tY随τlp变化曲线 Figure4. Output pulse amplitude and width as a function of τlp : (a) Input waveform; (b) output pulse amplitude as a function of τlp; (c) output pulse width as a function of τlp.