1.School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, China 2.School of Electronics Engineering and Computer Science, Peking University, Beijing 100871, China 3.Nanjing CEC Panda FPD Technology Co., Ltd., Nanjing 210033, China
Abstract:There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiNx/SiO2 insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiNx/SiO2. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (Vth) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(W/L) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiNx/SiO2 leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiNx film and SiO2 film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure. Keywords:Cu interconnect/ electrostatic-discharge/ InGaZnO thin film transistor/ gate driver on array
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2.1.GOA电路
本研究的IGZO TFT背板的各层薄膜自玻璃基板起依次是Mo/Cu栅极层、SiNx/SiO2栅极绝缘层、IGZO有源层、Mo/Cu源漏极层、SiO2/SiNx保护层. 扫描线左右两侧的GOA驱动电路采用由13个IGZO TFT和1个电容构成的13T1C架构(图1). 该架构在4T1C架构基础上增加了GOA电路信赖性提升单元和辅助帧电荷清除单元, 其输入信号有: 初始置位信号GSP、时钟信号CLK1-CLK8、清空信号CLR和关态低电位VSS. 采用8根CLK可以降低时钟信号线的负载, 满足对上升时间的要求, 在降低功耗的同时提升显示区像素的充电能力[15]. 设计55寸UHD面板像素时, 保证数据线信号和扫描线脉冲信号的交叠时间控制在2 μs以内, 输出使能(output enable, OE)时间为1.8 μs, 以防止错误的数据线信号充入像素. 图 1 13T1C架构的GOA电路单元原理图 Figure1. Diagram of the GOA circuit unit composed of 13 TFTs and 1 capacitor.