1.
Introduction
Although the charge coupled device (CCD) image sensors have been widely used during the past several decades, complementary metal oxide semiconductor (CMOS) image sensor (CIS) have brought a huge popularity to various imaging applications due to the advantages over CCD image sensor such as system on chip (SOC), low power consumption, and lower cost. The dynamic range and signal-to-noise ratio are two key parameters which determine the performance of an image sensor. In these characteristics, it is obvious to one that the noise parameter is the key technology because the dynamic range is the result of full swing range over the readout noise and the signal-to-noise ratio is the results of signal power over the noise power[1].
To reduce the temporal noise, high gain column amplifier is adopted in the first stage of the column readout chain[2], which is helpful to the low light level, but it will restrict the input light range for the high light level. So, the entire range of light level is not considered in the high gain technology at the same time. An effective approach is to optimize the individual noise of all modules. Offset FPN, low frequency noise and reset noise of pixel can be suppressed through the correlation of reset voltage and integrated signal voltage, which is called correlated double sampling (CDS)[3]. In recent years, high column level gain and correlated multiple sampling (CMS) were implemented to further reduce the input referred temporal noise[4, 5]. Both fixed pattern noise (FPN) and temporal noises are suppressed by the proposed digital correlated multiple sampling (DCMS) technology in Ref. [6]. From the previous reported work, we can see that the temporal noise and the spatial noise are considered and researched through the system. It is realized by sacrificing the swing range and dynamic range. The thoroughgoing approach should be the practical circuit level solution which optimizing the components parameters and the non-ideal effect[7]. So, we are devoted to give the module level solution to reduce the practical level circuit noise. Offset mismatch and charge sharing between the column amplifier and the column buffer are two outstanding problems existed in the column readout circuit. Unfortunately, because the charge sharing is inseparably linked with the charge injection, the image signal is nonlinear. In this paper, simple column readout circuits with improved offset mismatch and charge sharing for CMOS image sensor is proposed. The linear range and the readout noise are improved in a 1024 × 1024 CMOS image sensor chip designed and fabricated in the 55 nm low power CMOS process. The detail description and discussion are organized as following sections.
2.
Traditional column readout designs
Several CMOS image sensor architectures have been reported according to the types of the signal readout schemes and the position of the analog to digital processing. A typical readout circuit of CMOS image sensor with a noise canceller for fixed pattern noise and reset noise of pixels is shown in Fig. 1. By controlling the timing sequence of switches S1 and S2, the reset level and signal level of the amplified pixel output are sampled on the capacitor C1 and C2 respectively[8]. The equivalent input parasitic capacitor of column buffer 1 and column buffer 2 are Cpar1 and Cpar2. Because this parasitic capacitor and storage capacitor are parallel to the column amplifier, it can’t induce the nonlinearity of the signal level, except for increasing driving current and settling time. The intrinsic offset due to the mismatch between the column buffer 1 and column buffer 2 is a critical problem. Even though both column buffers use the same circuit, the offset also can’t be eliminated by CDS, because the actual signal output can be expressed by Eq. (1), where VR is the reset level from pixel output, VS is the image level from pixel output, VOS1 is the offset voltage of the buffer 1, and VOS2 is the offset voltage of the buffer 2.
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Figure1.
Column readout with two buffers.
${V_{ m{OUT}}} = ({V_{ m{R}}} + {V_{ m{OS1}}}) - ({V_{ m{S}}} + {V_{ m{OS2}}}) = ({V_{ m{R}}} - {V_{ m{S}}}) + ({V_{ m{OS1}}} - {V_{ m{OS2}}}).$  | (1) |
Therefore, a serial output through single column buffer was designed to overcome the offset, as shown in Fig. 2[9]. Its sample phase is the same as shown in Fig. 1, but the output phase is different because the reset level on capacitor C1 is transmitted through the switch S3 and column buffer, the image level on capacitor C2 is transmitted through the switch S4 and column buffer. However, due to the parasitic capacitor Cpar in column buffer input, the respective charge sharing during the reset level and image level output phase will produce high noise and nonuniformity. Furthermore, the final balance level is decided not only by the ratio of the storage capacitor and the parasitic capacitor, but also by the initial or the final state. It can be expressed by the following equations:
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Figure2.
Column readout with single buffer.
${C_1}{V_{ m{R}}} + {C_{{ m{par}}}}{V_{left( {L1} ight)}} = ({C_1} + {C_{{ m{par}}}}){V_{{ m{R}}left( { m{F}} ight)}},$  | (2) |
${C_2}{V_{ m{S}}} + {C_{{ m{par}}}}{V_{left( {L2} ight)}} = ({C_2} + {C_{{ m{par}}}}){V_{{ m{S}}left( { m{F}} ight)}},$  | (3) |
where V(L1) is the last stage level on the column buffer input Cpar before switch S3 turns on, V(L2) is the last stage level on the column buffer input Cpar before switch S4 turns on. So, V(L1) has an approximate storage value of reset level, V(L2) has an approximate storage value of image level during the last row readout. Although there is a correlation between each adjacent row, but for the low noise demanding, the difference will induce enough performance deteriorating owing to the discharge and fixed pattern noise.
3.
Proposed column readout structures
Based on the analysis of traditional column solution, a low noise column readout circuit with improved charge sharing for CMOS image sensor is proposed in this paper, as shown in Fig. 3(a), and the control timing is shown in Fig. 3(b). The presented approach is composed by the column amplifier, reset level storage capacitor C1, image level storage capacitor C2, a single column buffer and eight switches. In the sample phase, firstly the switch S1 which connect the column amplifier and both plates of capacitor C1 is on, the reset level from pixel column line can be sampled on the capacitor C1, as shown in Fig. 4(a). Then the switch S2 which connect the column amplifier and both plates of capacitor C2 is on, the image level from pixel column line can be sampled on the capacitor C2, as shown in Fig. 4(b). In the buffer phase, firstly the switch S3 which connect both plates of capacitor C1 and the column buffer is on, the reset level sampled on the capacitor C1 can be buffered out to the next stage, as shown in Fig. 4(c). Secondly the switch S4 which connect both plates of capacitor C2 and the column buffer is on, the image level sampled on the capacitor C2 can be buffered out to the next stage, as shown in Fig. 4(d). Since the input operating point is unchanged, it can be seen that this method not only adopts a single column buffer to eliminate the offset, but also improves the charge sharing by the bottom plate sampling.
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Figure3.
(a) Proposed column readout. (b) Control timing of the proposed circuit.
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Figure4.
(a) Reset level sample phase. (b) Image level sample phase. (c) Reset level buffer phase. (d) Image level buffer phase.
A large array CMOS image sensor is composed by a great number of column readout circuits. Generally, the sample phase is parallel at same time in a row pixel, and the buffer phase is consecutive to transmit from column 1 to column n. n column readout circuit adopted proposed approach is designed in Fig. 5, where each column readout has two input ports, one is the pixel output, and another is the common voltage VCM, which is shared to all columns, but with enough driving capability, where the maximum load capacity we designed is 10 mA. The detail control timing is shown in Fig. 6.
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Figure5.
n columns readout schematic.
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Figure6.
Control timing of n columns readout.
4.
Measurement results
The low noise column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is implemented in 55 nm CMOS image sensor technology. The die micrograph of the fabricated sensor is shown in Fig. 7, which consists of a 1024 × 1024 pixel array and peripheral circuitry. The column parallel readout circuit is located on a single side below the pixel array. In order to measure the performance of the proposed approach how it improve the offset mismatch and charge sharing, the output gray code variances with exposure time and rms value is measured for all pixels by using a 14 bit ADC. Based on EMVA 1288 presented by European Machine Vision Association, a full set of parameters measurement procedures were done on the test image sensor.
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Figure7.
(Color online) Die micrograph.
Fig. 8 shows a comparative curve with and without the proposed technique applied to the readout circuit under bright and dark conditions. In contrast to conventional architectures, the proposed architecture achieves an excellent linearity output code versus exposure time, which can be increased by 20%. As we can see that the traditional solution dramatically decreased the linearity under bright field and the nonuniformity under dark field, which will deteriorate the image quality during low light to high light application. Furthermore, Fig. 8 shows the measurement results of the nonuniformity with conventional and proposed approach under bright and dark conditions. The proposed architecture can get optimization uniformity lower than ten digital codes, but the conventional method shows a worse noise and growth rate. As is shown, the photo response nonuniformity is reduced by 40% and 30% in bright and dark field. Because the parasitic capacitor can’t be matched in the readout chain, the proposed approach without parasitic influence will provide an excellent uniformity. It is verified significantly by the prototype sensor chip, and the statistics results show a better PRNU less than 1.16%. Finally, the comparison of actual image before and after the optimization is shown in Fig. 9. In order to improve the recognition, we extracted part of the image, where the resolution of the pixels shown in the picture is about 10 × 10, and performance summary and comparison with the state of the art are given in Table 1.
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Figure8.
Output code and nonuniformity versus exposure time.
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Figure9.
Comparison of actual images before and after optimization. (a) Image with traditional technique. (b) Image with proposed technique.
| Parameter | This work | Ref. [7] | Ref. [10] |
| Process | 55 nm CMOS | 40 nm CMOS | 180 nm CMOS |
| Pixel size (μm) | 5.4 | 5.4 | 2.8 |
| Supply (V) | 3.3/1.2 | 2.5/2/1.1 | 3.3/1.8 |
| Horizontal time (μs) | 5 | 6.02 | 1.92 |
| Column FPN (%) | 0.0075 | 0.028 | 0.31 |
| Read noise (μVrms) | 190 | 261.5 | 320 |
| Dynamic range (intrinsic) (dB) | 75 | 71.8 | 62.9 |
| Photo response nonuniformity | 1.16% | N/A | N/A |
Table1.
Performance summary and comparison with the state of the art.
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| Parameter | This work | Ref. [7] | Ref. [10] |
| Process | 55 nm CMOS | 40 nm CMOS | 180 nm CMOS |
| Pixel size (μm) | 5.4 | 5.4 | 2.8 |
| Supply (V) | 3.3/1.2 | 2.5/2/1.1 | 3.3/1.8 |
| Horizontal time (μs) | 5 | 6.02 | 1.92 |
| Column FPN (%) | 0.0075 | 0.028 | 0.31 |
| Read noise (μVrms) | 190 | 261.5 | 320 |
| Dynamic range (intrinsic) (dB) | 75 | 71.8 | 62.9 |
| Photo response nonuniformity | 1.16% | N/A | N/A |
5.
Conclusions
With the pixel array resolution increasing, the column parallel readout topology is facing the challenges in high speed, high accuracy and low noise application. The reset level and the image level of the storage capacitor are sampled by the correlated double sampling technology in the traditional method. However, the offset mismatch which is introduced in the two buffers is not certain related to the luminance of light, and it can’t be cancelled by the CDS because of the intrinsic unbalanced structure and the electrical properties. Due to the difference between the sequential rows, the charge sharing exists in the image level point evidently, and it also exists in the reset level point which is induced by fixed pattern noise. However, the charge sharing which exists in the single buffer structure can result in the charge exchange between the reset level and image level which is critical to the readout noise. Therefore, column readout circuit with improved offset mismatch and charge sharing using a single buffer with eight switches is proposed in this paper. The key technology presented in our design not only avoids the charge sharing through the extra switches, but also keeps the constant operating point, which is favorable to the low noise design. A 1024 × 1024 pixels CMOS image sensor including 1024 columns readout has been fabricated in a 55 nm 1P4M CMOS with pinned photodiode process. The measurement results show that the linear range is extended by 20%, the readout noise is reduced by 40% and 30% in bright and dark field, and the photo response nonuniformity is up to 1.16%. Finally, a raw sample image taken by the prototype sensor shows the excellent practical performance.
Acknowledgments
This work was supported by Shaanxi Education Department (No. 19JC029).
