Analysis and performance exploration of high performance (HfO<sub>2</sub>) SOI FinFETs o

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1.
Introduction

Today, human life in all practical aspects is affected by electronic industries, and low power and high-performance portable devices have become the major requirement in commercial applications. Increasing demand for such products encourages the researchers to design a semiconductor device at sub 20 nm technology nodes. At each technology node researchers are trying to reduce the transistor size to obtain the better performance and portability of consumer products^[1]. But, in CMOS technology, the continued scaling of the physical size of the transistor may couple the source-drain region, which reduces the gate electrode control over the potential distribution and flow of current in the channel, and generates undesirable side effects, called SCEs (short channel effects)^{[2, 3]}. So, as technology is scaling down and moving into the nanometer regime, the performance of devices degrades in terms of SCEs. Now, classical bulk MOSFET structure has reached its scaling limits and it seems impossible to further shrink the dimension of the MOS transistor below 20 nm. So, there have been revolutionary changes occurring in the semiconductor device structures to get fast, reliable, and low power performance^{[4, 5]}. FinFET has emerged as a desirable candidate to fulfill this requirement due to its 3-D geometry^[6–8]. FinFET has both DG (double gate) and TG (triple gate) architecture and is fabricated on SOI (silicon on insulator) substrates. FinFET is a more suitable structure for CMOS (complementary metal oxide semiconductor) technology because of its easy fabrication steps, quasi-planar structure^{[9, 10]}, excellent scalability, improved SCEs, and is very close to MOSFET in respect to layout. Therefore, major semiconductor leading companies like TSMC and Intel designed the FinFET at 22 nm technology node for mobile and high-performance computing platforms and others are further trying to enhance the SCEs of SOI FinFET structure by gate-source/drain high-k spacer region optimization and source/drain extension engineering techniques near 16/14 nm future technology nodes^{[11, 12]}. However, the tradeoff always occurs among SCEs, analog and RF performance parameters of SOI FinFET structure.

A lot of advanced semiconductor device structures are proposed by many researchers like pi-gate^[13], ohm-gate^[5], tri-gate, planar double gate SOI MOSFETs, Bulk FinFETs, SOI FinFETs and all around gate^{[14, 15–18]} etc. ITRS (International Technology Road Map for Semiconductors)^[19] considered the FinFET a suitable structure in CMOS circuits due to low power consumption and a higher level of integration with an optimized level of SCEs. The FinFET device does not exist in discrete form. So, it requires the simulation study to evaluate the analog/RF performance characteristics at the circuit perspective view.

In this paper, 3-D simulation of SOI FinFETs of different flavors is carried out to explore the analog/ RF figures of merit at 20 nm technology node. The effect of spacers (HfO₂ and Si₃N₄) and source/drain extension regions of SOI FinFET has been investigated with the help of 3-D simulation results. This paper starts with Section 1 which is the introduction part, and Section 2 explores the device structures of D1, D2, and D3 along with its dimensions, doping concentration, models, and spacers materials considered for the simulation process. Section 3 describes the two subsections that include the electrostatic performance characteristics matrices along with SCEs like SS, DIBL (drain induced barrier lowering), and various analog/RF matrices like A_V, g_d, g_m, TGF = g_m/I_d, V_EA, GFP, TFP, GTFP, and f_T for device-D1, device-D2, and device-D3. Finally, Section 4 describes the conclusion part of the paper.

2.
SOI FinFET device structures and models used for simulation

Schematic diagrams of device-D1, device-D2, and device-D3 are shown in Figs. 1(a), 1(b), and 1(c) respectively. In all three symmetrical SOI FinFET structures, the 20 nm channel length is considered for 3-D simulations. Source/drain of all structures is heavily doped as n-type 1 × 10²⁰ cm^?3 and channels of all structures are lightly doped as p-type 1 × 10¹⁵ cm^?3. Source/drain is heavily doped to overcome the effect of mobility degradation, which is generated due to Coulomb scattering effects. Here the total effective width of the transistor is considered because of the total current of all FinFET structures is the effect of all current components flowing through sidewalls and the top surface of Fin^[20]. The structural parameters of all SOI FinFET devices used for 3D simulation in this paper are given in Table 1.

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Figure1.
(Color?online) (a) Device-D1 (conventional Si₃N₄ spacer SOI FinFET). (b) Device-D2 (conventional HfO₂ SOI FinFET). (c) Device-D3 (source/drain extended HfO₂ spacer SOI FinFET).

Parameter	Description	Device-D1	Device-D2	Device-D3
W_Fin	Fin width	10	10	10
H_Fin	Fin height	26	26	26
L_g	Gate channel length	20	20	20
t_ox	Oxide thickness	0.9	0.9	0.9
BOX	Thickness of the buried oxide	40	40	40
W	Effective width of transistor	62	62	62
L	The total length of the device	110	110	110
L_lk	Spacer length (Si₃N₄, k = 7.5)	5	–	–
L_hk	Spacer length (HfO₂, k = 22)	–	5	5
W_s/d	Source/drain width	10	10	40

Table1.
Dimensional values used for simulation in this paper (unit: nm).

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Parameter	Description	Device-D1	Device-D2	Device-D3
W_Fin	Fin width	10	10	10
H_Fin	Fin height	26	26	26
L_g	Gate channel length	20	20	20
t_ox	Oxide thickness	0.9	0.9	0.9
BOX	Thickness of the buried oxide	40	40	40
W	Effective width of transistor	62	62	62
L	The total length of the device	110	110	110
L_lk	Spacer length (Si₃N₄, k = 7.5)	5	–	–
L_hk	Spacer length (HfO₂, k = 22)	–	5	5
W_s/d	Source/drain width	10	10	40

The 3-D simulation is carried out using Sentaurus TCAD simulator^[21] for the same effective width of all SOI FinFET structures and V_th (threshold voltage) of all devices is set to 0.2 V at the fixed value 0.7 V of V_DS (drain-source voltage) by optimizing the Φ_m (gate metal work function). All electrical and physical parameters are calibrated to meet the ITRS requirements below 22 nm channel length^{[7, 22–26]}. The equivalent oxide thickness is taken as a value of 0.9 nm with the supply voltage V_DD of 0.7 V.

The model considered in this paper is the velocity saturation model, concentration-dependent and field dependent models of mobility^[27]. The inversion mobility Lombardi CVT^[28] and model of Auger recombination with Shockley–Read–Hall (SRH)^{[29, 30]} is also effectively used in the simulation process. For numerical simulations, the drift-diffusion method is used. A set of differential equations: Poisson, continuity, energy, and thermal equations, are also used for simulations^[21]. Junctions with smooth meshing and biasing are done at room temperature. The analog/ RF performance is evaluated for high (V_DS = 0.7 V) and low (V_DS = 0.05 V) values of drain-source voltages.

3.
Results and discussion

SCEs performance evaluation of all SOI FinFET devices D1, D2, and D3 is done with the help of SS and DIBL parameters in the nanometer regime. DIBL is the measure of the controlling of the semiconductor device against threshold voltage reduction, and SS is responsible for a measure of ‘OFF’ characteristics of the semiconductor device. These two parameters are calculated for D1, D2, and D3 devices according to Ref. [31] and mentioned in Table 2. Electrostatic parameters summaries in Table 2 are evaluated for the values of V_DS = 0.7 V and V_DS = 0.05 V for all SOI FinFET structures. From evaluated results, we conclude that as moving from Si₃N₄ spacer device-D1 to HfO₂ spacer devices D2 and D3, SS and I_on values improve with compromising in I_off current. Device-D1 has better immunity to SCEs due to the low value of DIBL as compared to devices D2 and D3 while devices D3 and D2 have a higher value of I_on current as compared to device D1 which plays the key role in analog circuit design.

Device	SS (mV/decade)		I_on (μA)		I_off (nA)		DIBL (mV/V)
Device	V_DS = 0.7 V	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.05 V	DIBL (mV/V)
D1	71.56	67.69	61.0	33.0	12.5	5.65	30.37
D2	68.93	66.17	89.0	46.6	25.3	13.9	70.76
D3	68.89	66.41	100	57.7	58.6	30.5	81.53

Table2.
Electrostatic SCEs parameters.

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Device	SS (mV/decade)		I_on (μA)		I_off (nA)		DIBL (mV/V)
Device	V_DS = 0.7 V	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.05 V	DIBL (mV/V)
D1	71.56	67.69	61.0	33.0	12.5	5.65	30.37
D2	68.93	66.17	89.0	46.6	25.3	13.9	70.76
D3	68.89	66.41	100	57.7	58.6	30.5	81.53

I_D (drain current) versus V_GS (gate-source voltage) characteristics for D1, D2, and D3 devices both in the log and linear scales are plotted in Figs. 2(a) and 2(b) and gives the effective drain current for the values of V_DS = 0.05 V and V_DS = 0.7 V respectively. It is observed from the I_D–V_GS characteristics in Fig. 2 that due to the HfO₂ (k = 22) spacer region, I_D increases significantly and device D3 has a large value of I_D as compared to devices D1 and D2 due to its extended value of source/drain regions, which significantly reduces the effective value of source/drain resistance. Extended source/drain structure of SOI FinFET is beneficial for multi-fin structure designing for enhancing the further driving capability and reliability of FinFET for analog circuit applications.

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Figure2.
(Color?online) I_D–V_GS characteristics for devices D1, D2, and D3 in log and linear scales for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

3.1
Analog performance evaluation

The main figures of merit like g_d, g_m, V_EA, TGF, and A_V are explored for all SOI FinFET devices D1, D2, and D3 for evaluating the analog performance. A plot of TGF and g_m versus V_GS voltage for devices D1, D2, and D3 are shown in Fig. 3. The g_m parameter of the semiconductor device is an important parameter which affects the gain of the amplifier and is calculated according to Eq. (1). TGF signifies the effective uses of device current to get the desired value of g_m. The high TGF means the effective realization of analog circuits and operated with a low value of supply voltage. TGF is calculated according to Eq. (2).

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Figure3.
(Color?online) Trans-conductance (g_m) and trans-conductance generation factor (TGF) against V_GS characteristics for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

$ {g_ {
m{m}}} = frac{{partial {I_ {
m{D}}}}}{{partial {V_ {
m{GS}}}}} ,$

(1)

$ {
m TGF} = frac{{{g_ {
m{m}}}}}{{{I_ {
m{D}}}}} .$

(2)

The analog performance parameters for considering the same V_th voltage evaluated at a fixed value of V_DS = 0.05 V and V_DS = 0.7 V for SOI FinFET devices D1, D2, and D3 are shown in Table 3. The high value of trans-conductance (g_m) and improved value of early voltage (V_EA) are generated for SOI FinFET devices D2 and D3 as compared to device D1 at low and high values of V_DS = 0.05 V and V_DS = 0.7 V respectively. The SOI FinFET devices D2 and D3 have an improved value of gain 33.06 and 32.60 dB as compared to device D1 in the saturation region respectively. The slightly low gain (30.01 dB) of SOI FinFET device-D1 is due to the low g_m, which is due to the Si₃N₄ material used in the device. For all SOI FinFET devices, the gain is calculated according to Eq. (3).

Device	g_m (S)		g_d (S)	A_V (dB)	TGF (V^?1)		V_EA (V)
Device	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.7 V	V_DS = 0.7 V	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.7 V
D1	9.04 × 10^?5	1.9 × 10^?4	4.39 × 10^?6	30.01	36.90	35.08	5.30
D2	1.06 × 10^?4	1.80 × 10^?4	4.0 × 10^?6	33.06	37.92	35.97	6.35
D3	1.24 × 10^?4	2.01 × 10^?4	4.71 × 10^?6	32.60	37.21	34.60	6.45

Table3.
Analog performance of device D1, D2, and D3 for V_DS = 0.7 V and V_DS = 0.05 V.

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Device	g_m (S)		g_d (S)	A_V (dB)	TGF (V^?1)		V_EA (V)
Device	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.7 V	V_DS = 0.7 V	V_DS = 0.05 V	V_DS = 0.7 V	V_DS = 0.7 V
D1	9.04 × 10^?5	1.9 × 10^?4	4.39 × 10^?6	30.01	36.90	35.08	5.30
D2	1.06 × 10^?4	1.80 × 10^?4	4.0 × 10^?6	33.06	37.92	35.97	6.35
D3	1.24 × 10^?4	2.01 × 10^?4	4.71 × 10^?6	32.60	37.21	34.60	6.45

$ {A_ {
m{V}}} = frac{{{g_ {
m{m}}}}}{{{g_ {
m{d}}}}} .$

(3)

Combined performance characteristics of g_d (output conductance) and I_D (drain current) for SOI FinFET devices D1, D2, and D3 with the function of V_DS (drain to source voltage) for the value of V_GS = 0.35 V and V_GS = 0.7 V are plotted in Fig. 4. It is an essential requirement of the low value of output conductance (g_d) in order to have a large value of gain for analog circuit design. The high value of g_d means low output resistance, which increases the drain current with V_DS in saturation and this effect is known as channel length modulation. At a high gate bias point (V_GS = 0.7 V) as compared to a low gate bias point (V_GS = 0.35 V), there is much fluctuation of g_d of all devices D1, D2, and D3 with V_DS, which is shown in Fig. 4. The improved value of drain current, gain, and early voltage are obtained for HfO₂ SOI FinFET devices, which are the essential requirements of analog circuit design. Output conductance and early voltages for all SOI FinFET structures are obtained according to Eqs. (4) and (5) respectively.

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Figure4.
(Color?online) Output conductance (g_d) and drain current (I_D) against V_DS characteristics for (a) V_GS = 0.35 V, (b) V_GS = 0.7 V.

$ {g_ {
m{d}}} = frac{{partial {I_ {
m{D}}}}}{{{V_ {
m{DS}}}}} ,$

(4)

$ {V_ {
m{EA}}} = frac{{{I_ {
m{D}}}}}{{{g_ {
m{d}}}}} .$

(5)

3.2
RF Performance evaluation

The RF or high frequency performance of SOI FinFET devices D1, D2, and D3 is evaluated by RF circuits parameters like transconductance frequency product (TFP), gain frequency product (GFP), cut-off frequency (f_T), and gain trans-conductance frequency product (GTFP) for the value of drain to source V_DS = 0.7 V and V_DS = 0.05 V. A combined plot of C_gd (gate to drain capacitance) and C_gs (gate to source capacitance) against of V_GS (gate to source voltage) for D1, D2, and D3 devices for values of V_DS = 0.7 V and V_DS = 0.05 V are shown in Fig. 5. The SOI FinFETs D2 and D3 have more value of capacitances C_gs and C_gd as compared to device D1 due to more fringing field effects, which are generated by an increased value of ‘k’ in HfO₂ dielectric spacer material. Device D3 has a significantly large value of C_gs and C_gd in the strong inversion region due to the source/drain extension region, which results in optimization of source/drain resistance.

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Figure5.
(Color?online) C_gd (gate drain capacitance) and C_gs (gate source capacitance) against V_GS characteristics for (a) V_DS = 0.05 V and (b) V_DS = 0.7 V.

Cut-off frequency (f_T) is also the key parameter to observe and analyze the performance of SOI FinFET based RF circuits. At the cut-off frequency, the unity value of current gain is generated and it is defined according to Eq. (6)^[32].

$ {f_ {
m{T}}} approx frac{{{g_ {
m{m}}}}}{{2pi ({C_ {
m{gs}}} + {C_ {
m{gd}}})}} .$

(6)

The f_T observation against V_GS can be observed in Fig. 6 and it is noticed that due to more value of ‘k’ in HfO₂ spacer material, cut-off frequency of devices D2 and D3 decreases. The low value of f_T for devices D2 and D3 as compared to device D1 occurs due to the relatively higher value of intrinsic capacitances C_gs and C_gd as compared to the trans-conductance (g_m). The peak value of f_T of all SOI FinFETs corresponds to the peak value of g_m and a minimum value of gate to source/drain capacitances.

The other RF parameters of devices D1, D2, and D3 are GFP, GTFP, and TFP, which are obtained by Eqs. (7), (8), and (9) respectively. The C_gs, C_gd, GTFP, GFP, TFP, and f_T parameters are evaluated for devices D1, D2, and D3 for the values of V_DS = 0.05 V and V_DS = 0.7 V and are shown in Table 4 and Table 5 respectively. For the effective analysis of RF circuit performance, values are obtained at V_GS = V_DD/2 = 0.35 V.

Device	C_gd (aF)	C_gs (aF)	GTFP (GHz)	TFP (GHz/V)	GFP (GHz)	f_T (GHz)
D1	33.4	35.6	6.44 × 10⁴	1.11 × 10³	1.13 × 10⁴	195.83
D2	54.9	57.6	8.70 × 10⁴	1.40 × 10³	1.83 × 10⁴	132.45
D3	78.8	84.6	3.63 × 10⁴	5.66 × 10²	7.49 × 10³	116.86

Table4.
RF Performance of Device D1, D2, and D3 at V_DS = 0.05 V.

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Device	C_gd (aF)	C_gs (aF)	GTFP (GHz)	TFP (GHz/V)	GFP (GHz)	f_T (GHz)
D1	33.4	35.6	6.44 × 10⁴	1.11 × 10³	1.13 × 10⁴	195.83
D2	54.9	57.6	8.70 × 10⁴	1.40 × 10³	1.83 × 10⁴	132.45
D3	78.8	84.6	3.63 × 10⁴	5.66 × 10²	7.49 × 10³	116.86

Device	C_gd (aF)	C_gs (aF)	GTFP (GHz)	TFP (GHz/V)	GFP (GHz)	f_T (GHz)
D1	8.35	44.4	1.22 × 10⁵	2.79 × 10³	1.82 × 10⁴	413.15
D2	14.6	73.1	7.48 × 10⁴	1.82 × 10³	1.22 × 10⁴	296.29
D3	41.6	99.4	3.18 × 10⁴	1.14 × 10³	5.67 × 10³	202.09

Table5.
RF Performance of Device D1, D2, and D3 at V_DS = 0.7 V.

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Device	C_gd (aF)	C_gs (aF)	GTFP (GHz)	TFP (GHz/V)	GFP (GHz)	f_T (GHz)
D1	8.35	44.4	1.22 × 10⁵	2.79 × 10³	1.82 × 10⁴	413.15
D2	14.6	73.1	7.48 × 10⁴	1.82 × 10³	1.22 × 10⁴	296.29
D3	41.6	99.4	3.18 × 10⁴	1.14 × 10³	5.67 × 10³	202.09

${
m GFP} = {frac{{{g_ {
m{m}}}}}{{{g_ {
m{d}}}}}} {f_ {
m{T}}} ,$

(7)

$ {
m GTFP} = {frac{{{g_ {
m{m}}}}}{{{g_ {
m{d}}}}}} {frac{{{g_ {
m{m}}}}}{{{I_ {
m{D}}}}}} {f_ {
m{T}}} = {A_ {
m{V}}} cdot {
m TFP} ,$

(8)

${
m TFP} = {frac{{{g_ {
m{m}}}}}{{{I_ {
m{D}}}}}} {f_ {
m{T}}} .$

(9)

From Figs. 6(a) and 6(b) the peak values of GTFP for D1, D2, and D3 at V_DS = 0.05 V are achieved at V_GS = 0.2275 V, V_GS = 0.1925 V, and V_GS = 0.1925 V and low levels of corresponding currents are 4.41, 7.23, and 9.8 μA respectively. In saturation region (V_DS = 0.7 V), the high value of GTFP achieved at V_GS = 0.2625 V, V_GS = 0.3675 V, and V_GS = 0.385 V for devices D1, D2, and D3 respectively. All these biasing points are the best regions of operation for a circuit designer with tradeoff among speed, trans-conductance, and gain of the device. At these bias points, the high value of GTFP is obtained for devices D1, D2, and D3 due to higher g_m, f_T, and low g_d values.

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Figure6.
(Color?online) GTFP (gain transconductance frequency product) and f_T (cut-off frequency) against V_GS for (a) V_DS = 0.05 V and (b) V_DS = 0.7 V.

Eq. (9) describes the occurrence of the tradeoff between effective used power and bandwidth of SOI FinFET device; the equation is most used in moderate and high-performance RF circuit design applications. GFP is described by Eq. (8) and is also an important metrics in amplifiers design in high-speed applications. Both TFP and GFP against V_GS for the values of V_DS = 0.05 V and V_DS = 0.7 V for SOI FinFET devices D1, D2, and D3 are shown in Figs. 7(a) and 7(b) respectively. It is observed from Figs. 7(a) and 7(b) that the values of TFP and GFP increase with increasing V_GS in the sub-threshold region, and moving towards the saturation region it decreases. All devices D1, D2, and D3 are compared in terms of GTFP, f_T, GFP, and TFP values, device D1 gives better performance, and D2 and D3 give optimum performance with respect to RF circuit applications.

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Figure7.
(Color?online) GFP (gain frequency product) and f_T (cut-off frequency) against V_GS for (a) V_DS = 0.05 V and (b) V_DS = 0.7 V.

Further optimum analog/RF performance of device D3 is obtained by optimization of high-k space length from 2 nm to 16 nm at V_DS = 0.7 V with the help of the 3-D simulation process, which is shown in Table 6. It is noticed from the simulated results in Table 6 that at V_DS = 0.7 V, on increasing the spacer lengths, there is an improvement in the digital performance parameters like SS, I_off, I_on/I_off, and TGF with compromising in analog performance parameters like I_on and g_m. At V_DS = 0.7 V, 12 nm spacer length gives improved gain value with optimum cut-off frequency and slightly compromises in the digital performances.

Device spacer region, L_{sp, hk}	SS (mV/decade)	I_on (μA)	I_off (nA)	I_on/I_off	TGF (V^?1)	g_m (S)	g_d (S)	C_gg (fF)	f_T (GHz)	Gain, A_V(g_m/g_d) (dB)
2 nm	83.53	106.80	185.85	574.7	25	2.15 × 10^?4	1.14 × 10^?5	0.210	163	25.5
5 nm	69.89	100.23	58.56	1711.6	32.5	2.02 × 10^?4	5.54 × 10^?6	0.150	215	31.24
8 nm	66.62	96.80	39.83	2430.3	34.9	1.96 × 10^?4	4.14 × 10^?6	0.133	235	33.50
12 nm	65.11	92.56	31.36	2951.5	36.1	1.89 × 10^?4	2.25 × 10^?6	0.137	219	38.48
16 nm	65.12	31.23	2.19	14 260.3	39.3	4.35 × 10^?5	7.30 × 10^?7	0.681	102	35.50

Table6.
Simulated results at different spacer length for SOI FinFET at V_DS = 0.7 V.

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Device spacer region, L_{sp, hk}	SS (mV/decade)	I_on (μA)	I_off (nA)	I_on/I_off	TGF (V^?1)	g_m (S)	g_d (S)	C_gg (fF)	f_T (GHz)	Gain, A_V(g_m/g_d) (dB)
2 nm	83.53	106.80	185.85	574.7	25	2.15 × 10^?4	1.14 × 10^?5	0.210	163	25.5
5 nm	69.89	100.23	58.56	1711.6	32.5	2.02 × 10^?4	5.54 × 10^?6	0.150	215	31.24
8 nm	66.62	96.80	39.83	2430.3	34.9	1.96 × 10^?4	4.14 × 10^?6	0.133	235	33.50
12 nm	65.11	92.56	31.36	2951.5	36.1	1.89 × 10^?4	2.25 × 10^?6	0.137	219	38.48
16 nm	65.12	31.23	2.19	14 260.3	39.3	4.35 × 10^?5	7.30 × 10^?7	0.681	102	35.50

4.
Conclusion

The analog/RF performance has been explored through 3-D device simulation for SOI FinFET devices D1, D2, and D3. An analysis is done for static and dynamic performance with Si₃N₄ and HfO₂ spacers SOI FinFET devices. SCEs performance parameters SS, DIBL, and analog/RF parameters like V_EA, f_T, A_V, GTFP, GFP, and TFP explored to find out the effective operating point for analog/RF circuit designs. It is observed that at V_DS = 0.7 V, device D3 has 63.93 % and 12.35 % in ‘ON’ current improvement as compared to devices D1 and D2 respectively. Device D2 has 3.61 % and 2.29 % improvement in SS values as compared to devices D3 and D1 and device D1 has a much-improved value of DIBL as compared to devices D2 and D3. So, there is always tradeoff among I_on, SS, and DIBL parameters. For analog performance devices, D2 and D3 have a slightly improved value of early voltage and gain with respect to device D1 in the saturation region. Both devices D2 and D3 have better analog performance as compared to device D1 but device D2 has poor performance in current driving capability as compared to device D3. Device D3 has a good current driving capability with optimum analog performance characteristics. For RF performance, device D1 gives better results in terms of GTFP, f_T, GFP, and TFP parameters due to Si₃N₄ material used for the spacer region. At an optimized value of spacer length 12 nm, device D3 gives better analog/RF performance at V_DS = 0.7 V. So, we conclude that there is always tradeoff among SCEs, analog, and RF performance parameters of SOI FinFET at the 20 nm node.