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3D modelling based comprehensive analysis of high-<i>κ</i> gate stack graded channel dua

本站小编 Free考研考试/2022-01-01



1.
Introduction




The unremitting device scaling for continuous growth of silicon technology has resulted in higher device density alongside the extraordinary functional capacity in terms of high current drive in semiconductor integrated chips (ICs)[1]. However, the current CMOS logic circuits not only require high transconductance but also low leakage and low subthreshold swing. The device scaling has weakened the gate control over the channel due to the increased influence of the drain voltage in the channel in addition to lowering of the source potential barrier in a traditional planar bulk MOSFET. This has resulted in the introduction of performance degrading short channel effects (SCEs) like drain induced barrier lowering (DIBL), Vth roll-off, higher subthreshold swing (SS), and hot carrier effects (HCEs) in nanoscale planar MOSFET[2, 3]. In order to mitigate the underlying SCEs, the nanoscale MOSFET has ushered in non-conventional structures like trigate and SOI[4–6]. The trigate (TG) configuration enhances threefold the gate control over the channel and its innate ability of suppressing various SCEs has subsequently forged into an appealing structural choice to continue the MOSFET scaling trend[7, 8]. Further, the multiple material gate and graded channel have also demonstrated aptness in diminishing the deteriorating impact of draining the electric field on the channel[9, 10]. The use of high-κ gate dielectric and gate stack (GS) in nanometer MOSFET has been found effective in reducing the gate leakage current and attaining enhanced control of the channel[11, 12]. The techniques of separating the device body and substrate by a buried insulating layer (BL) has further improved the device electrostatics by reducing parasitic capacitances[13].



Goel et al.[14] have reported a 2-D analytical threshold model of a graded channel dual material double gate MOSFET and have reported that the optimized values of gate-length ratio, doping concentrations, and gate materials can effectively control performance degrading effects like threshold voltage roll-off, HCEs, and DIBL. A 3D analytical surface potential model of Trigate SOI MOSFET has been given by Ghanatian and Hosseini while the performance analysis of a dual material trigate-silicon-on-nothing (SON) MOSFET has been proposed by Pritha et al. employing a gate electrode composed of two materials to improve the device ability in mitigating SCEs[15, 16].



To combine the advantages of gate and channel engineering alongside the high-κ GS and BL with TG MOSFET, a new device structure called gate-stack graded-channel dual material trigate (GSGCDMT) SON MOSFET is proposed in this work where the BL layer is composed of air/vacuum. An analytical model of the proposed structure has been developed illustrating the potential distribution, electric field profile, Vth, and SS. The rest of the paper has been organized as follows. The proposed GSGCDMT-SON-MOSFET is demonstrated in Section 2. The 3-D analytical model is derived in section 3. Results and discussions are presented in Section 4. The conclusion is drawn in Section 5.




2.
Device structure




The proposed structure of GSGCDMT-SON MOSFET has been shown in Fig. 1. The device consists of a channel being surrounded by gate electrodes on three sides. The gate is engineered to be made of two metals of M1 and M2 with work-functions ?m1 = 4.8 eV and ?m2 = 4.4 eV respectively. The length of gate metals are in the ratio of 2 : 1. The channel is graded into two regions with two different doping concentrations Na1 = 1.5 × 1020 cm?3 and Na2 = 1 × 1018 cm?3, and the ratio of the lengths of the two regions is 1 : 2. The device channel and substrate are separated by a buried insulating layer of air. The source and drain doping concentrations are ND = 2 × 1026 m?3. The other device parameters - channel length (L), thickness of BL layer tbox, thickness of channel (tSi), and width of channel (w) are taken as 40, 10, 30, and 10 nm respectively. The stacked gate oxide is composed of two oxides: low-κ silicon dioxide (SiO2) and high-κ hafnium dioxide (HfO2) with thickness $t_{
m SiO_2}$ = 1 nm and $t_{
m HfO_2}$ = 2 nm respectively. The high-κ oxide layer helps in overcoming the leakage and scaling problems while SiO2 provides the interface stability and mitigates the fringing fields. In order to calculate the effective oxide thickness (EOT), the use of ${
m{EOT}} = $${t_{{
m{High}} {text{-}} kappa }}displaystylefrac{{{varepsilon _{{
m{Si}}{{
m{O}}_2}}}}}{{{varepsilon _{{
m{High}} {text{-}} kappa }}}}$ is considered inappropriate for non-planar devices, so we have considered the expression given in Eq. (1) for calculating the EOT in the proposed trigate MOSFET [17]






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Figure1.
(Color online) 3-D schematic of gate-stack graded-channel dual material trigate MOSFET.










${
m{EOT}} = {
m{}}frac{w}{{{{cal F}_{{
m{High}} {text{-}} kappa}}}}left[ {{{left( {1 + {{cal F}_{{
m{High}} {text{-}} kappa}}frac{{{t_{{
m{Si}}{{
m{O}}_2}}}}}{w}}
ight)}^{frac{{{{cal F}_{{
m{High}} {text{-}} kappa}}{varepsilon _{{
m{High}} {text{-}} kappa}}}}{{{{cal F}_{{
m{SiO}}_2}}{varepsilon _{{
m{SiO}}_2}}}}}} - 1}
ight],$


(1)



where $t_{
m SiO_2}$, $varepsilon_{
m SiO_2} $, ε${}_{{
m{High}} {text{-}} kappa}$, and ${cal F}$$ {}_{{
m{High}} {text{-}} kappa}$ are dielectric thickness of SiO2, dielectric constant of SiO2, and ${{
m{high}} {text{-}} kappa}$ dielectric respectively. ${cal F}$$ {}_{{
m{High}} {text{-}} kappa}$ and ${cal F}_{
m SiO_2}$ are fitting parameters of SiO2 and ${{
m{high}} {text{-}} kappa}$ dielectric (HfO2) whose values are estimated as 1.5 and 0.95 respectively.




3.
Analytical model formulation




In order to have better insight into the operation of the proposed MOSFET structure, the physics based compact analytical model of the surface potential and threshold voltage has been presented in this section.



3.1. Surface potential modeling



The device considered is GSGCDMT-SON MOSFET and has been divided into three regions – Region 1 corresponding to halo doping Na1 controlled by gate material M1of length L1, Region 2 corresponds to doping Na2 under the control of gate material M1, and Region 3 corresponds to channel doping of Na2 and gate material M2 given as









${
m{Region; 1!!:;}} {0 leqslant y leqslant {L_1};;0 leqslant z leqslant {t_ {
m{Si}}};; - frac{w}{2} leqslant x leqslant frac{w}{2}} ,$


(2)









${
m{Region;2!!:;}} {{L_1} leqslant y leqslant {L_2} - {L_1};;0 leqslant z leqslant {t_ {
m{Si}}};; - frac{w}{2} leqslant x leqslant frac{w}{2}} ,$


(3)









${
m{Region; 3!!:;}} {{L_2} leqslant y leqslant L - {L_3};;0 leqslant z leqslant {t_ {
m{Si}}};; - frac{w}{2} leqslant x leqslant frac{w}{2}} .$


(4)



The source is assumed to be grounded and drained at a potential VDS. The gate-source voltage (VGS) is common to trigate and across different gate materials. As the potential in the channel gradually increases from source to drain, this variation can be approximated by a parabolic function[18]. If λ = 1, 2, and 3 represent the channel region, then the potential profile between the lateral gates can be written as









${psi _lambda }left( {x,y,z}
ight) = {mu _{0lambda }}left( {y,z}
ight){x^2} + {mu _{1lambda }}left( {y,z}
ight)x + {mu _{2lambda }}left( {y,z}
ight),$


(5)



where ψ1(x, y, z), ψ2(x, y, z), and ψ3(x, y, z) represent the electrostatic potential distribution in Region 1, Region 2, and Region 3.



The coefficients of Eq. (5) can be found using following boundary conditions[19]









${left. {{psi _1}left( {x,y,z}
ight)}
ight|_{y = 0}} = {V_{
m bi,1}},hspace*{fill}tag{6a}$


(6a)









${left. {{psi _1}left( {x,y,z}
ight)}
ight|_{y = L}} = {V_{
m bi,2}} + {V_ {
m{DS}}}.hspace*{fill}tag{6b}$


(6b)



Vbi, 1 and Vbi, 2 are the built-in potential at the source/channel and drain/channel junction respectively.



The electric field at the gate–oxide and channel interface is assumed to be continuous in GSGCDMT-SON MOSFET, we have









${left. {frac{{
m d{psi _lambda }}left( {x,y,z}
ight)}{{dz}}}
ight|_{x = 0,z = 0}} = frac{{{varepsilon _ {
m{eff}}}}}{{{varepsilon _ {
m{Si}}}.
m EOT}}left( {{psi _{
m slambda }}left( y
ight) - V_{
m GSlambda }^{
m{'}}}
ight),hspace*{fill}tag{6c}$
ight),hspace*{fill}tag{6c}$
'/>

(6c)









${left. {frac{{
m d{psi _lambda }}left( {x,y,z}
ight)}{{dz}}}
ight|_{x = 0,z = {t_ {
m{Si}}}}} = frac{{{varepsilon _ {
m{BL}}}}}{{{varepsilon _ {
m{Si}}}{t_ {
m{BL}}}}}left( {V_{
m sblambda }^{
m{'}} - {psi _{
m sblambda }}left( y
ight)}
ight).hspace*{fill}tag{6d}$
m sblambda }}left( y
ight)}
ight).hspace*{fill}tag{6d}$
'/>

(6d)



Because of the symmetry along the x-direction as shown in Fig. 2(b), we have






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Figure2.
(Color online) Cross-sectional view of graded-channel gate-stack dual material trigate MOSFET.










${psi _lambda }left( { - frac{w}{2},y,z}
ight) = {psi _lambda }left( { + frac{w}{2},y,z}
ight).hspace*{fill}tag{6e}$


(6e)



εeff, εBL, and εSi are the dielectric constant of the front gate oxide, BL, and silicon body respectively. EOT and tBL are the thicknesses of the front gate oxide and BL respectively. VGS' = VGS – VFbλ, where VFb1, VFb2, and VFb3, represent the channel flatband voltage in Region 1, Region 2, and Region 3 respectively. Vsbλ' = Vsub – VFbbλ, Vsub is the substrate bias voltage and VFbbλ is the back channel interface flatband voltage. ψsλ(y) and ψsbλ(y) represent the front channel surface potential and back channel potential.



Using above boundary conditions, the coefficients are obtained as









${mu _{0lambda }}left( {y,z}
ight) = left( {frac{4}{{{w^2}}}left( {{psi _{
m slambda }}left( y
ight) - {mu _{2lambda }}left( {y,z}
ight)}
ight)}
ight),$


(7)









${mu _{1lambda }}left( {y,z}
ight) = 0.$


(8)



The coefficient μ2λ(x, y) can be derived by assuming the parabolic potential profile in the vertical direction for low VDS such that the potential in the center plane of the channel of GSGCDMT-SON MOSFET can be written as [20]:









$begin{aligned}&{mu _{2lambda }}left( {y,z}
ight) !=! {psi _{
m s}}left( y
ight) !+! displaystylefrac{{{varepsilon _ {
m{eff}}}}}{{{varepsilon _ {
m{Si}}}.
m EOT}}left( {{psi _{
m s}}left( y
ight) - V_{
m GSlambda }^{
m{'}}}
ight)z ,- &frac{{left[ {left( {displaystylefrac{{{C_ {
m{BL}}}}}{{{C_ {
m{eff}}}}} !+! frac{{{C_ {
m{BL}}}}}{{{C_ {
m{Si}}}}} !+! 1}
ight){psi _{{
m s}lambda }}left( y
ight) !-! left( {1 !+! displaystylefrac{{{C_ {
m{BL}}}}}{{{C_ {
m{Si}}}}}}
ight)V_{
m GS1}^{
m{'}}}
ight]displaystylefrac{{{C_ {
m{eff}}}{t_ {
m{BL}}}}}{{{varepsilon _ {
m{BL}}}}} !-! V_{
m sblambda }^{
m{'}}}}{{t_ {
m{Si}}^2left( {1 !!+!! 2displaystylefrac{{{C_ {
m{Si}}}}}{{{C_ {
m{BL}}}}}}
ight)}}{z^2},end{aligned}$
ight)z ,- &frac{{left[ {left( {displaystylefrac{{{C_ {
m{BL}}}}}{{{C_ {
m{eff}}}}} !+! frac{{{C_ {
m{BL}}}}}{{{C_ {
m{Si}}}}} !+! 1}
ight){psi _{{
m s}lambda }}left( y
ight) !-! left( {1 !+! displaystylefrac{{{C_ {
m{BL}}}}}{{{C_ {
m{Si}}}}}}
ight)V_{
m GS1}^{
m{'}}}
ight]displaystylefrac{{{C_ {
m{eff}}}{t_ {
m{BL}}}}}{{{varepsilon _ {
m{BL}}}}} !-! V_{
m sblambda }^{
m{'}}}}{{t_ {
m{Si}}^2left( {1 !!+!! 2displaystylefrac{{{C_ {
m{Si}}}}}{{{C_ {
m{BL}}}}}}
ight)}}{z^2},end{aligned}$
'/>

(9)



where Ceff, CBL, CSi represent the effective front gate oxide capacitance, BL capacitance, and Si channel capacitance.



The surface potential ψsλ in GSGCDMT-SON MOSFET can be calculated by solving a three dimensional Poisson’s equation [21] given by









$frac{{{partial ^2}psi left( {x,y,z}
ight)}}{{partial {x^2}}} + frac{{{partial ^2}psi left( {x,y,z}
ight)}}{{partial {y^2}}} + frac{{{partial ^2}psi left( {x,y,z}
ight)}}{{partial {z^2}}} = - frac{{q{{left. {N{a_{ {j}}}left( {x,y,z}
ight)}
ight|}_{{{j}} = 1,2}}}}{{{varepsilon _ {
m{Si}}}}},$


(10)



where ${left. {N{a_{ {j}}}left( {x,y,z}
ight)}
ight|_{{ {j}} = 1,2}} = left( {N{a_{ {j}}} + nleft( {x,y,z}
ight)}
ight)$, and n(x, y, z) is the mobile electron charge density and ${ {j}}$ corresponds to channel doping. Considering full depletion approximation for the channel under zero bias condition and $N{a_{ {j}}} gg nleft( {x,y,z}
ight)$ such that $N{a_{ {j}}}left( {x,y,z}
ight) cong qN{a_{ {j}}}$, q is electron charge.



On solving Eqs. (5) and (10) using the coefficients derived in Eqs. (7), (8), and (9), we get









$frac{{{partial ^2}{psi _{{
m s}lambda }}left( y
ight)}}{{partial {y^2}}} - alpha {psi _{
m s}}left( y
ight) = {beta _lambda } - 2frac{{{t_ {
m{Si}}}}}{{delta {C_ {
m{Si}}}}}left[ {{w^2} - 4left( {{x^2} + {z^2}}
ight) - }
ight]V_{
m sblambda }^{
m{'}},$

'/>

(11)








$begin{split}alpha =& left{ {8frac{{{C_ {
m{eff}}}}}{delta }left[ {t_ {
m{Si}}^2left( {1 + frac{{{C_ {
m{Si}}}}}{{{C_ {
m{BL}}}}}}
ight)}
ight]z + 2frac{{{C_ {
m{Si}}}}}{{delta {t_ {
m{Si}}}}}left[ {frac{{{C_ {
m{eff}}}}}{{{C_ {
m{BL}}}}} + frac{{{C_ {
m{eff}}}}}{{{C_ {
m{Si}}}}} + 1}
ight]}
ight.&left. times;{left( {{w^2} - 4left( {{y^2} + {z^2}}
ight)}
ight)}
ight},end{split}$









$begin{aligned}& {beta _lambda } = qN{a_{cal {j}}}{w^2}{delta ^{ - 1}}left( {1 + 2frac{{{C_ {
m{Si}}}}}{{{C_ {
m{BL}}}}}}
ight)t_ {
m{Si}}^2 + 4t_ {
m{Si}}^2frac{{{varepsilon _ {
m{eff}}}}}{{EOT delta }}left( {1 + 2frac{{{C_ {
m{Si}}}}}{{{C_ {
m{BL}}}}}}
ight)& quad times x , t_ {
m{Si}}^2 , V{{
m{'}}_{
m GSlambda }} +left( {frac{{{C_ {
m{eff}}}}}{{{C_ {
m{BL}}}}} + frac{{{C_ {
m{eff}}}}}{{{C_ {
m{Si}}}}}}
ight)left( {{w^2} - left( {{x^2} + {z^2}}
ight)}
ight)frac{{{C_ {
m{Si}}}}}{{{t_ {
m{Si}}}delta }}V{{
m{'}}_{
m GSlambda }},end{aligned}$
m GSlambda }} +left( {frac{{{C_ {
m{eff}}}}}{{{C_ {
m{BL}}}}} + frac{{{C_ {
m{eff}}}}}{{{C_ {
m{Si}}}}}}
ight)left( {{w^2} - left( {{x^2} + {z^2}}
ight)}
ight)frac{{{C_ {
m{Si}}}}}{{{t_ {
m{Si}}}delta }}V{{
m{'}}_{
m GSlambda }},end{aligned}$
'/>








$begin{aligned}delta &= left( {t_{{
m{Si}}}^2left( {1 + 2frac{{{C_{{
m{Si}}}}}}{{{
m{BL}}}}}
ight)}
ight)left( {{w^2}{varepsilon _{{
m{Si}}}} + {C_{{
m{eff}}}}left( {{w^2} - 4{z^2}}
ight)x}
ight) &- left( {frac{{{C_{{
m{eff}}}}}}{{{C_{{
m{BL}}}}}} + frac{{{C_{{
m{eff}}}}}}{{{C_{{
m{Si}}}}}} + 1}
ight)left( {{varepsilon _{{
m{Si}}}}left( {4{z^2} - {w^2}}
ight){x^2}}
ight),end{aligned}$




The general form of surface potential ψsλ(y) in GSGCDMT-SON MOSFET can be obtained by solving the second order differential equation given in Eq. (11). Its solution is given as









${psi _{{
m s}lambda }}left( y
ight) = {{cal C}_lambda }{{
m e}^{eta {{cal P}_lambda }}} - {{cal D}_lambda }{{
m e}^{ - eta {{cal P}_lambda }}} - {sigma _lambda }.$


(12)



Here ${sigma _lambda } = - frac{{{beta _lambda }}}{alpha }$, $eta = sqrt alpha $, and ${{cal P}_lambda }$ takes the value ${{cal P}_1} = y$, ${{cal P}_2} = y - left( {{L_2} - {L_1}}
ight)$, and ${{cal P}_3} = y - {L_2}$. ${{cal C}_lambda }$ and ${{cal D}_lambda }$ are arbitrary constants to be determined by using the following boundary conditions:



i. ${psi _1}{left. {left( {x,{L_1},z}
ight)}
ight|_{x = 0,z = 0}} = {psi _2}{left. {left( {x,left( {{L_2} - {L_1}}
ight),z}
ight)}
ight|_{x = 0,z = 0}}$



ii. ${psi _{{
m s}1}}left( {{L_1}}
ight) = {psi _{{
m s}2}}left( {{L_2} - {L_1}}
ight)$



iii. ${left. {displaystylefrac{{
m d{psi _{s1}}}left( {x,y,z}
ight)}{{{
m d}y}}}
ight|_{y = {L_1}}} = {
m{}}{left. {displaystylefrac{{
m d{psi _{s2}}}left( {x,y,z}
ight)}{{{
m d}y}}}
ight|_{y = {L_2} - {L_1}}}$



iv. ${left. {{psi _2}left( {x,{L_2},z}
ight)}
ight|_{x = 0,z = 0}} = {left. {{psi _3}left( {x,{L_2},z}
ight)}
ight|_{x = 0,z = 0}}$



v. ${psi _{{
m s}2}}left( {{L_2}}
ight) = {psi _{{
m s}3}}left( {{L_2}}
ight)$



vi. ${left. {displaystylefrac{{
m d{psi _{s2}}}left( {x,y,z}
ight)}{{{
m d}y}}}
ight|_{y = {L_2}}} = {
m{}}{left. {displaystylefrac{{
m d{psi _{s3}}}left( {x,y,z}
ight)}{{{
m d}y}}}
ight|_{y = {L_2}}}$.



Using the above boundary conditions, we get the coefficients ${{cal C}_lambda }$ and ${{cal D}_lambda }$ as








$begin{split}&{{cal C}_1} = left{ {left( {{V_{
m bi,2}} + {V_{
m DS}} + {sigma _3}}
ight) !-! left( {{V_{
m bi,1}} !+! {sigma _1}}
ight){{
m e}^{ - eta L}} }
ight.& quad +! left( {{sigma _1} - {sigma _2}}
ight)cosh left( {eta left( {{L_3} !-! left( {{L_1} !-! {L_2}}
ight)}
ight)}
ight) & quad left.{+ left( {{sigma _2} - {sigma _3}}
ight)cosh eta left( {{L_3}! -! {L_2}}
ight)}
ight}{left{ {2sinh left( {eta L}
ight)}
ight}^{ !-! 1}} ,end{split}$









${{cal D}_1} = left( {{V_{
m bi,1}} + {sigma _1}}
ight) - {{cal C}_1},$









${{cal C}_2} = {{cal C}_1}{
m e}^{{eta} {L_1}} - left( {{sigma _1} - {sigma _2}}
ight)/2,$









${{cal D}_2} = {{cal D}_1}{
m e}^{ - eta {L_1}} - left( {{sigma _1} - {sigma _2}}
ight)/2,$









${{cal C}_3} = {{cal C}_2}{
m e^{eta}} left( {{L_2} - {L_1}}
ight) - left( {{sigma _2} - {sigma _3}}
ight)/2,$









${{cal D}_3} = {{cal D}_2}{
m e^{ - eta}} left( {{L_2} - {L_1}}
ight) - left( {{sigma _2} - {sigma _3}}
ight)/2.$




3.2. Threshold voltage modelling



The threshold voltage is taken to be that value of gate source voltage (VGS) at which the minimum surface potential ψs(ymin) = 2?F, where ?F is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level[22]. ymin is the position of minimum surface potential in the channel, which occurs under the higher work-function gate material (M1), and can be calculated as:









${left. {frac{{{partial ^2}{psi _{s1}}left( y
ight)}}{{partial {y^2}}}}
ight|_{y = {y_{min}}}} = 0.$


(13)




4.
Result and discussion




To verify the proposed 3-D analytical model, all the device simulations have been performed using 3D device simulator ATLAS[23]. Several physics-based models are used for GSGCDMT-SON MOSFET simulation like the concentration dependent mobility model, transverse field and temperature dependent Arora models. Shockley-Read-Hall and Auger recombination model have also been employed in the simulation. The employed device parameters are as given in Table 1.






Device structure?m1 (eV)?m2 (eV)Na1 (cm?3)Na2 (cm?3)
Conventional4.84.81.5 × 10201.5 × 1020
DMG4.84.41.5 × 10201.5 × 1020
GC4.84.81.5 × 10201 × 1018
DMG-GC4.84.41.5 × 10201 × 1018





Table1.
Employed device parameters.



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Device structure?m1 (eV)?m2 (eV)Na1 (cm?3)Na2 (cm?3)
Conventional4.84.81.5 × 10201.5 × 1020
DMG4.84.41.5 × 10201.5 × 1020
GC4.84.81.5 × 10201 × 1018
DMG-GC4.84.41.5 × 10201 × 1018





Fig. 3 shows the surface potential distribution plotted as a function of channel length for gate and channel engineered devices and against different gate oxides. Fig. 3(a) shows the comparison of surface potential distribution for different gate dielectrics for GSGCDMT-SON MOSFET. It can be observed that the high-κ dielectric (HfO2 + SiO2) gate stack increases the surface potential than a low-κ dielectric (SiO2), implying higher gate capacitance and reduced gate leakage current while assuring small capacitive coupling than high-κ gate dielectric (HfO2). The comparison of surface potential distribution between conventional (single material gate and non-graded channel), dual material gate (DMG), graded channel (GC), and the DMG-GC with gate stack TG SON MOSFET is shown in Fig. 3(b). The conventional TG device has the lowest minimum potential and has been found to suffer from DIBL due to VDS fluctuations. With DMG TG device structure, the source junction is shielded from VDS fluctuations because of the step in the potential profile. In the GC TG device, the high-doped implant is confined around the source region, while rest of the channel is lightly doped. The Vth of the device will be controlled by the implant region reducing the effective channel length resulting in a higher drive current. The DMG-GC TG device will be a high performance device as the DMG will shield the device against the DIBL effect and GC will improve the drain-to-source punch through resistance and consequently improve the short channel behavior of the device.






onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18060023-3.jpg'"
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Figure3.
(Color online) Surface potential distribution as a function of channel length. (a) Surface potential versus different gate oxide. (b) Surface potential distribution for conventional, DMG-, GC-, and DMG-GC- GS Trigate SON MOSFET as a function channel length.




Fig. 4 shows the variation of the GSGCDMT-SON MOSFET surface potential distribution as a function of channel length for different values of drain voltage (VDS). It can be observed that no or little change in surface potential distribution occurs in a major portion of the channel length except towards the drain side of the channel. This indicates the device’s ability in suppressing the performance degrading DIBL effect due to gate and channel engineering techniques. The analytical and simulated values are in close agreement with each other. Fig. 5 shows the comparison in the variation of lateral electric field Eλ(y) = – ?ψsλ(y)/?y of DMG-GC, DMG, GC, and conventional gate stack TG SON MOSFET as a function of the position along the channel length[24]. It can be seen that the electric field is almost uniform throughout the channel and redistributes mostly at the drain side, which is a desired characteristic for superior device performance. The electric field at the drain in case of the proposed DMG-GC-GS-TG SON MOSFET is significantly reduced due to low doping of the corresponding channel region and use of low work-function gate material near the drain. This results in an enhanced HCE suppression thus improving device reliability.






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Figure5.
(Color online) Variation of electric field along the channel for conventional, GCTG, DMTG, and GSGCDMT SON MOSFET.






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Figure4.
(Color online) Surface potential distribution as a function of channel length for GSGCDMT SON MOSFET against different values of Vds.




Fig. 6 shows the plots of the threshold voltage as a function of position along the channel. In Fig. 6(a), the threshold voltage is compared between conventional, DMG, GC, and DMG-GC gate stack TG SON MOSFET as a function of channel length. It can be observed that the threshold at the smaller gate length tends to roll off due to the close proximity between source and drain and at the large gate length, remains constant. The Vth is minimum in the case of the graded channel as the high-doped channel region reduces the effective channel length while it is highest in the case of the conventional Trigate structure due to the higher channel potential barrier. The DMG-GC has a slightly higher Vth than the GC structure due to the dual material gate configuration and thus provides higher transconductance than the conventional and DMG trigate structure. Fig. 6(b) shows the influence of different gate oxides on the threshold voltage of GSGCDMT-SON MOSFET. It can be observed that the threshold roll off increases with high-κ gate dielectric signifying higher carrier velocity. The DMG-GC trigate SON MOSFET with HfO2 as gate dielectric can be seen to provide higher threshold voltage roll-off due to higher field induced barrier lowering which substantiate faster device operation in addition to reduction of leakage current in the off state of the device.






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class="figure_img" id="Figure6"/>



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Figure6.
(Color online) Threshold voltage variation as a function of channel length. (a) Threshold voltage variations for conventional, DMG-, GC-, and DMG-GC-GS Trigate SON MOSFET. (b) Threshold voltage variations for different gate oxides.




Fig. 7 shows the DIBL comparison of DMG, GC, and DMG-GC with GS TG SON MOSFET as a function of position along the channel from source to drain. It can be seen from the figure that the GSGCDMT SON MOSFET shows better performance in suppressing DIBL, which is defined as






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class="figure_img" id="Figure7"/>



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Figure7.
(Color online) DIBL comparison along the channel for DMG, GC, and DMG-GC GS-TG-SON MOSFET. The symbols in the graph represent the simulated values from TCAD for the proposed model.









${
m DIBL} = {
m{}}frac{Delta{{V_{
m th}}}}{{Delta{V_{
m DS}}}} = frac{{{{left. {{V_{
m th}}}
ight|}_{
m lin}} - {{left. {{V_{
m th}}}
ight|}_{
m sat}}}}{{{{left. {{V_{
m DS}}}
ight|}_{
m sat}} - {{left. {{V_{
m DS}}}
ight|}_{
m lin}}}}.$




This reduction of DIBL in GSGCDMT structure is due to better gate controllability and screening of the minimum potential position from VDS due to gate and channel engineering techniques. The calculated and simulated values are in close agreement.



Fig. 8 shows the variation of the subthreshold swing ${
m SS} = 2.3{v_t}{left[ {{{left. {frac{{{
m d}{phi _{{
m s}1}}left( y
ight)}}{{{
m d}{V_{
m GS}}}}}
ight|}_{y = {y_{
m min}}}}}
ight]^{ - 1}}$ along the channel length for the DMG, GC, and DMG-GC with GS TG SON MOSFET[25]. It can be observed that the subthreshold swing is minimum in the case of GSGCDMT -SON MOSFET. This can be attributed to the small off state leakage current and better gate control of the channel due to the graded channel and dual material gate architecture of the device. The subthreshold swing attains a maximum value of about 80 mV/dec at the source junction, and it gradually goes down and saturates to about 60 mV/dec. Thus, a major portion of the channel is protected against SCEs and hence improves the performance of nanoscale MOSFET. All this detailed analysis about SCEs over the proposed model brings us to a conclusion about the aptness of this structure to subdue various SCEs like DIBL, HCEs, and improve the device electrostatics. This makes the proposed MOSFET structure quite a promising candidate in the era of device miniaturization as the structure is compatible with conventional planar technology. The calculated and simulated results almost match each other.






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class="figure_img" id="Figure8"/>



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Figure8.
(Color online) Subthreshold Swing comparison along the channel GC-, DMG-, and DMG-GC- GS-TG SON MOSFET. The symbols in the graph represent the simulated values from TCAD for the proposed model.





5. Conclusion




In this work, the graded channel gate stack dual material trigate SON MOSFET has been investigated for SCEs in the nano regime by the developed analytical model of the surface potential and threshold voltage based on three dimensional Poisson’s equation. The results obtained clearly establish that the proposed structure exhibits higher immunity to SCEs, which can be understood from the surface potential distribution, electric field, threshold voltage, DIBL, and subthreshold characteristics. The close agreement between the results obtained from the analytical model and the simulation validates the proposed model.



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