1.
Introduction

Nowadays, the complementary metal-oxide semiconductor (CMOS) chips’ feature size has commercially developed to 5 nm. FinFETs are promising to extend CMOS scaling owing to reduced short-channel effects^[1]. Compared with planar devices, FinFET has the following advantages, such as near-ideal subthreshold slope, excellent gate control over the body potential, low leakage current and higher mobility^[2]. On behalf of the high-performance device, FinFET also attracts the attention of applications in radiation environment, such as in space.



However, there are some serious reliability problems for aerospace devices, such as HCI and radiation damages. Channel hot carriers are generated by impact ionization under the action of a strong electric field near the drain. When these carriers are launched to the gate, oxide layer trap charges and interface states will be generated, which will affect the performance parameters of the devices, such as threshold voltage, subthreshold swing, saturation current and trans-conductance, etc^[3]. The FinFET with a small feature size has a strong internal electric field, thus the HCI can be significant. Some studies show that HCI is dependent on fin width^[4]. Ma pointed out that parameter degradation caused by 14 nm FinFET HCI is mainly attributed to interface states, and the distribution of interface states on the top of FinFET fins is significantly less than that on the lateral wall of fins^[5]. After studying the HCI of 90 nm SOI FinFET with different channel lengths, Jiang pointed out that the degradation mechanism of long-channel devices and short-channel devices is different^[6]. Yeh pointed out that 20 nm bulk FinFET with fewer fins show better device characteristics, but the degradation of device parameters caused by hot carriers is more serious^[7]. Moreover, different evolutions of the threshold voltage and the saturation current of the UTBB nMOSFETs may be due to the slow border traps^[8].



For devices used in a radiation environment, not only the conventional reliability problems should be considered, but also the influence of radiation effects on the conventional reliability of devices should be paid attention to. Silvestri pointed out that, for 130 nm NMOSFETs, the parameter degradation of the un-irradiated nMOSFETs is smaller than that of the irradiated sample after applying hot carrier stress^[9]. The larger the bias, the smaller the degradation of device parameters. Zheng pointed out that hot carrier degradation of irradiated 65 nm nMOSFETs is greater than those without irradiation due to radiation-induced charge trapping in the STI^[10]. The influence of TID (total ionizing dose effect) on HCI of short channel UTBB FD-SOI nMOSFETs is significant, which is due to irradiation generated defects in buried oxide (BOX)^[11]. For nMOSFET, the synergistic effect of total dose irradiation and hot carriers exceeds the simple superposition of the two effects. It considers that the combination of holes in the oxide trap induced by the total dose irradiation and hot electrons reduces the positive charge in the oxide trap. The irradiation-induced interface state captures the hot electrons to form negative interface trap charges^[12]. But, to the best of our knowledge, no studies have shown how total ionizing dose radiation affects HCI in 22 nm FinFETs.



The HCI of nFinFET with different fin numbers and the influence of total ionizing dose irradiation with different bias conditions on the HCI of nFinFET are studied in the paper. We demonstrate that the smaller the fin number, the more obvious the HCI of nFinFETs. What is more, compared with un-irradiated nFinFET, the HCI of irradiated nFinFET is weakened, which is different from the experimental phenomena of planar devices.

2.
Experiment and devices

The devices used in this test are bulk nFinFETs produced by the process of 22 nm. The gate length of devices is 60 nm. Fig. 1 shows the structure diagram of the device. The channel of the device is a parallel fin-like structure with various fin numbers, 2, 4, 8 and 16, the effective width of single fin 2H_fin + W_fin = 80 nm, and the effective fin width of the device W_eff = N(2H_fin + W_fin), where N is the fin number and working voltage V_DD = 0.8 V. HfO₂ and SiO₂ are employed as the gate oxide. The devices are divided into two groups, while samples in group A are un-irradiated before hot-carrier stress and samples in group B are radiated before hot-carrier stress with different bias conditions during irradiation. There are some samples failed during the experiment because of ESD damage. The samples in group A were tested on a Keithley 4200 semiconductor parameter analyzer to conduct the hot carrier stress test. The stress condition used in this test was V_GS = V_DS = 1.2 V with the body and the source grounded. The total stress time was 6000 s. The I_DS–V_GS characteristics were obtained at the stress time of 1, 3.2, 10, 31.6, 100, 316.2, 1000, 3162.3, and 6000 s, respectively. When testing the I_DS–V_GS curve of the device, the drain voltage was set to 0.1 V, the body and source were grounded, and the gate voltage was increased from 0 to 0.8 V.






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Figure1.
(Color online) The structure diagram of nFinFET. (a) A 3D model of bulk FinFET. (b) A cross-section view along A–A’ direction^[13].




In addition, samples in group B were taken for the pre-irradiation test. The dose rate used for irradiation was 425.26 rad(Si)/s, and the total ionizing dose for 60 nm gate length samples was 2.5 Mrad(Si). There were three bias conditions: ON, OFF and TG, during irradiation for all the samples in group B. The ON bias condition was carried out with the gate applied with 0.8 V and other electrodes 0 V. The OFF bias condition was carried out with the drain applied with 0.8 V and other electrodes 0 V. The TG bias condition was carried out with the source and drain applied with 0.8 V and other electrodes 0 V. The floating annealing was carried on at room temperature for one week after irradiation. After annealing, the hot carrier stress test was carried out. The test conditions and process are the same as above.

3.
Experimental results

Fig. 2 shows the degradation of V_T for un-irradiated nFinFETs in group A with different fin numbers and gate length of 60nm under HCI stress. It is shown that as the stress time increases, the V_T degradation percentage of 4 fin devices is significantly higher than the latter two with 8 fin and 16 fin.






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Figure2.
(Color online) Degradation of V_T for nFinFETs with different numbers of fins under HCI stress for samples with a 60 nm gate length.




Fig. 3 shows the degradation of I_DSAT for nFinFETs with different numbers of fins under HCI stress. We can see that there is also more degradation on devices with fewer fins. Fig. 4 shows I_DS–V_GS curves as a function of the irradiation dose for nFinFET with 8 fins and 60 nm gate length biased at ON state. As the dose increases, the I_DS–V_GS curve shifts positively, and V_T and I_DSAT increase.






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Figure3.
(Color online) Degradation of saturation current (I_DSAT) for nFinFETs with different numbers of fins under HCI stress for samples with a 60 nm gate length.






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Figure4.
(Color online) I_DS–V_GS curves as a function of the irradiation dose for nFinFET with 8 fins and a 60 nm gate length biased at the ON state.




Fig. 5 shows the degradation of V_T as a function of stress time for un-irradiated nFinFETs and irradiated nFinFETs in different bias conditions during irradiation. Table 1 shows the threshold voltage degradation percentage of un-irradiated and irradiated samples. The figure and the table indicate that the V_T degradation of all devices under the hot carrier test decreases a lot, and the HCI of the irradiated devices weakens.

Device	Un-irradiated	OFF irradiated	TG irradiated	ON irradiated
Lgate = 60 nm, 4 fin	30.15%	27.31%	25.63%	4.00%
Lgate = 60 nm, 8 fin	17.32%	14.46%	11.29%	7.69%

Table1.
V_T degradation percentage of un-irradiated devices, OFF-bias irradiated devices, TG-bias irradiated devices, and ON-bias irradiated devices in different groups after 6000 s hot carrier stress.



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Device	Un-irradiated	OFF irradiated	TG irradiated	ON irradiated
Lgate = 60 nm, 4 fin	30.15%	27.31%	25.63%	4.00%
Lgate = 60 nm, 8 fin	17.32%	14.46%	11.29%	7.69%

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Figure5.
(Color online) Degradation of V_T as a function of stress time for un-irradiated nFinFETs and for irradiated nFinFETs in different bias conditions during irradiation. (a) For 4 fin samples with a 60 nm gate length. (b) For 8 fin samples with a 60 nm gate length.




Fig. 6 shows the degradation of I_DSAT as a function of stress time for un-irradiated nFinFETs and irradiated nFinFETs in different bias conditions during irradiation. Table 2 shows the I_DSAT degradation percentage of un-irradiated and irradiated samples. The figure and the table indicate that the channel I_DSAT degradation of the four devices in the hot carrier test decreases successively, and the HCI of the irradiated devices weakens.

Device	Un-irradiated	OFF irradiated	TG irradiated	ON irradiated
Lgate = 60 nm, 4 fin	9.56%	7.39%	3.88%	1.24%
Lgate = 60 nm, 8 fin	4.5%	3.68%	3%	1.67%

Table2.
I_DSAT degradation percentage of un-irradiated devices, OFF-bias irradiated devices, TG-bias irradiated devices, and ON-bias irradiated devices in different groups after 6000 s hot carrier stress.



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Device	Un-irradiated	OFF irradiated	TG irradiated	ON irradiated
Lgate = 60 nm, 4 fin	9.56%	7.39%	3.88%	1.24%
Lgate = 60 nm, 8 fin	4.5%	3.68%	3%	1.67%

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Figure6.
(Color online) Degradation of I_DSAT as a function of stress time for un-irradiated nFinFETs and for irradiated nFinFETs in different bias condition during irradiation. (a) For 4 fin samples with a 60 nm gate length. (b) For 8 fin samples with a 60 nm gate length.

4.
Discussion and analysis

In a FinFET, all fins share one gate. As the gate voltage is positive, negative inversion charges are generated in the fins. Because the same charges repel each other, inversion charge density decreases in the adjacent fins. When the number of fins increases, the coupling effect between fins is more significant^[7], the charge density of the inversion layer in the fins decreases, and the channel hot carrier density decreases. And under the effect of the electric field, the impact ionization induced by the hot carrier near the drain is weakened, and the oxide trapped charge and interface state are reduced. Thus, for samples with more fin numbers, HCI weakens, as shown in Figs. 2 and 3.



The Si–H bond exists at the interface between the gate oxide layer and silicon of FinFET^[14], and the Si–H bond can be broken by total dose irradiation and hot carriers, generating oxide trap charge and interface state, and degrading the device performance. Pre-irradiation makes part of Si–H bond rupture and device parameters degrade. The HCI experiment carried out after irradiation will make the rest of the Si–H bond rupture. The fracture of the Si–H bond caused by HCI is reduced compared with that without irradiation, resulting in the reduction of the degradation of device parameters caused by HCI.



For another reason, under the action of hot carrier stress, the hot electrons generated by the impact ionization at the drain end will be injected into the gate oxide layer and form oxide trap charges, which is why the V_T drifts positively as the stress time increases^[7]. Total dose irradiation causes trap holes in the shallow trench isolation (STI) region of the FinFET, and the bottom region of the fin generates an additional electric field introduced by irradiation^[13]. Fig. 7 shows the schematic diagram of total dose irradiation causes trap holes. The direction of the electric field is opposite to the original electric field at the bottom of the fin. Therefore, the electric field in the bottom region of the fin is weakened, and the channel electric field strength is weakened. During the application of hot carrier stress, the hot carrier generation is reduced and the HCI is weakened due to the weakening of the channel electric field. The total ionizing dose effect of bulk FinFET is affected by the irradiation bias conditions. For the three irradiation bias conditions, the ON state bias is the worst bias condition, followed by the TG state, and the total dose irradiation under the OFF state bias has the least impact on the device^[16]. During the total dose irradiation, trapped charges will be generated in the STI region of the bulk FinFET. Therefore, the bulk FinFET HCI is weakened by total dose irradiation. While at ON bias, there are most traps, and the channel electric field strength decreases most.






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Figure7.
(Color online) A schematic diagram showing that total dose irradiation causes trap holes in STI^[15].

5.
Conclusion

For bulk nFinFET produced by the 22 nm process, as the fin number increases, the charge density of the inversion layer inside the fin decreases due to the charge coupling between fins. In the hot carrier test, the more the fin number, the more the impact ionization weakened, the V_T and channel I_DSAT degradation are reduced, and thus the HCI is weakened. In the total dose irradiated device, the radiation has broken some Si-H bonds. In the subsequent HCI test, compared with the un-irradiated devices, the number of Si–H bonds affected by hot carriers decreases, and the degradation of device performance decreases. Moreover, the trapped charges generated by the radiation in the STI reduce the channel electric field. Therefore, HCI is weakened by total dose irradiation in nFinFET. Further investigation needs to be carried out for deeply mechanism analysis.

Acknowledgements

This work was supported by Youth Innovation Promotion Association CAS (2018473), the National Natural Science Foundation of China under Grant NO. 12075313, and the West Light Foundation of The Chinese Academy of Sciences (Grant No.2019-XBQNXZ-A-003).