1.
Introduction
Over the past 50 years, Moore's Law, which guides the transistor scaling down to 10 nm[1, 2], has been the golden rule for semiconductor industry. A large number of new technologie[3] have been introduced into semiconductor processes, in which strained silicon[4, 5], high-κ/metal gate[3], and Fin-FET[6, 7] have led to great performance improvement, however, the process has become more complicated at the same time. As the devices are scaling down to sub-10 nm, the power consumption caused by the short channel effect[8] (SCE) makes the global semiconductor industry face unprecedented challenges. To overcome SCE and extend the Moore's Law, new materials, new structures and new mechanism are the main features of future device technology in the post-Moore era. According to the requirements of International Roadmap for Semiconductors 2.0 (ITRS 2.0)[9], beyond complementary metal oxide semiconductor (Beyond-CMOS) will become the key R&D areas in the future, and researchers hope to achieve high performance and low power devices by exploring new operating mechanism. Meanwhile, hetero-integration has received extensive attention. New materials are used to improve the performance in CMOS and memory devices. Otherwise, smarter devices with different functions are integrated with CMOS to realize more abundant applications.
2D layered materials are the hotspots for academic and industry in recent years. Such materials are built up by in-plane covalent bonds and out-plane van der Waals interaction, with general monolayer thickness of below 1 nm. Due to special properties and vast prospects of graphene, Geim and Novoselov at the University of Manchester who exfoliated the monolayer graphene in 2004, won the 2010 Nobel Prize in Physics[10]. The ultra-high mobility of graphene is a huge research motivation for electronic devices, however, zero bandgap greatly limits the application in logic devices. Various methods to open bandgap in graphene, including graphene nanoribbons[11], bilayer AB stacking[12, 13], hydrogenation graphene[14], etc., have been developed, It's almost impossible to maintain high mobility and high on/off ratio at the same time. At present, the mainstream view is that graphene is more suitable for analog RF devices but not digital logic devices.
In recent years, research on 2D logic electronic devices has gradually transferred from graphene to 2D semiconductors with sizeable band gap, which solve the biggest bottleneck of graphene. Among them, transition-metal dichalcogenides (TMDCs) are in-plane sandwich structure composed of transition metal (M) and chalcogen (X) with chemical component of MX2[15–17]. There are more than 40 different materials depending on the chalcogen (usually S, Se, Te) and transition metal elements. TMDCs have various physical properties, including semiconductors[18–20], metals, insulators, semi-metals, superconductors and other forms. Furthermore, researchers have also discovered the layer-dependent band structure[21], electron transport anisotropy[22], topological singularity[23], charge density wave[24] and other strange physical properties, and developed new concept of energy valley electronics[25]. In addition, various 2D materials can be freely built van der Waals heterojunction, which is not limited by the lattice matching of traditional epitaxial growth. Currently, prototype devices such as MOSFETs, tunneling transistors, photodiodes, photodetectors, etc. based on TMDCs and van der Waals heterojunction have been reported[26–29]. Here, we will focus on the contact resistance of TMDC FETs to review the latest progress.
Building a field-effect transistors (FET) as illustrated in Fig. 1 with low total resistance, which comprises of contact resistance (Rc) and channel resistance (Rch), is the key to reach high drive current for high-performance application[30]. Since Rch quickly decreases with the dimension scaling, Rc becomes a dominant factor in the total resistance for sub-100 nm channel length. For current high-performance applications, the typical Rc eigenvalue of less than 0.1 kΩ·μm is a basic requirement[31]. However, partly due to the clean surface without dangling bonds for TMDCs, it is very difficult to form strong covalent bond between metal-TMDC interface. In addition, because of 2D limit, the traditional substitutional doping, which can induce strong interface traps and impurities, is not applicable for TMDC. Besides, strong Fermi level pining observed in TMDC transistors leads to large Schottky barrier whatever metal deposits on TMDC devices. Above all, contact resistance is too high and consequently masks up the device performance[32]. From theoretical computation, the quantum limit of contact resistance is 30 Ω·μm at a carrier density n2D = 1013 m?2[33], which is far below the typical experimental result of a monolayer MoS2 device. Therefore, there is a huge space and need for optimizing the electrical contact properties in TMDC-based transistors, which has been a major research topic in recent years. This review is organized as following. In Section 2 we introduce several methods to measure Rc. In Section 3, common contact topology is discussed. In Section 4, different strategies to engineering contact in TMDC transistors are reviewed, with the focus on reducing Rc and controlling p/n doping.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-1.jpg'" class="figure_img" id="Figure1"/>
Download
Larger image
PowerPoint slide
Figure1.
(Color online) Typical structure of field-effect transistors.
2.
Measurement of contact resistance
Transfer length method (TLM)[32], which is based on the resistive network shown in Fig. 1, is widely adopted to analyze Rc. During this process, the FETs are measured with two probes with various channel lengths, and the resulting total resistance is plotted as a function of channel length. Rc is then extracted from the y-intercept of the fitted line. Under the network model, due to the resistance existed at both the interface and channel, the current would preferably flow through the edge of contact and drop drastically with increasing distance from the edge. Such phenomenon is known as “current crowding”[34], and the length where the current drops to 1/e of the edge value is featured as the “transfer length”[32].
However, whether the transfer length method can correctly characterize the contact resistance at 2D/3D interface is doubtful, since the resistive network model only fits in a bulk semiconductor assuming that the sheet resistance is constant throughout the material. In cases of TMDCs, however, the material under the contact area could have a different doping from the channel area. A systematic study conducted by Xia et al.[35] reveals the electron transport mechanism and brings up a new model. The contact behavior can be better understood by identifying the transmission probability at the vertical contact junction or the in-plane p–n junction at the edge of contact. Computational study of Kang et al.[36] on metal contacts with monolayer TMDCs divides the contact in a similar way. In the most ideal case, a metalized TMDC portion should exist under the contact area to form an in-plane metal-semiconductor Schottky junction.
Besides that, Rc can be directly extracted by parallel 4-probe measurement[37] and fixed channel length method[38]. In a 4-probe measurement, one pair of outside electrodes is used to inject carriers, while another pair of inside electrodes is used to measure the potential drop (Vin) between them. Due to that carrier is not injected from potential measurement electrodes, the measured resistance using the pair of inside electrodes does not cover Rc. Assuming that the resistance of contact metal is much smaller than Rc, the resistance difference between outside and inside pair of electrodes is a reasonably accurate:
$${R_ { m{c}}} = left[ {frac{{{V_ { m{out}}}}}{{{I_ { m{D}}}}} - frac{{{V_ { m{in}}}}}{{{I_ { m{D}}}}}bigg/left( {frac{{{L_ { m{ins}}}}}{{{L_ { m{out}}}}}} ight)} ight]bigg/2,$$  |
where Vout, Vin, Lins, and Lout is the voltage drop and length between outside pair electrodes and inside paired electrodes respectively, and ID is current across the channel,
In fixed channel length method, for two devices fabricated on the same TMDC flake, Rc scales as a function of contact width but fixed channel width. In this case, assuming that contact resistance of 2 devices is same, Rc can be expressed by
$${{R_{ m c}}} = frac{{R_{2 { m{p}}}^{ m Dev1} - frac{{{ ho _ { m{ch}}}{L^{ m Dev1}}}}{{{W^{ m Dev1}}}}}}{2},$$  |
where
$${ ho _ { m{ch}}} = left( {R_{2 { m{p}}}^{ m Dev1} - R_{2 { m{p}}}^{ m Dev2}} ight)Big/left( {frac{{{L^{ m Dev1}}}}{{{W^{ m Dev1}}}} - frac{{{L^{ m Dev2}}}}{{{W^{ m Dev2}}}}} ight),$$  |
and
m 2p}^{
m Dev1} $
m Dev1}$
m Dev1}$
m 2p}^{
m Dev1} $
m Dev1}$
m Dev1}$
3.
Contact topology
Normally, two common interface geometries known as top contact (Fig. 2(a)) and edge contact (Fig. 2(b)) are structured between 2D materials and metals with different characteristics[39]. Since 2D materials have clean surface without dangling bonds, it is hard to form strong covalent bonds with metals. Thus, a van der Waals (vdW) gap could exist in top-contact geometry, forming an additional ‘tunnel barrier’ aside from inherent Schottky barrier, which significantly reduces the charge injection efficiency and increases Rc[36].
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-2.jpg'" class="figure_img" id="Figure2"/>
Download
Larger image
PowerPoint slide
Figure2.
(Color online) Interface geometries of metal-2D contacts: (a) Top-contact configuration, (b) Edge-contact configuration[30].
In contrast, edge contacts to the 1D “surface” of 2D materials can overcome this vdW gap and are expected to perform better than top contacts[36, 40, 41]. The activated 1D edge tends to form stronger hybridization with metals, which reduces the tunnel barrier and has improved transmission probability[42]. Many practical contact structures involve both the edge and the top surface of the 2D material, and the hybrid contact topologies have been studied widely, and they are easier to integrate compared with edge contact. Hence, reducing the contact barrier at the top surface can effectively to improve the contact resistance for TMDC transistors.
4.
Contact optimization
The main goal for improving the electrical contacts of TMDC transistors is to decrease Rc and reduce the SB for both electrons and holes. Many methods have been reported, including forming strong covalent bonds, metalizing the semiconductor, heavy doping, utilizing the tunneling effect, and 1D edge contact[41, 43, 44]. Overall, they can be categorized into three strategies: optimizing metal work function, contact doping/phase change, and interface engineering.
4.1
Optimizing metal work function
From Schottky junction theory it is well-known that the metal work function could greatly impact the Rc. So far, many works have been reported to use various metals including In[45], Sc[46], Al[47], Ti[48], Cr[49], Mo[50], Ni[51], Au[47], and Pt[46]. Traditionally, high and low work function metals tend to form better contact with p-type and n-type semiconductors, respectively[46]. This situation, however, holds theoretically true but is more complicated for TMDCs. The material properties can be very different from the ideal intrinsic conditions due to abrupt structural termination and the existence of foreign atoms at the interface. They can generate defect states and energy levels that do not exist in pristine state. Therefore, the Fermi-level pinning effect could make the contact properties insensitive to the metal work function[52], making it difficult to realize complementary TMDC transistors by different metals. Many other factors should be considered in order to get a better electrical contact experimentally. In the study of Kang et al.[35], three general criteria were set up for selecting metals: the tunneling barrier, Schottky barrier, and orbital overlap, which depend on the width of the vdW gap, metal work function, and the nature of hybridized orbitals. Simulation shows that the Ti/MoS2 interface demonstrates a strong interfacial bonding and high electrons injection efficiency, resulting from the local metalized MoS2 that forms covalent bonds with Ti. Mo is also indicated as a good metal for contacts due to its presence in the lattice of MoS2 which results in better orbital overlap. The work from Popov et al.[53] also uses density functional theory calculations to compare the electron injection efficiency of MoS2/Ti contacts and the conventional MoS2/Au contact as seen in Fig. 3. They found that Ti could out-perform Au in many ways as an electrode material. Besides traditional metals, the use of graphene or even other 2D materials as the contact shows large performance boost, as they are believed to form stronger bonding with the TMDCs[54, 55]. In addition, the work function of graphene can be tuned by electrical doping. Yu et al.[56] made a systematic comparison of the FET performances with graphene and Ti contacts. Rc was decreased by an order of magnitude from 1 to 0.1 kΩ·mm by graphene electrodes.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-3.jpg'" class="figure_img" id="Figure3"/>
Download
Larger image
PowerPoint slide
Figure3.
(Color online) Contact interface between MoS2 and the (a) Au(111) and (b) Ti(0001) surface, (c) Binding energy E per interface metal atom as a function of the separation d between MoS2 and the Ti(0001) and Au(111) surface[53].
4.2
Doping and phase change
Another effective strategy is to dope the semiconductor under the contact area for efficient charge injection, which is similar to Si CMOS. It should be noticed that, in most practices, researchers only dope the semiconductors under contact area to prevent undesired changes in the channel[56]. A reduced Schottky barrier width can be obtained after heavy doping by dopant diffusion or ion-implantation, and the current through the metal–semiconductor contact is greatly enhanced by electron tunneling. However, there are difficulties associated with this method since traditional doping techniques (e.g. ion-implantation) for bulk semiconductors is not compatible with the 2D materials[57]. A more applicable method for ultrathin 2D semiconductors is surface doping[58, 59]. Yang et al.[60] report a chloride molecular doping technique by immersing MoS2 in solutions of dichloroethane so that Cl atoms can occupy the empty sites of S as shown in Fig. 4, but this method is only restricted to WS2 and MoS2. After doping, the contact resistance of WS2 and MoS2 have been decreased to 0.7 and 0.5 kΩ·μm, respectively. More recently researchers have developed a method to n-dope monolayer MoS2[61] or WS2[62] by depositing a layer of AlOx, reaching a contact resistance as low as 480 Ω·μm[63]. In addition to N-type doping, S. Chuang et al. used high work function MoOx as dopant to dope contact region of MoS2 FET. For the first time, a stable and controllable P-type MoS2 FET and a tunable MoS2 homogenous PN junction were realized[63]. For bipolar TMDCs, such as WSe2, the selected contact doping can be used to realize specific transport behavior. K+[58] and NO2[64] can effectively improve the N-doping and P-doping of WSe2 respectively. Controllable P/N doping show the potential for complementary MOSFETs[65].
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-4.jpg'" class="figure_img" id="Figure4"/>
Download
Larger image
PowerPoint slide
Figure4.
(Color online) Schematic of Cl-doped few-layer WS2 back-gate FET and the binding energies of core levels in WS2 with and without the DCE treatment[60].
Similar to surface doping, one can achieve even smaller Rc by phase engineering of the contact, i.e. by converting the semiconducting TMDC to metallic phase under the contact area. One of the smallest Rc for MoS2 FET is obtained by Kappera et al.[66] using this strategy (Fig. 5). They converted the semiconducting 2H (hexagonal) phase MoS2 to metallic 1 T (trigonal) phase by electrochemical intercalation of n-butyl lithium. The Rc was decreased to 200 – 300 Ω·μm level, which was an order of magnitude lower than the top metal contact.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-5.jpg'" class="figure_img" id="Figure5"/>
Download
Larger image
PowerPoint slide
Figure5.
(Color online) Device schematics and characterization of a bottom gated FET with Au deposited directly on (a) the 2H phase MoS2, and (b) the patterned 1T phase MoS2[66].
4.3
Interface engineering
Ideally, the interface between metal and semiconductor can be characterized by Schottky barrier, which can be predicted by the Schottky–Mott rule. However, a small difference of Schottky barrier can be observed among a variety of metals work function, which suggests strong Fermi level pinning still dominate the metal-semiconductor contact[67]. With proper engineering of the metal-semiconductor junction interface, the contact quality can also be greatly improved. The most common method is to insert an ultrathin tunnel layer (Fig. 6)[68] between the semiconductor and metal (Fig. 6(a)). The tunnel layer can alleviate the Fermi level pinning, therefore reducing the SB height. Up to now, many ultrathin oxide (such as MgO, TiO2 and Ta2O5) and BN tunnel layers have been employed in MoS2 FETs[68]. In particular, the SB height of the Co-MoS2 interface was reduced by about 84% by the MgO tunnel barrier[69], and that of Ti-MoS2 interface was reduced from 0.34 to 0.029 eV by the Ta2O5 tunnel layer[68].
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-6.jpg'" class="figure_img" id="Figure6"/>
Download
Larger image
PowerPoint slide
Figure6.
(Color online) (a) Schematic cross-sectional views of the typical metal/insertion-MoS2 sandwich interface. (b) Contact resistivity as function of Ta2O5 thickness[65].
A more powerful strategy is to insert 2D materials such as graphene and BN as the tunnel layer, to form the so-called vdW heterostructures at the contact[29, 70, 71]. The advantage is that the weak vdW interactions between different layers can preserve the intrinsic properties of TMDCs[72]. Since 2010, many efforts have been made to prepare 2D–2D vdW heterostructures[73–76] with excellent properties that can hardly be found in other materials systems, especially for manipulating the generation, confinement and transport of charge carriers within these atomic superstructures, and eventually for optimizing the performance of FET devices[77]. Du et al. directly transferred graphene on monolayer MoS2 followed by contacting with the metal surface to form the metal–graphene–MoS2 interface. They achieved Rc about three times lower than that of the metal–MoS2 contact[70]. This is because the smooth graphene can suppress the formation of interfacial gap states and weaken the Fermi level pinning effect at the metal–MoS2 interface[78]. So far, graphene–MoS2[79, 80], graphene–arsenene[81, 82], graphene–GaSe[83] and graphene–SnS2[84] contacts have been demonstrated in coplanar, staggered and hybrid geometries shown in Fig. 7[85].
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-7.jpg'" class="figure_img" id="Figure7"/>
Download
Larger image
PowerPoint slide
Figure7.
(Color online) Planar 2D transistor based on van der Waals vertical contacts: (a) coplanar contacts, (b) staggered contacts and (c) hybrid contacts[85].
In addition to graphene, BN monolayer is another frequently used interlayer. Farmanbar et al.[86] found that the inserted BN monolayer between the metal and the MoS2 can decrease the metal work function of Co and Ni by ～2 eV, and enables a lineup of the Fermi-level with the MoS2 conduction band for better electron injection. Doped TMDC as the inserted layer is another strategy to realize low Rc contact. Chuang et al. demonstrated that few-layer WSe2 field-effect transistors (FETs) with Nb doped WSe2(Nb0.005W0.995Se2) contacts exhibit low contact resistances of ~ 0.3 kΩ·μm, high hole mobility up to over 200 cm2/Vs, and high drive currents exceeding 320 μA/μm[87]. In a recent work, Su et al.[88] reported an extensive study on the electronic properties of metal-MoS2 interfaces using different kinds of 2D materials (graphene, silicene, germanene, stanene, boron nitride, blue phosphorene, arsenene and antimonene) as the insertion buffer layers by first principles calculations. The result indicates that weaker Fermi level pinning effects and charge scatterings are found at the metal–2D–MoS2 interfaces due to the weak interactions between 2D insertion layers and MoS2 layers. More recently, Liu et al.[89] reported a novel design of vdW metal-TMDC contact with key results displayed in Fig. 8. In their work, the metal contacts were laminated onto MoS2 without direct chemical bonding, and the interface was essentially free from chemical disorder and Fermi level pinning. Basing on this technique, the SB height is effectively tuned by metal work function for the first time, approaching the Schottky-Mott limit. In addition, p-type MoS2 FETs are demonstrated using high work function Pt as contact, which was not possible by direct deposition.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/12/PIC/18080022-8.jpg'" class="figure_img" id="Figure8"/>
Download
Larger image
PowerPoint slide
Figure8.
(Color online) Illustration and structural characterizations of vdW meta–semiconductor junctions[89].
5.
Conclusion and outlook
In conclusion, we briefly reviewed the current status of electrical contacts to 2D TMDC, and strategies to improve Rc and electron/hole injection at the metal-semiconductor interface. The effects of the topology of contacts, metal electrode materials, doping, and interface on the contact properties are discussed in detail.
Although great progress has been made in this area, contact remains to be a critical issue in TMDC transistors, and Rc is 1–2 orders of magnitude higher than Si CMOS. These atomic thin 2D materials have large surface-volume ratio and are highly sensitive to interface, thus the contact performance is primarily determined by the interface property. Customized design and engineering of 2D FET structures and interfaces, such as 2D-metal contact, 2D-tunnel layer, and 2D–2D vdW interfaces, as well as more theoretical and experimental studies are demanded to realize devices with optimal performance[90, 91]. Moreover, the design of novel FET structures and the development of advanced integration techniques are also required for large-scale fabrication and practical applications in the future.
