1.
Introduction

The silicon-based transistor has reached its scaling limit, so the recent focus by researchers is two-dimensional (2D) materials. Recently, Novoslov and Geim experimentally demonstrated graphene-based FET (G-FET) that replaces silicon, which has high mobility and excellent conductivity, but its zero band-gap^[1] limits its applications. G-FET fails to provide an efficient on/off current ratio which is the primary requirement for digital logic circuits. TMDs material (MoS₂, MoSe₂, WSe₂, WS₂, etc.) plays a significant role beyond graphene and post-silicon materials. It is in the form of MX₂ (M = transition metal atom, X = chalcogen atom), which are bonded together by Van der Waals forces^{[2, 3]} and is successfully sustaining in electronics, optoelectronics, and sensors applications^[4–10]. Fig. 1 shows the schematic structure of the MoS₂ layer, and in general the thickness of monolayer MoS₂ is 6.5 ?. MoS₂ has an excellent physical property whereas its band gap varies as its thickness varies. It will act as a direct bandgap semiconductor in monolayer with an energy gap (E_g) of 1.8 eV, and it serves as an indirect band gap with E_g 1.2 eV in bulk^[11–13]. Fig. 2 shows the band structure of MoS₂ for different layers, and the energy bandgap can be tuned based on the layer thickness. The change in the band structure dependent on layer thickness is due to quantum confinement and leads to a change in hybridization of d and P_z orbital of Mo–S atoms respectively. Off-current highly depends on the band gap; a larger band gap helps to achieve a high on-off current ratio.






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Figure1.
(Color online) Schematic structure of MoS₂ layer^[31].






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Figure2.
(Color online) Band structure for different MoS₂ layers^[13].




Jiahao et al. presents an overview of 2D material with its advantages and challenges. The unique property of the 2D material is used to design the next generation of low-cost, low power, and efficient devices^[14]. Fig. 3 shows the trend of choosing the channel materials for efficient MOSFETs, where m_eff is the effective carrier mass, μ is the mobility of the carrier, sSi is the strained Si, and 2D is the two-dimensional material for semiconductors^[15]. The basic issues of two-dimensional materials are inefficient source/drain doping, lower mobility, and large contact resistance. However, the mobility for bulk MoS₂ is large and lower for single layer MoS₂. Many theoretical works are carried out to enhance the mobility of single layer MoS₂ FET. MoS₂ transistors have an immunity to short channel effects because of its thin nature of 2D materials^[16]. In MoS₂ FET, the behavior of the short channel effect could be slightly different from MOSFETs because the MoS₂ transistors are basically majority carrier devices with carrier accumulation for on-state, whereas silicon MOSFETs are minority carrier devices with carrier inversion for on-state.






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Figure3.
(Color online) Scenario of channel material for logic MOSFET^[15].




The mobility for bulk MoS₂ based transistors is in the 200–500 cm²V^?1s^?1 range, and exfoliation of a single layer onto SiO₂ substrate results in a decrease of mobility to 0.1–10 cm²V^?1s^?1. Deposition of high-k dielectric on the single-layer MoS₂ channel and increasing the thickness of MoS₂ layer are the two ways to enhance the mobility of the device. Fischetti et al. have reported the temperature dependent mobility of top-gated monolayer MoS₂ considering the scattering mechanisms, which are usually represented by the power law given in Eq. (1)^[17],

$$mu propto {T^{ - gamma }},$$

(1)

where μ = mobility and γ = power law exponent. As the temperature increases, mobility will decrease due to the increase of phonon scattering^[18–20]. Many theoretical studies have been performed to investigate the improvements in device performance by using dual gate (DG) MoS₂ transistors and graphene/MoS₂ heterostructures^[21–23]. Also, there is a huge interest in downscaling the channel length to 5 nm and to studying critical problems such as the OFF-state leakage current and gate controllability over the channel^[24]. The temperature dependent mobility for different channel thickness is shown in Fig. 4, which states a clear transition of mobility towards higher temperature and thickness dependence^[17]. MoS₂ is a promising and well-developing material in nanofabrication, apart from the theoretical modeling.






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Figure4.
(Color online) Mobility and temperature for different channel layers/thickness^[17].




In this paper, we study the MoS₂ material based transistors, which exhibit an excellent energy band gap, thermal conductivity, and its unique physical properties that are expected to engage research attention to focus on semiconducting devices for most futuristic applications. This paper is organized as follows: Section 2 provides the different synthesis techniques of MoS₂ material. In Section 3, we discuss the impact of high-k dielectrics, contact engineering, and doping strategies to achieve higher device performance. We discuss the logic device applications and 2D heterostructure devices in Section 4. Section 5 concludes the paper.

2.
Synthesis of MoS₂

In this section, we review different synthesis techniques for both cases of mono and few-layered MoS₂ material. Several approaches have been developed to prepare mono or few layered MoS₂ material from bulk crystal such as chemical vapor deposition (CVD), mechanical cleavage, pulsed-laser deposition (PLD), and exfoliation techniques. Mechanical cleavage is the easiest method to make a few layers of MoS₂ flakes, but the control over the thickness and size is poor, making it unsuitable for commercial applications. Exfoliation methods^[25–27] involve the layers being prepared by using either chemicals or through some appropriate solvents (liquid exfoliation), or by using the scotch tape method. For preparing high-quality mono or few layered TMDs nanoflakes, liquid exfoliation is the most preferable and cost-effective method. In PLD, a high energy laser pulse is focused on bulk material, which leads to vaporization and forms a thin film on the substrate^{[28, 29]}. Chemical vapor deposition is used for direct deposition of 2D material on a substrate by using MoO₃ and S powder as reactants. The CVD growth of layer is sensitive to the SiO₂/Si substrate^[30] and the experimental setup using solid precursors is given in Fig. 5. Raman spectroscopy and atomic force microscopy (AFM) are used to determine the thickness of 2D materials. Hong et al. presented the importance of defects that are responsible for large electric and optical properties prepared by mechanical exfoliation, physical, and chemical vapor deposition^[31]. Many techniques have been developed for synthesizing MoS₂ layer from bulk TMDs materials in large scale productions^{[32, 33]}.






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Figure5.
(Color online) Synthesizing monolayer MoS₂ from bulk crystal using the scotch tape method.






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Figure6.
(Color online) CVD experimental set-up. (a) Sulfurization of MoO₃ powder. (b) Sulfurization of Mo films. (c) Schematic illustration of the two-step thermal decomposition of (NH₄)₂MoS₄^[30].

3.
MoS₂ field effect transistors

Semiconducting 2D layered TMDs have a larger band gap and unique physical properties that make it an alternative channel material to silicon-based MOSFET. This exclusive property of MoS₂ provides an excellent opportunity towards the electronic and optoelectronic applications^{[4, 5]}. But it is unsuitable for high-performance devices due to its lower mobility and formation of larger contact resistance (R_c). The possibilities to improve the mobility and device performance are by proper use of (i) the high-k gate dielectric material, (ii) source/drain contact engineering, and (iii) doping techniques. A high-k gate dielectric is suggested to reduce the columbic scattering and used to enhance the mobility of the transistor. Choosing an appropriate metal contact to improve the device performance by achieving low contact resistance for MoS₂ based FET is still challenging. Hence, contact engineering for MoS₂ based FET needs to be studied. Doping also plays a significant role in achieving a low contact resistance; the doping technique for the 2D material is slightly different from the conventional doping technique of silicon-based MOSFETs. We will discuss the impact of high-k dielectric and source/drain contact engineering followed by various doping approaches in the next section.

3.1
High-k gate dielectric screening

Many theoretical studies have been carried out for dielectric engineering of the MoS₂ transistor to enhance the mobility. Research works are exploring both the cases of a single layer and a multilayer channel using different high-k dielectrics. Radisavljevic et al. fabricated the single layer MoS₂ transistor with a channel thickness of 6.5 ? and the MoS₂ layer was synthesized by using the scotch tape method. HfO₂ gate dielectric with an oxide thickness of 30 nm is deposited using the atomic layer deposition technique, and the electron beam lithography technique is applied for contacts. The device achieves the improved mobility of 217 cm²/(V·s) due to the presence of high-k dielectric and large on/off current ratio of 10^8[34]. Fig. 7 shows the schematic device for a single layer MoS₂ transistor. Yoon et al. presented the non-equilibrium Green’s function (NEGF) based quantum transport simulations, with HfO₂ as a top-gate dielectric. The simulated device exhibits an I_on/I_off ratio of 10¹⁰ and a subthreshold slope of nearly 60 mV/dec and achieved maximum ON current of 1.6 mA/μm at a drain voltage of 0.5 V^[35]. Liu et al. demonstrate atomic-layer-deposited high-k integration on 2D MoS₂ crystals with 16 nm ALD-Al₂O₃ as the top-gate dielectric. The multilayer MoS₂ dual gate transistor with Al₂O₃ achieves the maximum drain current of 7.07 mA/mm for the back-gate and 6.42 mA/mm top-gate voltages respectively, at a drain voltage (V_ds) of 2 V with a channel length of 9 μm and top-gate length of 3 μm^[36].






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Figure7.
(Color online) Single-layer MoS₂ transistor^[34].




Geonwook et al. have introduced the fluoropolymer CYTOP as a gate dielectric for enhancement mode operation of back-gated multilayer MoS₂ transistor with the channel thickness of ~12.4 nm. MoS₂ FETs (14 devices) with CYTOP gate dielectric, achieved the threshold voltage V_TH of 5.7 ± 3.5 V with the field effect mobility up to 82.3 cm²/(V·s). The effect of fluorine groups leads to the positive shift in threshold voltage, and surface potential will improve due to the presence of the surface dipole effect in fluorine groups^[37]. Recently, the work presented by Kolla Lakshmi et al. then introduced 30 nm of HfO₂/Si as a new substrate for the back-gated multilayer MoS₂ transistor. The fabricated device exhibits the highest saturation drain current value of 180 μA/μm, the subthreshold slope ranges from 100–110 mV/dec, and it also exhibits I_on/I_off of nearly 10⁶. The HfO₂ back gate dielectric gives 1.5 times larger drain current when compared to SiO₂ back-gated transistors^[38]. Wen et al. presented the atomic layer deposited HfTiO as gate dielectric annealed in different ambient like N₂, O₂, and NH₃. HfTiO/MoS₂ annealed in NH₃ provides a higher carrier mobility of 31.1 cm²/(V·s), the subthreshold swing achieved nearly 100 mV/dec, and it also exhibits a higher on/off current ratio of 10⁶ as compared to other ambient materials^[39]. Many research works have been established to enhance the carrier mobility by dielectric engineering of MoS₂ by using different dielectric materials like silicon nitride, AlN to improve the key parameters (SS, μ_e, current ratio), and used to study the interface property with semiconductor and gate dielectric^[40–42]. You et al. proposed a compact sub-threshold model for the short channel monolayer TMDs field effect transistor, examined the impact of fringe fields from the high-k dielectric, and verified the proposed model with 2D numerical simulations. The nominal device has the gate length 5.9 nm, and the channel thickness for the monolayer is 0.65 nm. Fig. 8 shows the I_DS–V_GS characteristics for different high-k dielectric at a drain voltage of 0.64 V under consideration of 0.41 nm EOT^[43].






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Figure8.
(Color online) I_DS–V_GS characteristics for different dielectric materials^[43].

3.2
The impact of source/drain contact engineering

Understanding the physics of the metal contact with the 2D channel material is different from the conventional Si-MOSFET. The contact between metal and MoS₂ is still much debated and clearly not well understood yet. MoS₂ FETs with a Au electrode is reported as n-type, but controversy remains as whether it is an ohmic contact^{[34, 44]} or a Schottky contact^{[45, 46]}. Similarly, the Pd metal contact claimed to form a Schottky contact with multilayer MoS₂. The study of various contact metals for the MoS₂ transistor is carried out by Banerjee et al. At the Metal-Semiconductor interface the formation of the barrier interrupts the carrier injection and is where Ti is used as the contact metal, which lacks in high device performance due to its unstable property. Large Schottky Barrier heights (SBH) can form behalf of Fermi level pinning nearer to the conduction band of MoS₂. The MoO_x is considered as a contact metal by Chuang who demonstrates the P-type transistor^[47], where MoO_x (x ≤ 3) has a higher work function of 6.6 eV, which injects the hole carrier into MoS₂ to improve the on-current and its device performance. The nominal device shows current in the range of 100 μA/μm and the transconductance exceeds 20 μS/μm. Fig. 9 shows the schematic structure and the I–V characteristic of the MoO₂ transistor with ON and OFF state band diagram.






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Figure9.
(Color online) (a) Schematic and optical microscope image. (b) I_DS–V_GS characteristics at different drain voltage. (c) Band diagram with ON and OFF states. (d) I_DS–V_DS characteristics with MoO_x contact at V_GS varies from 0 to –15 V^[47].




Understanding the nature of contacts in MoS₂ devices with a metal electrode plays an important role in enhancing the carrier injection efficiency. Li et al. have carried the first-principle calculation to compare the geometric and electronic structure of Sc and Ti contacts with monolayer and multilayer MoS₂ to enhance the carrier injection efficiency^[48]. Das et al. present an experimental study of the contact engineering used for n-type multilayer MoS₂ transistors. The metal-MoS₂ interface is strongly affected by Fermi level pinning and lies near to the conduction band.



Fig. 10 shows the I_D–V_G characteristic of a multilayer MoS₂ transistor for different contact metals. Choosing a lower work function like Sc (φ = 3.5 eV) helps to improve carrier injection and forms lower contact resistance. The thickness of exfoliated MoS₂ is 10 nm, scandium acts as metal contacts, and its performance is compared with different contact metals like Ti, Ni, and Pt. The fabricated device achieved mobility up to 700 cm²/(V·s) by incorporating Al₂O₃ as a gate dielectric, and scandium provides the best carrier injection^[45]. Hong et al. introduced a novel device consisting of a highly flexible and transparent multilayer MoS₂ transistor with CVD-grown graphene as electrodes. This MoS₂/graphene interface exhibits a lower Schottky barrier (~22 meV) as compared to other MoS₂/metal interfaces. The fabricated device achieves on/off current ratio (> 10⁴) and an average field effect mobility of 4.7 cm²/(V·s)^[49]. Liu et al. presented the impact of contacts on the performance of a back-gated monolayer MoS₂ field effect transistor, and the importance of contact resistance for the metal–semiconductor interface is revealed and achieved the electron mobility of 44 cm²/(V·s) without using any mobility booster. The exfoliated thickness of monolayer MoS₂ is around 0.9 nm and Ti is used as metal contacts. DFT (density function theory) is used to determine the electronic properties of Ti and MoS₂ interface. The tunneling barrier between M-S below the metal contacts and the Schottky barrier between the contact and the channel has attracted a great deal of attention and contributes more to the contact resistance^[50]. Kang et al. investigated the 2D material as metal contacts for two-dimensional layered structures and explored the suitability of 2D metal contact and 2D semiconductor. Mo acts as metal contacts, and it forms a perfect interface with MoS₂ that exhibits lower resistance, and it improves the device performance for both the monolayer and multilayer transistors^[51]. Type I–III explores the formation of the tunnel barrier and the flow of electrons from the metal to the semiconductor for the ATK simulated device shown in Fig. 11.






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Figure11.
(Color online) Band alignment and band diagram of MoS₂ with different metal contacts^[51].






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Figure10.
(Color online) I_D–V_G characteristics for multilayer MoS₂ transistor for different contact metals^[48].




Yoon demonstrated the metal-contact and doped-contact dependent performance variability on monolayer MoS₂ using self-consistent quantum transport simulations. Metal-contact devices simulated at different SBH from 0.03 to 30 eV and SBH between metal and semiconductor channel slightly affects the output characteristics of a device. For ideal ohmic contact, there is a drastic improvement of on current and transconductance^[52]. Fig. 12 shows the electrical characteristic of contact-dependent performance variability on monolayer MoS₂ FET. Recently, many theoretical studies investigated how to achieve lower contact resistance, henceforth contact engineering plays a significant role in exhibiting a better performance in both the monolayer and multilayer MoS₂ transistors^[53].






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Figure12.
(Color online) (a) I_D–V_G characteristics. (b) I_on and I_on/I_off ratio. (c) I_D–V_D characteristics. (d) Output conductance^[52].

3.3
Doping approach of MoS₂ FET

Another way of reducing the contact resistance between metal and semiconductor is to dope the semiconductor under the metal. Doping of 2D material helps to reduce the Schottky barrier width, and it enhances the current through the M-S junction by electron tunneling^[54]. Investigation of electronic properties for thin-layered crystals through doping is still immature for 2D materials. Yuchen Du demonstrates the n-type doping effect on the multilayer MoS₂ transistor. Polyethyleneimine(PEI) doped FET gives 1.2 times reduction in contact resistance and also there is a vast improvement in field-effect mobility, and the doping effect will also enhance the electrical characteristics of the device. Fig. 13 shows the electrical behavior of MoS₂ FET before doping and after doping. From the figure, it is evident that before doping the ON-current is 10.25 mA/mm and after Polyethyleneimine doping, ON current increases up to 17.61 mA/mm, which is comparatively higher than the PEI doped graphene^[55].






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Figure13.
(Color online) Electrical behavior of MoS₂ FET before and after PEI doping^[55].




An air-stable doping technique pays attention to the electronic and optoelectronic devices. Kiriya et al. represented the use of benzyl viologen (BV) as a surface charge transfer donor for MoS₂ flakes. The fabricated device exhibits excellent stability in both ambient (air and vacuum) and also obtained a high electron sheet density of 1.2 × 10¹³ cm^?2, which corresponds to the degenerate doping limits of MoS₂. The fabricated top gate transistor with BV-doped n+ source/drain contacts exhibits excellent switching characteristics with a subthreshold slope of 77 mV/dec^[56]. The molecular doping technique will help to reduce the metal–semiconductor contact resistance. Yak et al. used chloride doping to reduce the contact resistance for few-layer MoS₂ and WS₂. After doping of MoS₂ and WS₂ with chloride, the contact resistance reduced to 0.5 and 0.7 k?·μm respectively. A reduction in contact resistance is due to n-type doping, and it leads to the reduction in Schottky barrier width^[57]. Fig. 14 shows the n-type doping of chlorine for few-layer MoS₂/WS₂ and the effect on contact resistance. Recently, Robinson et al. demonstrated that the doping efficiency of 2D materials depends on the environment in which the doping occurs, and doping of 2D materials by using non-TMDs materials like Mn is quite challenging. Doping of MoS₂ on the substrate is highly inefficient due to its reactivity of the substrate^[58]. Henceforth, the doping of 2D materials is different from the traditional doping techniques like ion-implantation and dopant diffusion due to its thin nature of layered materials. Fang et al. demonstrated the degenerate n-type doping of potassium for few layered MoS₂^[59] and Rastoki et al.^[60] represented the systematic study of doping strategies for MoS₂ monolayers using surface adsorption.






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Figure14.
(Color online) Chlorine doped TMDs FET and contact resistance after doping for MoS₂/WS₂^[57].

4.
Heterostructures and logic device applications of MoS₂

Heterostructure based transistors are used to improve the device performance. Chih et al. fabricated the Graphene-MoS₂ heterostructures that combine the higher mobility of graphene with the excellent band gap of MoS₂, and this heterostructure is used to tune the on/off current ratio and the mobility through Schottky barrier modulation. Fig. 15 shows the graphene-MoS₂ heterostructure and CVD graphene-coated MoS₂ crystal. Chih et al. investigated the gate-controlled electronic transport, charge transfer and photoluminescence intensity between Graphene and MoS₂ heterostructures without applying any transverse electric field. The work presented by Chih et al. reported that the flow of electrons from MoS₂–graphene can form a new type of nominal device^[61]. Du et al. fabricated the n-type FET using multilayer MoS₂ with Ti/Graphene as a hetero contact as a novel device that exhibits a drain current of 160 mA/mm with a gate length of 1 μm and reaches the current ratio of 10⁷.






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Figure15.
(Color online) (a) Cross-sectional view of graphene/MoS₂ heterostructure. (b) Optical microscope image. (c) Topographical diagram for a CVD graphene-coated MoS₂ single crystal^[61].




Fig. 16 shows the output and transverse curves, which can be estimated for the on-resistance value, and its improvement by using a single graphene layer between MoS₂ and metal. Here the current and voltage characteristics were compared with and without graphene contacts^[62]. The hetero contact of graphene with titanium reduces the contact resistance as compared to the device without using graphene/Ti hetero contact. Zou et al. investigated the exposure of ultra-thin metal oxides (MgO, h-BN, and Y₂O₃) as a buffer layer to attain the radical improvement to enhance the device performance^{[63, 64]}. Therefore, the works established on heterostructure devices provides interesting ways to proceed towards the realization of ohmic contacts for other 2D materials^{[65, 66]}.






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Figure16.
(Color online) (a) Output characteristic with and without graphene at V_bg from ?20 to 5 V. (b) Transfer curve of hetero-contacts for FET in linear (right) and log (left) scale^[62].




The single layer MoS₂ can amplify the signals and performs the logic operations by connecting the two transistors that form the integrated circuit. Though graphene has its advantage, it is quite difficult to fabricate amplifiers and logic circuits^[67] with a voltage gain > 1. The integrated circuit is based on a MoS ₂ transistor, which performs the logic inverter that converts logic 1 to logic 0 and vice versa. The integrated circuit is composed of two transistors and the cross-section view of MoS₂, as shown in Fig. 17. The operation of the logic circuits, which is explained briefly by Radisavljevic^{[68, 69]}, the low input voltage (logic 0), and the high output voltage (logic 1), is to proceed with a single layer of MoS₂ integrated circuits. Just like an inverter NAND gate for bilayer MoS₂^[70], Wang et al. reported a NOR gate by connecting two monolayer MoS₂ transistors in parallel and external resistor act as a load. The V_out is given for all combinations of input values; therefore, the MoS₂ based transistor has a prominent future in integrated circuits and logic operators with low power based transistors^[71]. Fig. 18 shows the fabricated device of NAND gate and SRAM on the thin film and the output voltage of the flip-flop memory. Xin-Ran et al. demonstrated the field effect transistors for logic applications of graphene and MoS₂, and also discussed the prospects for the future development in 2D material based transistor and its excellent property^[72]. Zhong et al. fabricated the top-gated integrated circuits to improve the mobility based on chemical vapor deposition of derived monolayer MoS₂. The fabricated device achieved the mobility of 36.4 cm²/(V·s), which is considered as the highest carrier mobility based on CVD derived single layer MoS₂^[73]. Table 1 presented the performance summary of MoS₂ transistors.






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Figure17.
(Color online) Single layer of integrated MoS₂ transistor^[68].






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Figure18.
(Color online) (a) Optical micrograph of the NAND gate and the SRAM fabricated on the same bilayer MoS₂ thin film. (b) The output voltage of the flip-flop memory cell. (c) Output voltage for NAND gate^[71].

Type of layer	Ion	SS (mV/dec)	Mobility (cm2/(V·s))	Ion/Ioff	Ref.
SL	2.5 μA/μm	74	217	108	[34]
SL	1.6 mA/μm	60	200	1010	[35]
ML	7.07 mA/mm	140	517	108	[36]
ML	180 μA/μm	100–110	11	106	[38]
ML	461 nA/μm	100	31.1	106	[39]
ML	1 μA/μm	74	700	106	[45]
SL	1L = 18 μA/μm	–	1L = 11	105	[51]
ML	5L = 34 μA/μm	–	5L = 25	106	[51]
SL	300 μA/μm	65	–	106	[52]
ML	160 mA/mm	–	50.4	107	[62]
SL	1.5 μA/μm	200	36.4	106	[73]
*SL: single layer; ML: multilayer.

Table1.
Performance summary of MoS₂ transistor.



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Type of layer	Ion	SS (mV/dec)	Mobility (cm2/(V·s))	Ion/Ioff	Ref.
SL	2.5 μA/μm	74	217	108	[34]
SL	1.6 mA/μm	60	200	1010	[35]
ML	7.07 mA/mm	140	517	108	[36]
ML	180 μA/μm	100–110	11	106	[38]
ML	461 nA/μm	100	31.1	106	[39]
ML	1 μA/μm	74	700	106	[45]
SL	1L = 18 μA/μm	–	1L = 11	105	[51]
ML	5L = 34 μA/μm	–	5L = 25	106	[51]
SL	300 μA/μm	65	–	106	[52]
ML	160 mA/mm	–	50.4	107	[62]
SL	1.5 μA/μm	200	36.4	106	[73]
*SL: single layer; ML: multilayer.

5.
Conclusion

In this paper, we review the layered TMDs material MoS₂ with its thickness dependent band gap and temperature dependent mobility. The band gap of MoS₂ layered structure varies from 1.2 eV for an indirect bandgap to 1.8 eV for a direct band gap. The overview of various synthesis techniques and the band structure of MoS₂ material have been reported. A brief study is carried out on the impact of high-k gate dielectric to enhance the mobility of MoS₂ FET and the effect on source/drain contact engineering. We examined different doping approaches to achieve low contact resistance to enhance the device performance of 2D based devices. Improper contacts between metal and MoS₂ possess a serious challenge towards the optimized device. Recent research progress has shown that finding an appropriate metal contact is still challenging and a doping method is needed to focus more on the performance enhancement of the MoS₂ transistor. Since there are many 2D materials with diverse properties that contribute a lot as an alternative channel to silicon-based MOSFETs, the MoS₂ material has a tremendous opportunity for logic device applications and 2D heterostructures. Henceforth, MoS₂ plays a significant role and is used to design the next generation of low cost, low power, and effective devices.