1.
Introduction
4H-silicon carbide (4H-SiC) is a wide bandgap semiconductor, and the devices fabricated from it have shown beneficial effects when used in high power applications[1–5]. This is a result of its unique properties like low intrinsic carrier concentration (5 × 10?9 cm?3), high energy bandgap (3.26 eV), and high thermal conductivity (3.2 W/(cm·K))[6–9]. High value of the critical electric field (2.2 MV/cm parallel to c-axis) means devices with a thinner drift region can be fabricated as compared to Si power devices. Drift region thickness determines the conduction loss occurring in a unipolar device and is higher in devices with thicker drift regions. High saturation velocity of electrons in SiC enables devices to operate at high switching frequencies. Higher the operating switching frequency is, the smaller will be the size of capacitors and inductors required to build high power electrical systems[10]. The fabrication of SiC devices is more demanding and complicated as compared to Si devices. Intrinsic properties of SiC make the devices more useful for temperatures higher than 200 °C. SiC is a robust material and it is difficult to perform any electrical and physical changes to it at temperatures lower than 1000 °C. That means when performing a processing step on SiC, high temperature conditions are required. For example, typically, temperature required to grow a layer of oxide (SiO2) on SiC is 1150 °C but in some cases it could be as high as 1300 °C, which requires special oxidation furnaces, hence conventional quartz furnaces cannot be used[11, 12]. Also, there is negligible diffusion of dopants in SiC, and hence cannot use a temperature annealing approach to drive-in the dopants into the material[13]. The only way to achieve the desired doping profile in SiC is through implantation of dopants, using a high energy implanter (typically 50–500 keV), and sometimes wafers needed to be at high temperatures (~ 500 °C), at the same time. In silicon (Si) devices, it is common to have doping profiles with a junction depth of 5 μm, while in SiC it is hard to achieve even a depth of 2 μm. Implantation of dopants is followed by a dopant activation step in SiC, which requires high temperature annealing conditions. Typically, n-dopants required an activation temperature of 1550 °C, while for p-dopants, the required temperature could be as high as 1700 °C. With n-dopants an activation rate of more than 90% can be achieved, but in the case of p-dopants it is tough to realise an activation rate anywhere near to n-dopants. The reason why a lower temperature is required for n-dopants as compared to p-dopants, is because their ionization energies are lower: ~ 0.06 eV for n dopants and ~ 0.198 eV (Al), 0.28 eV (B) for p-dopants[14]. Also, high temperatures and special metallization schemes are necessary to form ohmic and Schottky contacts on SiC. It is clear that a quite different set of expertise are required to fabricate SiC diodes.
In this paper we will discuss the influence of design and process variations on diodes’ electrical performance. On the design side different active cell designs have been used, such as a segment design or a stripe design. Within each cell design, some parameters have been varied. For example, in the case of a segment design the length (l), width (w) and space (s) between individual segments have been varied. Similar sort of split is done for the stripe design. In addition to the active cell design variation, different junction termination designs are fabricated to facilitate the required blocking voltage. Again, within each termination design different parameters have been varied such as l, w, depth (d), and the number of rings (n). On the processing side we have studied the influence of dopants’ dose (D). Aluminium (Al) is used as a dopant to form p+ regions underneath the Schottky metal contact and to create a termination structure (JTE and FLRs). Diodes with a field limiting rings (FLRs) design have the same dose (D = D1), as is employed to form the p+ grids. For the diodes, where a junction termination extension (JTE) is used as a termination, in addition to dose D1 for the p+ grids, dose D2 was used to create the termination structure of the diodes. Also, all the wafers except one have seen the nitrous oxide (N2O) annealing step.
2.
Experimental details
The 4H-SiC wafers used in this study are purchased from Epiworld. Each wafer has an 18 μm thick n- drift layer, and a doping concentration of 1 × 1016 cm?3. As mentioned before, during the fabrication of these devices two main variations are used. The first one is on the design side of the device, and is shown in Fig. 1. The second variation is implemented on the processing side, and is shown in detail in Fig. 2. In total, five wafers have been processed: wf1, wf2, wf3, wf4, and wf5. All the wafers except the wf5 have been treated with nitrous oxide (N2O). Fig. 3 shows the schematic of a schottky diode (JBS). In this figure we can see different parts of a diode like, the drift region, p+ grids in the active region, the termination region, the passivation layer/layers, and the Schottky and ohmic contacts. In Fig. 4 we can see the top-view of the diode with stripe (a) and segment (b) variations. The parameters which have been varied are width (w), length (l), and space between adjacent stripes/segments. The diodes fabricated in this study are designed to block a reverse bias voltage of 1.7 kV, and to conduct a 4 A forward current. Based upon the best device design and the fabrication process, some 50 A diodes are fabricated and then tested under static and dynamic conditions.
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Figure1.
Two main design variations used during the fabrication of 1.7 kV, 50 A SiC devices. For the active cell there is either a stripe design or a segment design which is used while in the case of termination there are FLR (field limiting ring) and JTE (junction termination extension) variations implemented.
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Figure2.
Two process variations performed on these devices are: dose, N2O passivation. In the case of dose, different doses are used to create the structure in active and termination regions of the device. In the second process split, before depositing Schottky metal, in some cases N2O annealing is done (w/).
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Figure3.
A schematic of a Schottky diode (JBS).
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Figure4.
A schematic of (a) a stripe design and (b) a segment design which are used in the active region of the diode.
3.
Results and discussion
Initially, we will discuss the electrical characteristics of 4 A diodes. All the measurements are done at room temperature. In Table 1, different design variations used to fabricate the diodes are listed. In total, diodes with three different stripe designs (d1–d3) and 5 segments designs (d4–d7) have been fabricated.
| Design | Type | w (μm) | s (μm) | l (μm) |
| d1 | Stripe-1 | w1 | s1 | – |
| d2 | Stripe-2 | w1 | s2 | – |
| d3 | Stripe-3 | w1 | s3 | – |
| d4 | Segment-4 | w1 | s3 | l4 |
| d5 | Segment-5 | w1 | s4 | l5 |
| d6 | Segment-6 | w1 | s4 | l6 |
| d7 | Segment-7 | w2 | s3 | l3 |
| d8 | Segment-8 | w3 | s3 | l3 |
Table1.
Different type of designs employed in the active region of 1.7 kV, 4 A diodes. Designs d1–d3 are different stripe design variations, while d4–d8 are the variations used in the segment design.
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| Design | Type | w (μm) | s (μm) | l (μm) |
| d1 | Stripe-1 | w1 | s1 | – |
| d2 | Stripe-2 | w1 | s2 | – |
| d3 | Stripe-3 | w1 | s3 | – |
| d4 | Segment-4 | w1 | s3 | l4 |
| d5 | Segment-5 | w1 | s4 | l5 |
| d6 | Segment-6 | w1 | s4 | l6 |
| d7 | Segment-7 | w2 | s3 | l3 |
| d8 | Segment-8 | w3 | s3 | l3 |
It must be noted that the width (w) of a stripe/segment is selected in such a way that w1 < w2 < w3. The same is true for other parameters, s1 < s2 < s3 < s4 and l1 < l2 < l3 < l4. The test set-up used to do the static measurements was capable of collecting data only at discrete points. The forward characteristics of a 4 A diode from wf1 are shown in Fig. 5. It is clear from Fig. 5(a) that the stripe design 1 (stripe 1) is most resistive with VF1 = 1.98 V (@ 4 A), and design 3 (stripe 3) is least resistive with the VF3 of 1.66 V. Design 2 has an intermediate value of the forward voltage drop, VF2 = 1.77 V. On the other hand all the segment designs 4, 5, 6, and 7 are less restive, as compared to all but one stripe design (stripe3). Values of the VF for different segments designs 4, 5, 6, 7, and 8 are VF4 = 1.66 V, VF5 = 1.74 V, VF6 = 1.75 V, VF7 = 1.71 V, and VF8 = 1.74 V respectively. It can be seen that the stripe design 3 and the segment design 4 have the lowest VF at 4 A.
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Figure5.
Typical forward characteristics of N2O annealed 1.7 kV, 4 A SiC Schottky diodes at room temperature for different designs namely: (a) stripe designs (d1–d3) and (b) segments designs (d4–d8) in the active region of the diodes. For stripe designs the VF drop at 4 A is higher than any of the segments designs.
In Fig. 6 the reverse characteristics of the diodes fabricated on wf1 are shown. Fig. 6(a) shows the blocking behaviour of the diodes with JTE designs used in the termination region. Clearly, one can see that the conditions (like design parameters and doses etc.) used to fabricate these diodes are not good enough to achieve the desired blocking voltage (≥1.7 kV). It must be noted that “str1 + JTE” means that while fabricating this particular diode, a stripe design in the active region, and a JTE design in the termination region has been used. With str1 + JTE and str2 + JTE, str3 + JTE and seg4 + JTE designs we obtained a breakdown of 1 kV. From Fig. 6(b) it is clear that FLRs termination design has improved blocking capability. In fact, all the diodes with variations seg5 + ring1, seg6 + ring1, seg7 + ring2, and seg8 + ring3 are capable of blocking up to 1.9 kV. The reverse leakage current IR values for these diodes are 85, 75, 170, and 147 μA, respectively at 1.9 kV.
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Figure6.
Typical reverse characteristics of N2O annealed 1.7 kV, 4 A SiC Schottky diodes at room temperature for different termination designs namely: (a) junction termination extension (JTE) and (b) field limiting ring (FLR) in the termination region of the diodes. Only diodes with FLR termination design are able to provide the required blocking voltage.
As mentioned before the dose of p dopant is varied in four wafers (wf1 to wf4). The dose is varied only for the JTE design, and not for the FLR design. The dose increases as we move from wf1 to wf4, and is of the order of 1012 cm?2 for all JTE designs. In the case of FLR, the dose is kept constant and is of the order of 1014 cm?2. No change in the electrical behaviour (static) of the diodes with dose variation is observed. Although, the results shown in Fig. 6 are from wf1, they are a good representation of the diodes that have seen N2O annealing (wf1–wf4).
The test results obtained for wf1–wf5 with JTE as a termination design, are summarized in Table 2. Here, VF, max and VF. min are the maximum and minimum values of the forward voltage drop (VF) obtained from a diode on particular wafer. Note that the VF, max is the VF of a diode which is able to block a maximum reverse bias voltage among all the diodes tested on the same wafer. For example, on wf1 the diode which is able to block 1 kV has a VF of 2.62 V. The same is true for the rest of the wafers, wf2–wf5. On the other hand, the VF, min corresponds to the diode which has the minimum forward voltage drop among all the diodes from the same wafer. The minimum value of the VF is always obtained for a segment design but is not specific to one particular design. Different wafers have diodes with different segment designs which have a minimum value of the VF. As we can see that in the case of wf1 (Fig. 7(b)), all the diodes with different segment designs have approximately the same VF, with a difference of less than 0.1 V. The same is true for wafers wf2, wf3, and wf4. Hence, we can conclude that the VF, min is not always observed for the same segment design. In the case of VF, max the active cell design could be either a stripe or a segment. For N2O annealed wafers (wf1 to wf4) the JTE design resulted in a poor reverse blocking/breakdown voltage (BV) of the diodes. For wafers wf1 to wf3, the BV is as low as 1 kV whilst for wf4 it is 1.5 kV, which is still way a below the required value (1.7 kV).
| Wafer # | VF, max (V) at 4 A | VF, min (V) at 4 A | VR, max (kV) | Outcome (based on the BV of 1.7 kV) |
| 1 | 2.62 | 1.66 | 1 | 0% |
| 2 | 2.47 | 1.68 | 1 | 0% |
| 3 | 2.42 | 1.60 | 1 | 0% |
| 4 | 2.55 | 1.63 | 1.5 | 0% |
| 5 (w/o NO) | 2.23 | 1.58 | 1.9* | 77.2% of the tested devices blocked 1.7 kV. |
| * The minimum and maximum values of IR at 1.9 kV for wafer 5 are 1.64 × 10?4 and 9.47 × 10?4 A respectively. | ||||
Table2.
Summary of the forward voltage drop (VF) and the reverse blocking voltage (VR) obtained from different diodes tested on wafers 1 to 4 (wf1–wf4).
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| Wafer # | VF, max (V) at 4 A | VF, min (V) at 4 A | VR, max (kV) | Outcome (based on the BV of 1.7 kV) |
| 1 | 2.62 | 1.66 | 1 | 0% |
| 2 | 2.47 | 1.68 | 1 | 0% |
| 3 | 2.42 | 1.60 | 1 | 0% |
| 4 | 2.55 | 1.63 | 1.5 | 0% |
| 5 (w/o NO) | 2.23 | 1.58 | 1.9* | 77.2% of the tested devices blocked 1.7 kV. |
| * The minimum and maximum values of IR at 1.9 kV for wafer 5 are 1.64 × 10?4 and 9.47 × 10?4 A respectively. | ||||
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Figure7.
Typical forward characteristics of 1.7 kV, 4 A SiC Schottky diodes at room temperature without (w/o) NO annealing for different designs namely: (a) stripe designs (d1–d3) and (b) segments designs (d4–d8) in the active region of the diodes.
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Figure8.
Typical reverse characteristics of 1.7 kV, 4 A SiC Schottky diodes without (w/o) N2O annealing at room temperature for different termination designs namely: (a) junction termination extension (JTE) and (b) field limiting ring (FLR) in the termination region of the diodes. Both termination design variations are able to block voltages ≥ 1700 V.
Now the results obtained from the diodes fabricated on wf5, w/o N2O anneal will be presented. The static characteristics of the diodes are plotted in Figs. 7 and 8. Again, like the diodes from wafers wf1 to wf4, the stripe design 1 (stripe 1) is found to be most resistive, with the VF of 2.23 V at 4 A. Diodes with designs 2 and 3 have the VF = 2.18 V and VF = 1.87 V, respectively. The results are shown in Fig. 7(a). In the case of a segment design all the diodes have approximately the same value of VF (approximately 1.5 V). These values lie within 1.51–1.58 V, and are shown in Fig. 7(b). The diode with the segment design 8 has the lowest VF8 (1.51 V), whilst the diode with the segment design 6 has the highest value of the forward voltage drop (VF6 = 1.58 V). Results obtained under reverse bias condition for these diodes without (w/o) N2O annealing, are significantly different from the ones which are fabricated on the first four wafers (wf1–wf4), with (w/) N2O annealing. In this case all the diodes except those with design variation, str2 +JTE, are able to block voltages up to 1.9 kV. As one can see that diodes with either termination designs, FLR and JTE, are able to pass the blocking voltage criteria of 1.7 kV. In fact, most of them (as listed in Table 3) are able to survive 1.9 kV reverse bias. The values of IR at 1.9 kV for these diodes, str1 + JTE, str3 + JTE and seg 4 + JTE, are 88, 21, and 131 μA respectively. In the case of the str2 + JTE, the value of IR is 233 μA at 1.7 kV.
| Wafer # | VF, max (V) at 4 A | VF, min (V) at 4 A | IR, max (A) at 1.9 kV | IR, min (A) at 1.9 kV | Outcome (based on the BV of 1.7 KV) |
| 1 | 2.32 | 1.70 | 8.5 × 10?5 | 1.65 × 10?4 | 91% |
| 2 | 2.22 | 1.77 | 9.1 × 10?5 | 2.45 × 10?4 | 87.5% |
| 3 | 2.13 | 1.55 | 1.38 × 10?4 | 8.8 × 10?4 | 100% |
| 4 | 2.20 | 1.60 | 3.2 × 10?5 | 4.20 × 10?4 | 100% |
| 5 (w/o NO) | 2.31 | 1.54 | 1.67 × 10?4 | 9.47 × 10?4 | 75% |
Table3.
Summary of the forward voltage drop (VF) and the reverse blocking voltage (VR) obtained from the diodes tested fabricated on wafer 5 without N2O annealing.
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| Wafer # | VF, max (V) at 4 A | VF, min (V) at 4 A | IR, max (A) at 1.9 kV | IR, min (A) at 1.9 kV | Outcome (based on the BV of 1.7 KV) |
| 1 | 2.32 | 1.70 | 8.5 × 10?5 | 1.65 × 10?4 | 91% |
| 2 | 2.22 | 1.77 | 9.1 × 10?5 | 2.45 × 10?4 | 87.5% |
| 3 | 2.13 | 1.55 | 1.38 × 10?4 | 8.8 × 10?4 | 100% |
| 4 | 2.20 | 1.60 | 3.2 × 10?5 | 4.20 × 10?4 | 100% |
| 5 (w/o NO) | 2.31 | 1.54 | 1.67 × 10?4 | 9.47 × 10?4 | 75% |
A summary of the results obtained from the diodes having FLRs as their termination design, is shown in Table 3. Again, like N2O annealed wafers (wf1 to wf 4), the minimum VF is obtained for a segment design. Although, unlike wf1–wf4 (w/ N2O annealing), diodes with a JTE termination design are able to block voltages up to 1.9 kV. In Table 3 instead of VR, max (maximum value of the blocking voltage) we have included IR, min and IR, max values. These are the minimum and the maximum values of the IR obtained for the diodes with FLR termination designs. The diode which resulted in the IR, min has the VF, min, as its corresponding forward voltage drop at 4 A. For example, in the case of wf1 there is a diode which not only gives a minimum forward voltage drop of VF, min = 1.66 V but is also capable of blocking 1.9 kV with a leakage current of 165 μA. On the other hand, the diode with a maximum forward voltage of VF, max = 2.62 V, has the IR, max = 85 μA. Note that all the diodes tested on wafers 3 and 4 are able to withstand voltages up to 1.9 kV. The device yield on wafers wf1 and wf2 is good (> 87%). For wf5, we are able to get working devices with a blocking capability of 1.9 kV, but the device yield is low (only 75%). Hence, we have seen that N2O annealing has a detrimental effect on the blocking voltages of the diodes without having a significant effect on the VF.
Nitrogen (N) acts as an n-type dopant in SiC, and after N2O annealing there may be some counter doping of the p-doped regions (created by aluminium dopants) by N[15, 16]. These p regions are used underneath the Schottky contact in the termination region. Similarly, it could change the net p doping in the termination region of the diodes and hence can lead to their premature breakdown. For the JTE design, the effect is more predominate as the dose employed is much lower (1012 cm?2) than used in FLR designs. In fact, this is what we observed on the diodes fabricated on the wafers wf1–wf4 involving JTE termination, where the maximum VR ≤ 1000 V. The effect of N2O annealing is not as severe in diodes, which have FLR as their termination design. Previous studies have shown that 2 h N2O annealing of the interface (SiO2/SiC) could lead to the formation of a N monolayer at the interface with an areal density of 1012 cm?2[17]. Also, we have observed that N2O annealing does not have any significant effect on the forward characteristics of the diodes. Based on the results for 1.7 kV, 4 A diodes, some 50 A diodes have been fabricated using three different stripe designs: stripe1, stripe2, and stripe3, (in the active region) along with a FLR design (ring1) in the termination region. The results are shown in Fig. 9. The diode with the stripe3 + ring1 design has the VF = 2.80 V and the IR = 60 μA at 1.7 kV (room temperature).
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Figure9.
(a) Forward-bias characteristics of 1.7 kV, 50 A Schottky diodes at room temperature with different active cell designs but with same FLR design. (b) Reverse-bias characteristics of a 1.7 kV, 50 A Schottky diode at room temperature.
In order to analyse the dynamic behaviour of a 50 A diode, some hybrid substrates (Si-IGBT + SiC-Schottky diode) are built. A typical double-pulse test has been conducted on them. For the sake of comparison, full Si substrates (Si-IGBT + SiC-diode) are also built and tested under the same conditions. The Si IGBTs are rated at 63 A, 1.7 kV while Si diodes are rated at 1.7 kV, 120 A. The same rating IGBTs are used to build full Si and hybrid SiC substrates. These tests have been performed at room temperature. The test results are summarized in Table 4. The electrical parameters which are extracted are: Irr (reverse recovery collector current overshoot), Qrr (stored charge), Eon (energy loss during the turn-on), Erec (reverse recovery energy loss), and Eoff (energy loss during turn-off). As expected, a low reverse recovery energy loss is measured for the hybrid SiC substrate,
m{rec}}}^{{
m {SiC, substrate}}}$
m{rec}}}^{{
m {S, substrate}}}$
| Substrate type | dl/dt (A/μs) | Eon (J) | Irr (μA) | Qrr (μC) | Erec (J) | Eoff (J) |
| Full Si substrate | 280 | 0.017 | 71 | 17 | 0.009 | 0.07 |
| Hybrid SiC substrate | 303 | 0.009 | 18 | 2 | 0.001 | 0.08 |
Table4.
Different electrical parameters namely Irr, Qrr and Erec extracted for a 50 A Schottky diode and a conventional Si diode using a double-pulse test.
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| Substrate type | dl/dt (A/μs) | Eon (J) | Irr (μA) | Qrr (μC) | Erec (J) | Eoff (J) |
| Full Si substrate | 280 | 0.017 | 71 | 17 | 0.009 | 0.07 |
| Hybrid SiC substrate | 303 | 0.009 | 18 | 2 | 0.001 | 0.08 |
4.
Summary
In this paper we have studied the effect of process and design variations on the performance of SiC Schottky diodes. It has been observed that the N2O annealed diodes have a poor reverse blocking capability as compared to the non-annealed diodes. The annealing process has not shown any significant influence on the forward characteristics of the diodes. The segment design resulted in lower VF as compared to the stripe design. Based upon the experimental results obtained from 4 A Schottky diodes, a few 50 A diodes were fabricated. The dynamic test results on these diodes have shown that the SiC diodes have lower reverse recovery energy loss as compared to the conventional Si diodes. Hence, it can be concluded that SiC Schottky diodes can lead to the manufacturing of more energy efficient systems.
