1.
Introduction
Implantable biomedical devices have been widely used to assess physiological information in humans as well as animal models for medical diagnosis, therapeutic applications and biological science studies[1–3]. In those implantable devices with therapeutic functions, such as cardiac pacemakers[4, 5], cochlear implants[6], and brain-machine interfaces[7], high-voltage electrical pulses with magnitude of several to over 10 V are generated to stimulate the neuron or muscle for a particular purpose of treatment. Since most implantable medical devices are powered by a battery with about 2-V supply voltage, charge pumps are often employed to provide high-voltage power supply or control signals for the pulse generators[8–11]. In order to provide a life span up to several years for the implantable medical devices, the power efficiency of the charge pump must be as high as possible. Moreover, a small area is also an important consideration for the charge pumps in implantable medical devices.
Dickson charge pumps are very popular for their simple architectures and are widely employed in applications such as nonvolatile memories and liquid crystal display (LCD) drivers[12, 13]. However, Dickson charge pumps show low power efficiency due to the voltage loss caused by the voltage drops across the diodes or the diode-connected transistors. Although backward control techniques have been developed to reduce the voltage drops in Dickson charge pumps[14, 15], the power efficiency is still not high enough for implantable medical devices.
The charge pump based on the cross-coupled voltage doubler is considered as a much more effective solution in low power applications[16], with a basic structure in standard CMOS process shown in Fig. 1, which consists of a cross-coupled NMOS pair, a cross-coupled PMOS pair acting as serial switches and 2 flying capacitors (C1 and C2) driven by a pair of non-overlapping clock signals. This architecture has higher efficiency than the basic Dickson charge pump for two reasons: (1) the gate–source voltages of MN1 and MN2 are always boosted to aboutVDD by C1 and C2 when they are turned on, ensuring no voltage loss across them in most applications; (2) the load capacitor CL is charged by C1 and C2 alternatively in both clock phases. However, this architecture still has several problems. Firstly, with the increasing of the cascaded stages of the voltage doubler implemented in standard CMOS technology, the threshold voltages of the NMOS transistors increase remarkably along the cascaded stages due to the body effect, resulting in a limited achievable output voltage of the charge pump. The maximum drain voltage that the NMOS transistor can stand also imposes another limit on the achievable output voltage of this architecture[17]. Secondly, the parasitic capacitors parallel to C1 and C2 will reduce the power efficiency of the voltage doubler remarkably. The efficiency can be improved by large-value off-chip flying capacitors[18]. However, this will increase the system volume dramatically for multi-stage charge pumps, which is unacceptable for implantable medical devices. Thirdly, the parasitic PNP transistors in the PMOS transistors (MP1 and MP2) will cause considerable leakage currents flowing into the P-type substrate when they are turned on, which may lower down the power efficiency, or even lead to failure in start-up of the charge pump. To deal with these issues, auxiliary circuits are employed in Refs. [19–21] to dynamically connect the substrate terminals of the PMOS transistors to a proper node with the highest voltage. However, these auxiliary circuits increase the chip area and will introduce extra parasitic capacitance, which reduces the efficiency of the charge pump.
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Figure1.
Conventional cross-coupled voltage doubler.
In this paper, a charge pump with cascaded cross-coupled voltage doublers in an N-type buried layer (NBL) isolated bipolar-CMOS-DMOS (BCD) technology (BCD) process is presented. Taking advantage of the structures of PMOS and NMOS transistors in the NBL-isolated BCD process, the proposed voltage doubler eliminates the issues of body effect and leakage currents by simply tying the body terminals of the NMOS and PMOS to other inherent terminals of the transistors. The simple circuit architecture leads to small parasitic capacitance, which improves the efficiency of the charge pump further. A charge pump consists of 5 cascaded stages of the proposed voltage doublers with on-chip flying capacitors implemented in a 0.35 μm BCD technology for implantable medical devices and achieves a maximum power efficiency of 72.6% at 40-μA load current.
The remainder of this paper is organized as follows. Section 2 provides an analysis of the factors that influence the efficiency of the conventional cross-coupled voltage doubler. Section 3 describes the architecture of the proposed charge pump. Measurement results are given in Section 4. Finally, Section 5 concludes this paper.
2.
Analysis of conventional voltage doubler
The factors that influence the performances of the conventional cross-coupled voltage doubler in Fig. 1 are analyzed in this section, including the body effect of the NMOS pair, the parasitic capacitance and the leakage currents in the PMOS pair. All the circuit examples in this section are designed in a 0.35-μm standard CMOS technology without isolation.
2.1
Influence of the body effect of the NMOS pair
As shown in Fig. 1, the flying capacitors, C1 and C2, are charged to VDD alternatively under the control of the cross-coupled NMOS transistors, MN1 and MN2, respectively. Hence, the voltages at node A and node B will toggle between VDD and 2VDD. Therefore, the gate source voltages of MN1 and MN2 are about VDD when they are on. As long as the threshold voltage (VTH) of MN1 and MN2 is less than VDD, the input voltage can be passed onto the capacitors without loss and high efficiency can be obtained. However, for a charge pump built by cascading multiple stages of the voltage doubler, the source voltages of the NMOS transistors will increase along the stages and can be expressed as:
$${V_{{ m{S,}}n}} approx n{V_{{ m DD}}},$$  | (1) |
where VS,n is the source voltage of the NMOS transistors in the nth stage. Considering the body effect, the VTH of an NMOS transistor can be expressed as
$${V_{{ m{TH}}}} = {V_{{ m{TH0}}}} + gamma left( {sqrt {2{varPhi _{ m{F}}} + {V_{{ m SB}}}} - sqrt {2{varPhi _{ m{F}}}} } ight),$$  | (2) |
where VSB is the source-bulk voltage, 2ФF is the surface potential, γ is the body effect parameter and VTH0 is the threshold voltage when VSB = 0. For standard CMOS technology, the bulk nodes of NMOS transistors are always connected to ground. Obviously, VTH of the NMOS transistors in the top stages is possible to exceed VDD because of their high VSB values, which will cause voltage loss and reduce the efficiency remarkably.
2.2
Influence of the parasitic capacitance
The parasitic capacitance at the internal nodes (A and B) imposes remarkable influence on the efficiency of the voltage doubler[17, 19], as shown in Fig. 2. The equivalent resistance of the structure can be expressed as
$${R_{ m{S}}} = frac{1}{{2{f_{{ m{CLK}}}}C}},$$  | (3) |
where fCLK is the frequency of the clock signal, CLK. There is a factor of 2 in Eq. (3) because the two capacitors pump charge to the load alternatively, which reduce the effective resistance by a factor of 2[19]. Because of the charge distribution caused by the parasitic capacitance, the output voltage can be expressed as
$${V_{{ m{OUT}}}} = (n + 1) {V_{{ m{DD}}}}frac{C}{{C + {C_{{ m{par}}}}}} - n {R_{ m{S}}}{I_{ m{L}}},$$  | (4) |
where n is the number of voltage doubler stages cascaded in the charge pump.
Fig. 3 plots the simulated efficiency of a single-stage charge pump as a function of IL under different values of α. As can be seen, the parasitic capacitance has a significant influence on the efficiency of the charge pump. The maximum efficiency can be close to 1 for α = 0.001. However, this can only be achieved for charge-pumps with off-chip large-value flying capacitors, which would lead to unacceptable system volume for implantable medical devices. For on-chip flying capacitors, α is in the range of 0.01–0.1, which limits the achievable efficiency of the charge pumps.
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Figure3.
Simulated efficiency of a single-stage voltage doubler as a function of the load current with different parasitic capacitance values.
2.3
Influence of the PMOS leakage current
The leakage currents caused by the parasitic PNP transistors of the PMOS serial switches (MP1 and MP2) are often overlooked in the cross-coupled voltage doubler because the parasitic PNP transistors are often not included in the simulation models of most CMOS technologies. However, these leakage currents will lead to start-up problems and lower the efficiency of the charge pump when the load current is large. Unfortunately, very little analysis about the influence of the leakage current can be found in the literature.
For a typical PMOS transistor implemented in the N-well of the standard CMOS technology shown in Fig. 4(a), 3 intrinsic PNP parasitic transistors exist in the structure, as shown in Fig. 4(b). In regular applications, the substrate (node B) always has the highest voltage among all the 4 nodes, and the 3 parasitic PNP transistors are always off. However, for the PMOS in the cross-coupled voltage doubler, Q2 will be turned on in some situations, which would lead to considerable leakage currents in the structure. Taking MP1 in Fig. 2 for example, when node A is switched to high state (node B is low) by the clock signals, MP1 is turned on and the charge stored in C1 is transferred to CL through MP1. In this situation, Q1 is shorted by the channel of the PMOS, and Q3 is simplified to a diode because the bulk node and source node of MP1 are tied together. Therefore, the equivalent circuit for MP1 in on state can be shown as that given in Fig. 4(c). Obviously, Q2 will be turned on as long as the voltage at node A, VA, is higher than Vout by about 0.7 V. This situation actually happens in the startup process of the voltage doubler, in which Vout increases gradually from ground because of the large load capacitor, CL, while VA may exceed Vout by a value of about VDD when MP1 is on. If the load current IL = 0, VA is always lower than or equal to VOUT after VOUT settles to its final value. However, VOUT in steady state deceases when IL increases. Therefore, Q2 will be turned on when the difference between VA and Vout is larger than 0.7 V.
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Figure4.
(a) Cross section of a PMOS in standard CMOS process. (b) Parasitic BJTs in the PMOS transistor. (c) Equivalent circuit of MP1 for the voltage doubler in Fig. 2.
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Figure2.
Cross-coupled voltage doubles with parasitic capacitance.
The leakage current, Ileak can be expressed roughly as a function of VOUT and VA:
$${I_{{ m leak}}}(t) = beta {I_{{ m{B0}}}}exp left[ {frac{{{V_{ m{A}}}(t) - {V_{{ m{OUT}}}}(t)}}{{{V_{ m{T}}}}}} ight],$$  | (5) |
where IB0 is the saturation current of the base–emitter junction of Q2,β is the current gain factor of Q2 and VT is the thermal voltage. Normally, β is quite small for the parasitic PNP transistors.
The leakage current will reduce the output voltage of the charge pump, and Eq. (4) can be rewritten as
$${V_{{ m{OUT}}}} = frac{{(n + 1){V_{{ m{DD}}}}C}}{{C + {C_{{ m{par}}}}}} - frac{n}{C} int_0^T {{I_{{ m leak}}}(t)} { m d}t - n {R_{ m{S}}}{I_{ m{L}}},$$  | (6) |
where T is the period of the clock signal. Fig. 5 compares the simulated Vout curves for the single-stage charge pump with and without PMOS leakage current. As expected, when IL is small (20 μA), the leakage current only increases the startup time slightly. When IL become larger (100 μA), evident reduction in VOUT can be observed after settling because of the leakage current. The charge pump even fails to start-up because of the leakage current when IL increases to 120 μA.
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Figure5.
(Color?online)?Simulated VOUT waveforms for the single-stage voltage doubler with and without the parasitic PNP model. fLCK = 1 MHz, C = 56 pF, VDD = 2 V, a = 0.02, and n = 1.
Moreover, the energy loss also increases because of the leakage current:
$${E_{ m{S}}} = 2n{C_{{ m{par}}}}V_{{ m{DD}}}^{ m{2}} + frac{{2n{{left( {int_0^T {{I_{{ m leak}}}(t)} { m d}t} ight)}^2}}}{C} + nfrac{{I_{ m{L}}^2{R_{ m S}}}}{{{f_{{ m{CLK}}}}}}.$$  | (7) |
Therefore, the power efficiency will be reduced remarkably by the leakage current for applications with a large load current. The exact calculation of the reduction in power efficiency caused by the leakage current is difficult, because the parameters of the parasitic PNP transistor depend heavily on the process. Fig. 6 compares the simulated power efficiency for the single-stage charge pump with and without the parasitic PNP transistors. As can be seen, the power efficiency drops remarkably for large load currents because of the leakage current caused by the parasitic PNP in the PMOS transistors.
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Figure6.
(Color?online)?Simulate power efficiency as a function of IL for the single-stage voltage doubler with and without the parasitic PNP models.
Many structures have been developed to solve the problem of PMOS leakage current. The voltage doubler with an auxiliary charge pump in Ref. [19] is a very effective and widely used architecture as shown in Fig. 7, in which a cross-coupled PMOS pair, MP3 and MP4, and an additional load capacitor CA are used as the auxiliary charge pump to bias the bulk nodes of MP2 and MP3. The leakage problem can then be solved because the auxiliary charge pump has no current load, and its output voltage is near 2VDD. However, the added structure reduces the achievable efficiency because it increases the parasitic capacitance. The architectures in Refs. [20, 21] also have the same problem of increased parasitic capacitance.
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Figure7.
(Color?online)?Voltage doubler with auxiliary circuit to avoid leakage[19].
3.
Proposed charge pump in isolated BCD technology
3.1
Structures of MOSFETs in isolated BCD technology
BCD processes are widely adopted to develop ICs for bio-medical devices because they provide various components including low-voltage CMOS, high-voltage CMOS, LDMOS and bipolar transistors in a single chip with relatively low cost, which facilitates the design of a multifunction IC. More importantly, isolation techniques employed in BCD processes ensure high performances for the circuits and reduce leakage currents significantly.
The cross-sections of the low-voltage PMOS and NMOS in the NBL-isolated BCD process adopted in this paper are shown in Figs. 8(a) and 8(b), respectively. The process includes an NBL within a p-epitaxy layer on a p-type substrate, therefore can provide good isolation for each transistor. Different from the standard CMOS process, NMOS in the isolated process has 6 ports (G, D, S, B, ISO and SUB), and PMOS has 7 ports (G, D, S, B, ISO, inside substrate (ISUB) and SUB), as given in Fig. 8(c). The extra ports are used to avoid latch-up and leakage. Obviously, the SUB terminals must be connected to the lowest voltage and the voltage of ISO must be equal to or larger than that of the SUB to avoid forward biasing of the diodes.
As can be seen, the architecture of the NBL-isolated PMOS is very different to that of the PMOS in standard CMOS technology in Fig. 4(a). The ISUB terminal can be connected to nodes other than ground to avoid the leakage problem. On the other hand, the architecture of the NBL-isolated NMOS is similar to the NMOS in the CMOS technology with deep N-well[17, 20, 21]. However, the NBL to P-SUB diode in the isolated BCD technology can stand higher voltage (several tens of volts) with proper widths of the ISO strips, which provide the possibility to realize high-voltage charge-pumps with many cascaded voltage doublers.
3.2
Schematic of the proposed voltage doubler
Based on the structure of the isolated NMOS and PMOS, the schematic of the proposed cross-coupled voltage doubler is given in Fig. 9. The basic structure is similar to that shown in Fig. 1; the main differences are the connections of the internal nodes of the NBL-isolated MOSFETs.
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Figure9.
Proposed voltage doubler in the NBL-isolated BCD technology.
As shown in Fig. 9, the body nodes (B) of the NMOS pair, NM1 and NM2, are connected to the source nodes to eliminate possible voltage loss caused by the body effect in charge pumps with multiple cascaded stages, while the ISO nodes are connected to the drain nodes, respectively, to realize reverse bias for the relevant diodes. For clarity, the structure including parasitic devices of the NMOS is given in Fig. 10(a). Besides the 2 conventional diodes between the source/drain nodes and the body nodes (D1 and D2), 2 additional parasitic diodes D3 and D4 are included to demonstrate the isolation function of the NBL layer. Also taking MN1 in Fig. 9 as example, its equivalent circuit including the parasitic devices is shown in Fig. 10(b), in which D1 is neglected because the B and S nodes are tied together. In normal operation, when VA is turned to low state (VB is high), MN1 is on and C1 is charged by VDD through MN1. Obviously, D2 and D3 help to improve the conductance of MN1. On the other hand, when VA is high and VB is low, MN1 is turned to off state, in which D2 and D3 provide additional isolation between VDD and VA. The ISO-PSUB diode, D4, can be designed with proper width for the ISO stripe to stand high reverse bias voltage for high-voltage charge pumps with multiple stages of the voltage doubler. However, this will increase the parasitic capacitance at node A (and node B) which would result in reduction of the power efficiency. In this paper, 5 stages of the voltage doubler are cascaded to provide an output voltage from 7 to about 12 V. Based on the design rules of the technology, only the top 2 stages need to be designed with relatively wider ISO stripes.
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Figure10.
(a) Parasitic devices in the NBL-isolated NMOS transistor. (b) Equivalent circuit of MN1 for the voltage doubler in Fig. 9.
The connections for the internal nodes of the PMOS pair are dedicated to avoiding the possible leakage current of the charge pump implemented in standard CMOS technology. Based on the cross-section in Fig. 8(a), the structure of the isolated PMOS transistor with parasitic devices is shown in Fig. 11(a). As can be seen, if the ISUB node is connected to ground, the structure would be the same as the standard PMOS in Fig. 4(b) and have the same problem of leakage current. In order to avoid leakage currents with simple circuit structure, the B, S, ISUB and ISO nodes of each PMOS are all tied together, respectively, as shown in Fig. 9.
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Figure11.
(a) Parasitic devices in the NBL-isolated PMOS transistor. (b) Equivalent circuit of MP1 for the voltage doubler in Fig. 9.
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Figure8.
(Color?online)?Structures of MOSFETs in the NBL-isolated technology used in this paper: (a) cross-section of PMOS, (b) cross-section of NMOS, (c) symbols for PMOS and NMOS.
The equivalent circuit of MP1 with the parasitic devices is shown in Fig. 11(b) as an example. Again, Q1 in Fig. 11(a) is neglected because it is shorted by the PMOS channel when it is on. D3 and Q3 are also eliminated because the B, S, ISUB and ISO nodes are shorted together. Therefore, only Q2 and D4 remain in the structure. As analyzed in the standard PMOS case, when the charge pump operates in the start-up process or in steady state with large load current, Q2 would be turned on if VOUT is less than VA by about 0.7 V. However, the current in Q2 can only flow to the output node because the node ISUB is connected to node D. Therefore, the leakage problem is readily solved by simple connections of the internal nodes of the PMOS. The ISO to P-SUB diode, D4, always operates with reverse bias and provides the necessary isolation between VOUT and ground. Similarly, with the NMOS, D4 is also required to stand the maximum voltage of the charge pump. This can be easily realized with proper width of the ISO stripes for the PMOS transistors in the top stages.
Taking advantage of the characteristics of the NBL-isolated BCD technology, the proposed voltage doubler solves the leakage current and body effect problems with simpler circuit structure than those in Refs. [19–21] The simple structure eliminates the parasitic capacitance that resulted from the auxiliary circuits and wires. Therefore, it has the potential to achieve the high efficiency and low area requirements for implantable biomedical applications.
3.3
Overall structure of the charge pump
The charge pump is designed to provide an output voltage of over 7 V with a current load range of 0–100 μA under a 2-V supply voltage for implantable medical devices such as the cardiac pacemaker. Because the charge pump is mainly used to generate the control clock signals for the pulse stimulator, there is no need for precise control of the charge pump’s output voltage. Therefore, five stages of the proposed voltage doubler are cascaded to realize the open-loop charge pump, as shown in Fig. 12. A classic clock generator is also employed to provide two-phase non-overlapping driving clock signals (CLK1 and CLK2) from an input clock signal (CLK) with frequency of 1 MHz.
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Figure12.
Overall structure of the charge pump.
Based on the possible range of the load current and the clock frequency, the flying capacitors in each stage are designed with a value of 56 pF from calculation and simulation to achieve high efficiency in the required load current range. High density metal-insulator-metal (MIM) capacitor (about 1.86 fF/μm2) is employed for the flying capacitors to realize small bottom-plate parasitic capacitance. From post-layout parasitic parameter extraction, the parasitic capacitance factor, α, is about 0.03 (i.e. Cpar = 0.03C).
4.
Measurement results
The proposed charge pump is fabricated in the Dongbu 0.35-μm NBL-isolated BCD process and has an area of 350 × 1600 μm2, with the die photo given in Fig. 13. The circuit detail is not displayed clearly in the micrograph because of the automatically inserted dummy top metal made by the foundry.
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Figure13.
Die photo of the proposed charge pump.
The output waveform of the charge pump given in Fig. 14 is measured under a supply voltage of 2 V, an input clock frequency of 1 MHz, an off-chip load capacitor of 2.2 nF and a current load of 20 μA, which shows that the output amplitude of the proposed charge pump reaches above 10.57 V in about 0.5 ms with ripple lower than 10 mV. Because the stimulate pulse’s magnitude in a pacemaker is usually lower than 7 V, the charge pump’s output voltage is enough to generate the control signals for the pulse stimulator.
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Figure14.
Measured output voltage waveform of the charge pump (VDD = 2 V, IL = 20 μA, CL = 2.2 nF, fCLK =1 MHz).
The measured output voltages at different current load are given in Fig. 15. The calculated results according to Eq. (4) are also shown in Fig. 15 for comparison. As can be seen, the measured values are a little lower than the calculated values, which may result from the fact that the actual parasitic capacitance is larger than the extracted values from the layout. The output voltage of the charge pump is about 11.5 V with zero current load and is reduced to about 7.1 V at a current load of 100 μA.
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Figure15.
(Color?online)?Measured output voltage as a function of load current.
The measured power efficiency of the charge pump is obtained from the following equation[17]:
$$eta = frac{{{V_{{ m{OUT}}}}{I_{ m{L}}}}}{{{V_{{ m{bat}}}}{I_{{ m{bat}}}}}},$$  | (8) |
where Vbat and Ibat are the output voltage of and current from the power supply, respectively. Fig. 16 plots the measured power efficiency of the proposed charge pump as a function of the current load with comparison to the calculated results. As can be seen, the measured power efficiency is also a little lower than the calculated efficiency because the actual parasitic capacitance is larger than the extracted values. The measured maximum efficiency is about 72.6% at a current load of 40 μA and is reduced to about 57.2% at a current load of 100 μA.
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Figure16.
(Color?online)?Measured power efficiency as a function of load current.
The performances of the proposed charge pump are summarized in Table 1, with comparison to other works. As can be seen, the proposed charge pump achieves a relatively high efficiency with on-chip flying capacitors because it has a simple circuit structure with low parasitic capacitance.
| Parameter | Ref. [17] | Ref. [18] | Ref. [19] | Ref. [20] | Ref. [21] | This work |
| Technology (μm) | 0.18-CMOS (with deep N-well) | 0.8 HV-CMOS | 0.7 CMOS | 0.35 BCD | 0.13-CMOS (with deep N-well) | 0.35 BCD |
| Area (mm2) | – | 4.4* | 0.15 | – | 0.066 | 0.56 |
| Clock freq. (MHz) | 100 | 0.033 | 10 | 10 | 0.25 | 1 |
| Flying capacitance | On-chip 2.5 pF | Off-chip 0.47 μF | On-chip 100 pF (MOS) | On-chip 10 pF (MOS) | Off-chip 10 nF | On-chip 56 pF (MIM) |
| Supply voltage (V) | 1.8 | 2.5 | 3 | 3.7 | 0.18 | 2 |
| Number of stages | 5 | 3 | 1 | 36 | 3 | 5 |
| Output voltage (V) | 10.1 (@IL = 0 ) | 9.06 (@IL = 100 μA) | 5.9 (@IL = 0) | 105 (@IL = 100 μA) | 0.619 (@IL = 0) | 11.5 (@IL = 0) |
| Max. power eff. (%) | 50 | 90.6 | 75 | 39** | 34 | 72.6 |
| IOUT @ Max. eff. (μA) | 350 | 100 | – | 100 | 21 | 40 |
| * Overall area including 2 charge pumps and other system level blocks. ** Simulation results. | ||||||
Table1.
Performance summary and comparison.
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| Parameter | Ref. [17] | Ref. [18] | Ref. [19] | Ref. [20] | Ref. [21] | This work |
| Technology (μm) | 0.18-CMOS (with deep N-well) | 0.8 HV-CMOS | 0.7 CMOS | 0.35 BCD | 0.13-CMOS (with deep N-well) | 0.35 BCD |
| Area (mm2) | – | 4.4* | 0.15 | – | 0.066 | 0.56 |
| Clock freq. (MHz) | 100 | 0.033 | 10 | 10 | 0.25 | 1 |
| Flying capacitance | On-chip 2.5 pF | Off-chip 0.47 μF | On-chip 100 pF (MOS) | On-chip 10 pF (MOS) | Off-chip 10 nF | On-chip 56 pF (MIM) |
| Supply voltage (V) | 1.8 | 2.5 | 3 | 3.7 | 0.18 | 2 |
| Number of stages | 5 | 3 | 1 | 36 | 3 | 5 |
| Output voltage (V) | 10.1 (@IL = 0 ) | 9.06 (@IL = 100 μA) | 5.9 (@IL = 0) | 105 (@IL = 100 μA) | 0.619 (@IL = 0) | 11.5 (@IL = 0) |
| Max. power eff. (%) | 50 | 90.6 | 75 | 39** | 34 | 72.6 |
| IOUT @ Max. eff. (μA) | 350 | 100 | – | 100 | 21 | 40 |
| * Overall area including 2 charge pumps and other system level blocks. ** Simulation results. | ||||||
5.
Conclusion
This paper demonstrates a charge pump composed of 5 cascaded cross-coupled voltage doublers based on the NBL-isolated BCD process. Taking advantage of the isolated structure of the transistors, the proposed voltage doubler solves the issues of leakage currents in PMOS and the body effect in NMOS by simply connecting their body terminals to other proper terminals. Complex auxiliary circuits in conventional structures are then no longer needed. Fabricated in a 0.35-μm NBL-isolated BCD process, the charge pump achieves a maximum power efficiency of 72.6% at a current load of μA, which is suitable for applications in implantable medical devices.
