A 0.9 V PSRR improved voltage reference using a wide-band cascaded current mode differentiator

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1.
Introduction

For many applications such as wireless medical devices and sensors, the optimized PSRR performance of the reference is demanded in the ultra low power and voltage system. Unfortunately, the reference’s PSRR performance^[1–7] would be easily degraded because of the coupling high frequency noise on the power supply line.

Conventionally, the improving approaches are: (1) designing the internal cascaded regulator to isolate the supply noise^[8–11]; (2) implementing the feed forward current mode compensation path^[12–14]. The first approach should significantly improve the PSRR performance at the high frequency range. However, the internal regulator would consume the supply voltage drop and much more power dissipation. To optimize the power and supply voltage performances, the second approach is presented. The topology would improve the PSRR performance with the limited power. However, since the current mode feed forward path is designed with the micro internal feedback loop, the feedback loop would still cost the considerable supply voltage drop and power dissipation. So the technique is not applicable in the reference with the ultra low power and supply voltage.

This paper presents a wide-band cascaded current mode differentiator. It is able to optimize the reference’s PSRR performance at the high frequency range, with the ultra low power and supply voltage. The paper is organized as follows. The previous architectures are analyzed in Section 2. The proposed reference implementation is described in Section 3. The experimental results are presented in Section 4. The conclusions are drawn in Section 5.

2.
Conventional approaches

The conventional approach of designing the internal regulator is shown in Fig. 1(a). The regulator and the voltage reference constitute the cascaded topology, so as to improve the PSRR performance of the reference. Although the corresponding high frequency noise can be improved to some extent (with the regulator’s PSRR bandwidth much larger than the reference’s), the regulator would dissipate much more power. On the other hand, the reference would cost the extra dropout voltage (as shown in Fig. 1(a)), so the technique is not applicable in the reference with the ultra low power and supply voltage.

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Figure1.
(a) The typical reference with the cascaded topology. (b) The reference with the current mode feedforward path.

To improve the reference’s power performance, another conventional approach is shown in Fig. 1(b). It is designed with the current mode feed forward path and the voltage reference. To prevent the current mode signal transfer degradation, the two stages’ micro feedback loop on the path is designed, as shown in Fig. 1(b). However, for the improvement of the input impedance’s performance, the considerable power has to be dissipated to increase the stages’ transconductance. Moreover, in the micro feedback loop, the extra voltage (as shown in Fig. 1(b)) has to be cost to satisfy the minimum overdrive voltage of the transistors M_{1, 2}.

3.
The proposed reference with the wide-band cascaded current mode differentiator

Based on the above analysis of the previous topology, the improved PSRR reference with the ultra low supply voltage is given. Firstly, the topology and corresponding supply noise signal transfer functions of the proposed reference’s respective blocks would be presented. Then the model of the reference is set up and the PSRR performance is analyzed. Finally, with the topology of the reference, the minimum supply voltage is evaluated.

3.1
The topology implementation and supply line noise signal process of the conventional voltage reference

Fig. 2 shows the voltage reference’s conventional blocks: the current reference generator is constituted by the devices M_{1, 2}, C, R_1–3 and M_{4, 5}. The error amplifier EA (as shown in Fig. 2) is used to calibrate the error signal of the generator. Devices C₁, M₃ and R₄ constitute the voltage reference generator.

According to the topology, the noise on the supply line is processed in steps through the following parts (the red dotted line): the supply line’s noise transferring circuit (analyzed in the following passage), the current reference generator, the error amplifier and the voltage reference generator, as shown in Fig. 2.

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Figure2.
The topology of the proposed reference’s core.

Specifically, as shown in Fig. 3(a), the supply line’s noise transferring circuit is mainly constituted by the transistors M_{6, 7} of the error amplifier and the capacitor C. It converts the noise into the voltage input signal of the current generator. The topology of the current reference generator, the error amplifier and the voltage reference generator is shown in Figs. 3(b)–3(d).

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Figure3.
(a) The supply voltage noise transferring circuit. (b) The current generator. (c) The error amplifier. (d) The voltage generator.

With the topology of the respective blocks, the transfer functions of the corresponding blocks in voltage mode should be expressed as follows.

The supply line’s noise transferring circuit:

$$H(s) = 1 - bigg[ {{g_{text{m}}}{r_{{text{out}}}}/({g_{text{m}}}{r_{{text{out}}}} + 1) cdot 1/left[ {1 + left(s/omega
ight)}
ight]} bigg].$$

(1)

The error amplifier:

$$G(s) = {g_{
m{m}}}{r_{{
m{out}}}}/[1 + (s/omega )].$$

(2)

The current generator:

$${G_1} = {G_{{
m{negative}} {text {-}} {
m{feedback}}}} - {G_{{
m{positive}}{text {-}} {
m{feedback}}}}.$$

(3)

The voltage generator:

$${G_2}(s) = {g_{{
m{m}}2}}{r_{{
m{out}}2}}/[1 + (s/{omega _2})],$$

(4)

where ω is the low-pass cutoff frequency of the amplifier and $omega = {1 / {{r_{
m {out}}}C}}$

; ω₂ is the low-pass cut off frequency of the voltage generator and ${omega _2} = {1 / {{r_{
m {out2}}}{C_2}}}$

. g_m and r_out are the transconductance and the output resistance of the error amplifier; g_m2 and r_out2 are the trans conductance and equivalent output resistance of the voltage generator. G_{positive–feedback} and G_{negative–feedback} are the reference’s positive and negative feedback coefficients.

3.2
The topology implementation and the supply line noise signal process of the proposed differentiator

With regards to the proposed technique’s circuit implementation, in order to work with the ultra low supply voltage, the PSRR improved technique is characterized by the wide-band current mode signal processing stages differentiator, as shown in Fig. 4. The wide-band characteristic is achieved by the two cascaded stages. The first stage senses the high frequency supply voltage noise, while the second stage transfers it to the input of the current generator. Specially, the second stage is designed to generate a zero, which is able to cancel the dominant pole of the first stage.

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Figure4.
An illustration of the proposed differentiator.

In the differentiator, the transistors M_14–17 and the capacitor C_comp1 constitute the first stage of the path, as shown in Fig. 4. The transistors M_{20, 21} form the simple feedback loops with the gate and drain nodes’ shorted^[11]. The capacitor C_comp1 senses the power supply noise, and translates it into the current mode signal I. Accordingly, the DC input impedance of the nodes A and B in the first stage should be expressed as follows:

$${R_{{
m{in}}}} = frac{1}{{{g_{{
m{mp}}}}}},$$

(5)

where g_mp is the transconductance of the transistors M_{20, 21}, respectively.

However, as shown in Fig. 5, with the frequency increasing, the current I should be seriously degraded by the dominant pole ω_p of M₂₀’s simple feedback loop. Consequentially, the performance of the differentiation would become poor with the frequency increasing beyond ω_p.

To overcome the drawback, the second stage (the OTA G_m) with the extra zero characteristic is designed, as shown in Fig. 5: the resistor R_c, the capacitor C_z and the transistor M₁₂ constitute the high-pass filter, which provides the zero ω_z.

The corresponding equivalent circuit is also illustrated in Fig. 5: transistor M₂ and M₅ can be seen as the micro amp A₁, A₂, respectively. Specifically, the design of the transistors’ size is as follows:

$$begin{split}{left(frac{W}{L}
ight)_{{
m{M}}16}} = {left(frac{W}{L}
ight)_{{
m{M}}17}} = {left(frac{W}{L}
ight)_{{
m{M}}10}} = {left(frac{W}{L}
ight)_{{
m{M}}11}};{left(frac{W}{L}
ight)_{{
m{M}}12}} = {left(frac{W}{L}
ight)_{{
m{M}}13}};,,, {left(frac{W}{L}
ight)_{{
m{M}}12}} = {left(frac{W}{L}
ight)_{{
m{M}}13}}.end{split}$$

(6)

The current mode output signal of the cascaded stages should be calculated as follows:

$$I(s) + Delta I(s) = frac{{(1 + s/{omega _{
m{z}}})}}{{(1 + s/{omega _{
m{p}}})}}{I_{{
m{ideal}} {text {-}} {
m{highpass}}}}(s),$$

(7)

where

$${I_{{
m{ideal}} - {
m{highpass}}}}(s) = - frac{{{V_{{
m{dd}}}}}}{{1/{C_{{
m{comp}}1}}s}};$$

$${omega _{
m{z}}} = frac{1}{{{R_{
m{c}}}{C_{
m{z}}}}};;;{omega _{
m{p}}} = frac{{{g_{{
m{mn}}}}}}{{{C_{{
m{comp}}1}}}}.$$

where g_mn is the trans-conductance of the transistors M_{16, 17}; and V_dd is the variation of the supply voltage. So, the degraded I(s) could be compensated by ΔI(s), which is generated by ω_z.

Based on the characteristics above, with the proper value of the R_c and C_z (R_c = 300 kΩ, C_z = 100 fF), the dominant pole ω_p should be canceled by the zero ω_z, as shown in Fig. 5’s bode diagram. So, the output signal should be simplified as follows:

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Figure5.
(Color?online) An illustration of the signal processing in the differentiator.

$$I(s) + Delta I(s) = {I_{{
m{ideal}} {text {-}} {
m{highpass}}}}(s).$$

(8)

Therefore, with the special OTA G_m, the PSRR performance should be optimized without the conventional micro feedback loop. And the output signal can be approximately expressed as follows:

$$I(s) + Delta I(s) = - frac{{{V_{{
m{dd}}}}}}{{1/{C_{{
m{comp}}1}}s}}.$$

(9)

3.3
Analysis of the proposed reference’s PSRR signal processing

With the topology of the reference blocks and the corresponding analysis, the illustration of the reference signal processing in voltage mode is given in Fig. 6: the V_GS of the transistors M_{1, 2, 3} can be seen as the input voltage of the feedback loop of the conventional reference (the signal process has been analyzed in Section 3.1); and the output current of the differentiator is translated into the compensating voltage of the V_GS of the transistors M_{1, 2, 3}. So the V_GS can be maintained to be the constant value. Therefore, the proposed reference’s PSRR transfer function should be characterized as follows:

$${
m {PSRR}} = [H(s) + {H_{
m{d}}}(s)]frac{{{G_2}(s)}}{{{G_1}G(s) + 1}},$$

(10)

where H_d(s) is the differentiator’s transfer function in voltage mode. Combined with Eq. (9), H_d(s) should be as follows:

$${H_{
m{d}}}(s) = - {r_{{
m{out}}}}{C_{{
m{comp}}1}}s/[1 + (s/omega )].$$

(11)

So, Eq. (11) could be modified to be:

$${H_{
m{d}}}(s) approx - {r_{{
m{out}}}}{C_{{
m{comp}}1}}s/[1 + (s/omega )] cdot {g_{
m{m}}}{r_{{
m{out}}}}/({g_{
m{m}}}{r_{{
m{out}}}} + 1).!!!$$

According to Eq. (1), the PSRR performance should be expressed as follows:

$$begin{split} & begin{array}{*{20}{l}} {{text{PSRR}} = left[ {1 - left[ {left[ {{g_{text{m}}}{r_{{text{out}}}}/left( {{g_{text{m}}}{r_{{text{out}}}} + 1}
ight) cdot 1/left[ {1 + (s/{r_{{text{out}}}}C)}
ight]}
ight.}
ight.}
ight.} {left. {left. { -,, {g_{text{m}}}{r_{{text{out}}}}/left( {{g_{text{m}}}{r_{{text{out}}}} + 1}
ight) cdot {r_{{text{out}}}}{C_{{text{comp}}1}}s/left[ {1 + left( {s/{r_{{text{out}}}}C}
ight)}
ight]}
ight]}
ight]} end{array}!!!!!!!!!!!!!!!!!!! & times frac{{{G_2}(s)}}{{{G_1}G(s) + 1}}.end{split} $$

(12)

Thus, with the value of the capacitor C_comp1 designed to be equivalent to the feedback loop’s capacitor C, the dominant pole ω_p can be canceled by the zero ω_z (as shown in Fig. 6), the PSRR performance of the reference should be approximately expressed as follows:

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Figure6.
(Color?online) The illustration of the reference signal processing.

$${
m {PSRR}} approx frac{1}{{{g_{
m{m}}}{r_{{
m{out}}}} + 1}}frac{{{G_2}(s)}}{{{G_1}G(s) + 1}}.$$

(13)

Furthermore, combined with Eqs. (2) and (4), with the characteristic of ω = ω₂ (C = 1 pF, C₁ = 10 pF and C₁ is designed with the MOS capacitor), the PSRR performance of the reference can be derived into the equation as follows:

$${
m {PSRR}} approx frac{1}{{{g_{
m{m}}}{r_{{
m{out}}}} + 1}}frac{{{g_{{
m{m}}2}}{r_{{
m{out}}2}}}}{{{G_1}{g_{
m{m}}}{r_{{
m{out}}}} + 1}}.$$

(14)

3.4
The evaluation of the reference’s minimum supply voltage

The reference’s minimum supply voltage is limited by the reference’s current and voltage generators, the error amplifier and the proposed current mode differentiator.

According to the topology of the proposed reference, the minimum supply voltages of the above blocks should be expressed as follows:

The error amplifier:

$${V_{{
m{MIN}}_{
m{ERROR}}}} = {V_{{
m{GS}}_{
m{subthreshold}}}} + {V_{{
m{overdrive}}}}.$$

(15)

The current generator:

$${V_{{
m{MIN}}_{
m{CURRENT}}}} = {V_{{
m{GS}}_{
m{subthreshold}}}} + {V_{{
m{overdrive}}}}.$$

(16)

The voltage generator:

$${V_{{
m{MIN}}_{
m{VOLTAGE}}}} = {V_{{
m{ref}}}} + {V_{{
m{overdrive}}}}.$$

(17)

The proposed differentiator:

$${V_{{
m{MIN}}_{
m{DIF}}}} = {V_{{
m{GS}}_{
m{PMOS}}}} + {V_{{
m{overdrive}}}},$$

(18)

where V_{GS_subthreshold} is the gate to source voltage of the transistors M4, 5, 8, 9 operating in the subthreshold region^[15–17]; V_overdrive is the overdrive voltage of the NMOS and PMOS transistors; V_{GS_PMOS} is the gate to source voltage of the saturated PMOS transistor; and V_ref is the output reference voltage of the proposed reference. In the reference topology, the transistors M_{4, 5, 8, 9} are designed to be operating in the sub threshold region, while the others are in the saturated region. With the 0.18 μm CMOS process (V_{TH_NMOS} = 0.3 V, V_{TH_PMOS} = 0.4 V), the gate to source voltage V_{GS_NMOS} and V_{GS_PMOS} of the saturated NMOS and PMOS transistors are designed to be 0.5 and 0.6 V, respectively; meanwhile, in the proposed reference, the V_{GS_subthreshold} of the transistors M_{4, 5, 8, 9} is controlled to be 0.2 V, and the reference voltage V_ref is 0.3 V. Therefore, the reference’s minimum power supply should be improved to be V_{GS_PMOS} + V_overdrive = 0.8 V.

4.
Experimental results

The proposed reference is designed and fabricated with a 0.18 μm CMOS standard process. The prototype of the chip is shown in Fig. 7. The chip area is 193 × 396 μm², and the sizes of the key devices are summarized and shown in Table 1. The supply voltage for the measurement is 0.9 V.

Key device	Value	Key device	Value
M₄	5 μm/0.5 μm	M₁₆	15 μm/0.5 μm
M₅	20 μm/0.5 μm	M₁₇	15 μm/0.5 μm
M₁₀	15 μm/0.5 μm	C_comp	1 pF
M₁₁	15 μm/0.5 μm	C	1 pF
M₁₂	30 μm/0.5 μm	R_c	300 kΩ
M₁₃	30 μm/0.5 μm	C_z	100 fF

Table1.
The sizes of the key devices

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Key device	Value	Key device	Value
M₄	5 μm/0.5 μm	M₁₆	15 μm/0.5 μm
M₅	20 μm/0.5 μm	M₁₇	15 μm/0.5 μm
M₁₀	15 μm/0.5 μm	C_comp	1 pF
M₁₁	15 μm/0.5 μm	C	1 pF
M₁₂	30 μm/0.5 μm	R_c	300 kΩ
M₁₃	30 μm/0.5 μm	C_z	100 fF

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Figure7.
(Color?online) The prototype of the proposed reference. 1: The voltage reference. 2: The proposed differentiator.

4.1
Measurement of the PSRR characteristic

On the issue of the PSRR performance, the output voltage of the reference is analyzed by the Agilent Spectrum Analyzer, the frequency spectrum is shown in Fig. 8: with the supply noise 100 mV_p-p @ 20 MHz (~?15 dBm), the output noise at 20 MHz achieves at ~?69 dBm. So, the PSRR achieves at about ?54 dBm. With different frequencies of the supply noise, the PSRR with different frequencies is shown in Fig. 9.

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Figure8.
(Color?online) An illustration of the reference transient response at the supply noise 20 MHz.

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Figure9.
(Color?online) An illustration of the reference PSRR performance.

4.2
Measurement of the quiescent power and temperature irrelevant output voltage

The performance of the temperature irrelevant output voltage is evaluated across the temperature range (?20 to 80 °C). As shown in Fig. 10, the variation of the voltage is maintained within 9 ppm/°C. With regards of the quiescent power as shown in Fig. 11, the power at the worst case is less than 19 μW with the temperature (?20 to 80 °C).

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Figure10.
(Color?online) The characteristics of temperature irrelevant voltage.

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Figure11.
(Color?online) The measurement of the reference quiescent power.

4.3
Comparison and discussions

The comparison with the previous works and products is concluded in Table 2. In Table 2, the PSRR at the high frequency range (or the other parameters such as supply voltage and power dissipation) of the previous works is considerable. In this work, with the technique, the PSRR is optimized with the ultra low supply voltage 0.9 V, and the power dissipation is less than the others.

Parameter	Process technology (μm)	Supply voltage (V)	Power (μW)	PSRR (dB)
Ref. [1]	0.35	0.9	/	?40 @ 10 MHz
Ref. [4]	0.35	3	24	/
Ref. [8]	0.18	3.3	252	?90 @ 10 MHz
Ref. [10]	0.35	3.3	/	?30 @ 1 MHz
Ref. [14]	0.35	3.3	40	?54 @ 20 MHz
Ref. [16]	0.18	1.8	/	?35 @ 10 MHz
Ref. [18]	0.18	2.5	0.5	?64 @ 1 kHz
This work	0.18	0.9	19	?54 @ 20 MHz

Table2.
Performance comparison.

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Parameter	Process technology (μm)	Supply voltage (V)	Power (μW)	PSRR (dB)
Ref. [1]	0.35	0.9	/	?40 @ 10 MHz
Ref. [4]	0.35	3	24	/
Ref. [8]	0.18	3.3	252	?90 @ 10 MHz
Ref. [10]	0.35	3.3	/	?30 @ 1 MHz
Ref. [14]	0.35	3.3	40	?54 @ 20 MHz
Ref. [16]	0.18	1.8	/	?35 @ 10 MHz
Ref. [18]	0.18	2.5	0.5	?64 @ 1 kHz
This work	0.18	0.9	19	?54 @ 20 MHz

5.
Conclusions

This paper presents a 0.9 V PSRR improved voltage reference with a wide-band cascaded current mode differentiator. With the analysis of the proposed reference, it could be derived that the PSRR at the high frequency range could be improved under the ultra low supply voltage. According to the experimental results, with the technique, the reference realizes the optimized PSRR at ?54 dB @ 20 MHz. So the reference realizes the optimized PSRR at the high frequency range with the ultra low supply voltage and power.