1.Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China 2.Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China 3.Spallation Neutron Source Science Center, Dongguan 523803, China 4.Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract: Based on the wide-spectrum neutron beam (covering thermal neutrons and E > 10 MeV neutrons, with maximum energy of 1.6 GeV) provided by the China Spallation Neutron Source (CSNS), this paper focuses on the single event effect study of 14 nm FinFET large-capacity SRAM and 65 nm planar process SRAM device, using combined techniques of irradiation experiment, reverse analysis, and Monte-Carlo neutron transport simulation. The aim is to reveal the effect of integrated circuit process changing on the sensitivity of neutron induced single-bit and multiple-bit upsets (MBU), and to analyze the inner mechanisms, including the distribution of secondary particles in the sensitive volume, the characteristics of deposited charges, etc. The results show that compared with the 65 nm device, single event upset (SEU) cross section of the 14 nm FinFET device, induced by E > 10 MeV neutrons, is reduced by about 40 times, while the MBU ratio increases from 2.2% to 7.6%, which is due to the reduction of sensitive volume size of the 14 nm FinFET device (80 nm × 30 nm × 45 nm), pitch, and critical charge (0.05 fC). The main forms of MBU are double-bit upset, triple-bit upset and quadruple-bit upset. Unlike the phenomenon that the 65 nm device is immune to thermal neutrons, the use of the 10B element near M0 in the 14 nm FinFET device causes it to present the thermal neutron sensitivity to a certain extent. The SEU cross section induced by thermal neutrons is about 4.8 times smaller than that induced by E > 10 MeV neutrons. Based on the device cross-section and memory area images obtained from the reverse analysis, a device model is established and neutron transport simulation based on Geant4 toolkit is carried out. The E > 10 MeV neutrons result in abundant secondary particle distribution in the sensitive volume of the device, covering n, p into even W. The neutron energy and presence or absence of the W plug near the sensitive volume have an importantinfluence on the type and probability of secondary particles in the sensitive volume. The analysis and calculations show that a large number of high-Z secondary particles with long range and large LET values generated by high-energy neutrons in the sensitive volume of the device are the inducement of MBU, and SEUs mainly result from the contribution of light ions such as p, He, and Si. Keywords:FinFET/ neutron/ single event upset/ nuclear reaction
单粒子效应测试系统具备对被测器件进行上电、写读、工作电流监测等功能. 开始辐照前, 将测试板安装在束流大厅的中子束线上(见图1), 操作人员在控制大厅通过网线控制测试板, 在被测器件中写入初始测试图形(棋盘格图形), 实时监测被测器件各路工作电流. 打开中子束流后, 持续对被测器件进行“读比”操作, 发现错误时, 测试系统会自动上报错误地址、错误数据等信息. 测试过程中, 所有被测器件均未观测到单粒子闩锁现象. 图 1 实验现场图(中子束流孔道位于测试板背后, 中子束流对准被测器件) Figure1. Experimental setup (neutron beam channel is loca-ted behind the test board, and aligned with the device under test).
使用SRIM软件[16,17]可以计算得到次级Li离子和He离子在硅器件中的LET值与能量的关系(如图5所示). 0.84 MeV的Li离子和1.47 MeV的He离子在硅器件中的LET值分别为2.10 MeV·cm2·mg–1和1.15 MeV·cm2·mg–1. 图6给出了本文使用的14 nm FinFET SRAM的重离子实验结果, 通过Weibull曲线拟合得到该款器件SEU的LET阈值为0.1 MeV·cm2·mg–1. 可见, 热中子与10B元素相互作用产生的次级Li离子和He离子可以在14 nm FinFET SRAM中引起SEU. 图 5 (a) Li离子和(b) He离子在硅材料中的LET值与能量的关系 Figure5. Relationship between LET value and energy of (a) Li ion and (b) He ion in silicon material.
图 6 14 nm FinFET SRAM的重离子实验结果 Figure6. Heavy ion experiment results of 14 nm FinFET SRAM.
对65 nm平面工艺器件开展二次离子质谱(secondary ion mass spectroscopy, SIMS)测量和分析, 未在器件中发现10B元素成分, 该结果解释了上述“65 nm平面工艺器件对热中子不敏感”的结论. 而14 nm FinFET工艺器件表现出一定的热中子敏感性的现象与FinFET工艺器件M0附近工艺中使用了10B元素有关. 图7为65 nm平面工艺和14 nm FinFET工艺SRAM的中子MBU比例对比, 包含了热中子和E > 10 MeV中子的共同贡献. 可见, 相比于65 nm平面器件, 14 nm FinFET器件的MBU比例明显增高. 其中, 两位翻转比例从2.1%增大至6.6%; 65 nm平面器件中未发现三位翻转, 而14 nm FinFET器件的三位翻转比例为1%. 图 7 65 nm平面工艺和14 nm FinFET工艺SRAM的中子MBU比例对比(使用图2的全能谱) Figure7. Comparison of neutron MBU ratio of 65 nm planar and 14 nm FinFET SRAM devices (using the full spectrum in Fig. 2).