1.School of Science, Harbin Institute of Technology (Shenzhen), Shenzhen 518055, China 2.Key Laboratory of Micro-Nano Optoelectronic Information System of Ministry of Industry and Information Technology, Harbin Institute of Technology (Shenzhen), Shenzhen 518055, China
Fund Project:Project supported by the Young Scientists Fund of the National Natural Science Foundation of China (Grant No. 61604049), the Shenzhen Overseas High-Caliber Personnel Technology Innovation Project, China (Grant No. KQJSCX20170726104440871), and the Startup Funding of Shenzhen, China
Received Date:14 June 2019
Accepted Date:29 October 2019
Available Online:01 January 2020
Published Online:20 January 2020
Abstract:The electrical performance and the long-term reliability of GaN-based high electron mobility transistors (HEMTs) are greatly affected by the Joule self-heating effect under high power density operation condition. Measurement of the junction temperature and analysis of the thermal resistance of the constituent layers including the packaging material are critically important for thermal design and reliability assessment of GaN-based HEMTs. In this paper, Raman thermometry combined with the finite element thermal simulation is used to compare the junction temperature and the thermal resistance of a GaN HEMT mounted on a novel Cu/graphite composite flange with those of a conventional CuMo flanged device. The results show that the junction temperature of the Cu/graphite flanged device is 15% lower than that of the CuMo flanged device at a power dissipation of 1.43 W/mm, while the overall device thermal resistance is 18.7% lower in the Cu/graphite flanged device. In addition, the temperature distributions of each layer along the cross-plane direction are analyzed for the two devices; the thermal resistance ratio of the Cu/graphite flange is 40% of the overall device thermal resistance, while the CuMo flange account for 53% of the overall thermal resistance of the device. This proves the effectiveness and benefit of using the Cu/graphite composite material package of high thermal conductivity to improve the heat dissipation of GaN HEMTs. By tuning the mass fraction of the graphite, it is possible to further increase the thermal conductivity of the Cu/graphite composite flange and to further reduce the device thermal resistance. It is observed in the Raman thermal measurement that the highest thermal resistance after flanging is the interfacial thermal resistance between the GaN epitaxial layer and the SiC substrate (~50 m2·K/GW). For obtaining the better thermal characteristics of the GaN HEMT, it is crucial to reduce the GaN/SiC interfacial thermal resistance through interface engineering during the epitaxial growth. In the meantime, Raman thermometry combined with the finite element thermal simulation is demonstrated to be an effective method for implementing the thermal characterization of the GaN-based devices and the constituent material layers, and the principle and procedure of the method are described in detail in the paper. Keywords:GaN high electron mobility transistor/ thermal resistance/ Cu/graphite flange/ Raman thermometry
表1两种铜基法兰封装GaN器件的热阻对比 Table1.Thermal resistance of GaN HEMT with different Cu-based flange materials.
图 4 (a)铜/石墨法兰封装器件GaN层、SiC上表层和封装法兰的温度随功率密度的变化; (b)铜/石墨法兰封装器件GaN层和SiC上表层的温度差、GaN层和封装法兰之间的温度差随功率密度的变化; (c)铜钼法兰封装器件GaN层、SiC上表层和封装法兰的温度随功率密度的变化; (d)铜钼法兰封装器件GaN层和SiC上表层的温度差、GaN层和封装法兰之间的温度差随功率密度增加的变化 Figure4. (a) Measured temperature of GaN, SiC, and the Cu/graphite flange as a function of the device power density; (b) temperature differences between GaN and SiC, and between GaN and and the Cu/graphite flange as a function of the device power density; (c) measured temperature of GaN, SiC, and the CuMo flange as a function of the device power density; (b) temperature differences between GaN and SiC, and between GaN and and the CuMo flange as a function of the device power density.
表2有限元热仿真分析中使用的各层材料的尺寸及热导率 Table2.Dimensions and thermal conductivity of each layer in the GaN-on-SiC HEMT used in the finite element device thermal simulation.
图 5 (a)铜/石墨法兰封装的GaN器件的GaN外延和SiC衬底上表层温度的模拟值(线)和实测值(点); (b)铜钼法兰GaN电子器件的结温和SiC衬底上表层温度的模拟值和实测值的对比; (c) 1.43 W/mm功率密度下铜/石墨法兰和铜钼法兰封装GaN器件在垂直器件表面方向上的温度分布; (d)铜/石墨法兰和铜钼法兰封装GaN器件各层材的热阻占比(其中TBR的材料为AlN) Figure5. (a) Simulated (line) and measured (dot) junction temperatures of the Cu/graphite flanged device; (b) simulated (line) and measured (dot) junction temperatures of the CuMo flanged device; (c) depth wise temperature distribution of the Cu/graphite flanged device and the CuMo flanged device at the power density of 1.43 W/mm; (d) thermal resistance of each layer within the Cu/graphite flanged device and the CuMo flanged device (The material of TBR is AlN).