1.
Introduction
With the continuous scaling of process and power supply voltage, the design of mixed-signal integrated circuits is facing unprecedented challenges. In recent years, the development of wearable medical equipment has put forward higher requirements for the power consumption of integrated circuit chips[1–3]. As an indispensable module, the power optimization of the analog-to-digital converter (ADC) has become a hot spot in the design. A traditional sigma–delta modulator uses an operational amplifier as the core module of the integrator, which is also the main source of power consumption.
To realize low power OTA, a variety of circuit solutions have been proposed. Refs. [4, 5] respectively presented the body-driven OTA and digital-assisted OTA. The small equivalent output transconductor with poor noise performance means the body-driven OTA can only be applied in signal-bandwidth limited design. The digital-assisted OTA increases the excess power consumption for a digital calibration circuit. Although the comparator-based OTA in Ref. [6] uses the current source to eliminate the unstable point in the feedback loop, the circuit cannot work in a low power supply voltage environment. In this paper, to overcome these difficulties, the inverter is adopted as the OTA circuit in the integrator[7]. With this design technique, the sigma–delta modulator is realized and achieves excellent power efficiency and resolution in spite of the low supply voltage.
Ref. [8] proposed a feedback 2nd-order structure based on a self-biased digital inverter. With a 0.5 V power supply 63.6 dB SNDR is achieved. But its power reached 17 μW. Using the near-threshold-voltage-biased inverter, the 3rd-order modulator in Ref. [9] works at a low voltage of 250 mV, it only consumes 7.5 μW when obtaining 61 dB SNDR. However, the stability problem of the 3rd-order modulator restricts the input signal amplitude, and the near-threshold circuit also has poor robustness. The 2nd-order modulator in Ref. [10] operates at a 1.5 V supply voltage, and the power consumption reaches 58.3 μW. So, it is difficult to apply to the low-power sensor system. In this paper a 2nd-order modulator with a bootstrap switch is proposed, and high resolution and low power consumption are achieved.
2.
Circuit principle
The traditional OTA-based and inverter-based integrator are shown in Figs. 1(a) and 1(b) respectively.
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Figure1.
Integrator circuit (a) using OTA, (b) using inverter.
In Fig. 1(a), the integrator is controlled by a non-overlapping clock: sampling clock (clk1) and integrating clock (clk2). When clk1 is high, the input signal is sampled into the sampling capacitor Cs; while clk2 is high, the charge stored in Cs is transferred to the feedback capacitor Cf to complete the integration operation. In Fig. 1(a) the OTA negative input terminal Vx shorting to the positive input terminal virtually becomes a virtual ground node. But in Fig. 1(b), unlike the OTA-based integrator, the inverter-based integrator has only one input, and cannot form a virtual ground. Therefore, the voltage of the Vx node is close to the inverter input offset voltage Voff:
${V_{ m{x}}} = frac{A}{{1 + A}}{V_{{ m{off}}}} - frac{{{V_{{ m{Cf}}}}}}{{1 + A}} approx {V_{{ m{off}}}},$  | (1) |
where the A is the DC gain of the inverter, and
m{Cf}}}}$
m f}({V_{{
m{in}}}} - {V_{{
m{off}}}})$
An inverter-based integrator with auto-zeroing offset cancellation mechanism is shown in Fig. 2[11]. In the clk1 phase, the inverter forms a unity-gain feedback circuit, and Voff is sampled into capacitor Cc. At the same time, the input signal is sampled to the sampling capacitor Cs; in the clk2 phase, the Vx node voltage is the offset voltage due to the negative feedback path formed by Cf. At this time, the node VG can be used as virtual ground, and the charge in Cs is completely transferred to Cf. So, we can get the relationship between the input and output of the integrator as:
${C_{ m{s}}} {V_{{ m{in}}}}(n + 1/2) + {C_{ m{f}}} {V_{{ m{out}}}}(n) = {C_{ m{f}}} {V_{{ m{out}}}}(n + 1).$  | (2) |
Derive the transfer function of the integrator in the z-domain as:
$frac{{{V_{{ m{out}}}}(z)}}{{{V_{{ m{in}}}}(z)}} = frac{{{C_{ m{s}}}}}{{{C_{ m{f}}}}} times frac{{{z^{ - 1/2}}}}{{1 - {z^{ - 1}}}}.$  | (3) |
The pseudo-differential integrator including the common mode feedback (CMFB) circuit is shown in Fig. 2(b). The CMFB capacitance Cm detects the output common mode voltage in clk2 phase, and in clk1 phase the common mode voltage is input to the signal path. The difference between the CMFB voltage and the common mode voltage in the signal path will be input into the integrator, which constitutes the CMFB loop. The CMFB gain is determined by the capacitance ratio Cm/Cf. Because Cm in each integral cycle only drives a small amount of charge to maintain the output common mode voltage, the Cm value is smaller, which will not increase the load capacitance of the integrator.
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Figure2.
Auto-zeroing inverter-based integrator (a) single-ended, (b) pseudo-differential.
The main specification of the sigma–delta modulator includes three aspects: output resolution, signal bandwidth, and power consumption. Since the design in this paper is mainly used in portable or wearable low-power medical devices, the signal bandwidth is small, which is usually within hundreds of Hertz. A low power supply is used to reduce the power consumption. Therefore, the output resolution has become the main objective. These specifications are mainly affected by the gain, bandwidth, and slew rate of OTA in the integrator. Because the inverter is used to replace the traditional OTA, the bandwidth and slew rate of open-loop inverters are large, which can meet the requirements for the set-up of hundreds of Hertz signals. The output resolution is mainly limited by the inverter gain, that is to say, the non-ideal characteristics of the sigma–delta modulator mainly come from the limited gain of the inverter. The gain of traditional inverters is usually between 20–30 dB. In order to increase the output gain, this paper uses a cascode inverter for design.
Therefore, the effect of finite gain (A) was simulated depending on modulator order with OSR of 256, as shown in Fig. 3. It demonstrates that when adopting a 2nd-order modulator structure and achieving 70 dB SNDR, the minimum gain is 30 dB. In order to leave a certain design margin, the cascade inverter with larger DC gain is chosen for our circuit in Fig. 4. By simulation the cascade inverter shows 55 dB gain that will satisfy the modulator's design requirement.
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Figure3.
(Color online) SNDR versus inverter gain for OSR = 256.
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Figure4.
Cascode inverter.
However, because there are four transistors through power to ground, the output swing of the cascade inverter is limited, reducing the output dynamic range to a certain extent.
In the sigma–delta modulator, the noise is mainly determined by the switch-capacitor thermal noise of the first integrator. The sampling phase and integral phase will both contribute to certain noise. In the sampling phase, the input noise power is:
${P_{{ m{sampling}}}} = frac{{kT}}{{{C_{ m{s}}}}}.$  | (4) |
Assuming that the transconductance of NMOS and PMOS is equal, the input noise power of the integral phase is:
${P_{{ m{integral}}}} = frac{{kT}}{{{C_{{ m{Leff}}}}}} gamma frac{{{C_{ m{f}}} + {C_{ m{s}}}}}{{{C_{ m{f}}}}} {left( {frac{{{C_{ m{f}}}}}{{{C_{ m{s}}}}}} ight)^2},$  | (5) |
where
m{Leff}}}} approx frac{{{C_{
m{S}}} {C_{
m{f}}}}}{{{C_{
m{S}}} + {C_{
m{f}}}}} + {C_{
m{C}}} + {C_{{
m{S}}2}}$
m{S}}2}}$
m{f}}}/{C_{
m{s}}} = 7$
${P_{{ m{integral}}}} = 56 frac{{kT}}{{{C_{{ m{Leff}}}}}}.$  | (6) |
Similarly, the sampling phase noise of the second stage integrator will also be fed to the first stage, so the noise power of the second stage integrator is divided by the first stage integrator gain
m{f}}}/{C_{
m{s}}}$
$begin{split}{P_{{ m{total}}}} &approx 4 frac{{kT}}{{{C_{ m{s}}}}} + 2 times 56 times frac{{kT}}{{{C_{{ m{Leff}}}}}} + 2 times 49 times frac{{kT}}{{{C_{{ m{s}}2}}}} &= 4 times frac{{kT}}{{{C_{ m{s}}}}} + 112 times frac{{kT}}{{{C_{{ m{Leff}}}}}} + 98 times frac{{kT}}{{{C_{{ m{s}}2}}}}.end{split}$  | (7) |
Unlike traditional integrators using OTA, the inverter-based integrator is susceptible to clock jitter. The clock jitter is added to the input signal:
${V_{{ m{in}}}} = {V_{{ m{amp}}}} sin (2pi f (n T + {t_{{ m{jitter}}}})),$  | (8) |
where
m{clk}}}}}}$
m{jitter}}}}$
${sigma _{{ m{jitter}}}} = sqrt {frac{{ m OSR}}{{{{(2pi m BW)}^2} m SNDR}}} .$  | (9) |
Finally, put thermal noise,
m{S}}} = 560 text{fF}$
m{C}}} = 3920 text{fF}$
m{f}}} = 3920 text{fF}$
m{S}}2}} = 480 text{fF}$
m{jitter}}}} = 0.13$
m Gain}$
3.
Schematic design
The schematic of the proposed 2nd 14 bit/500 Hz sigma–delta modulator is shown in Fig. 5.
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Figure5.
2nd 14 bit/500 Hz sigma–delta modulator.
The modulator adopts a stable 2nd order feedback structure. High reference voltage Vrefh and low reference voltage Vrefl are set to the power supply and ground, respectively, which means the quantization range is 600 mV ideally. Clk1 and clk2 are the non-overlapping two-phase clock. Clk1a and clk2a are respectively clk1 and clk2 delay shutdown clock signal, whose purpose is to reduce the charge injection effect. In order to keep the gate-drain voltage of the switch constant in 0.6 V power supply and reduce the harmonic distortion introduced by the switch, the bootstrapped switch is used as an input sampling switch as shown in Fig. 6[12–16].
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Figure6.
Bootstrap switch.
The operating principle of the bootstrapped switch is as follows: when CLK is low, the switch is in the holding state, and transistors M5, M6 turn on to make node n3 connect to ground. Meanwhile M2, M3 turn on and the capacitor C1 is charged to VDD, and switch transistor MS, CMOS switch (M1/M10) turn off. Due to the M7’s turn-on, the node n5 is high. Transistor M4 turns off so that the node n3 and node n2 are disconnected. Therefore, the voltage change of switch input will not affect the output node of the circuit.
When CLK is high, the switch enters the sampling state. M1, M10 turn on to make node n1 voltage equate to input Vin. At the same time, M2 turns off and M4, M8 turn on. So, node n3 voltage rises and M3 turns off. Transistor MS connects to capacitor C1 through the CMOS switch, whose difference of the gate-drain voltage is equal to the voltage VC across C1.
Due to the rise of internal node voltage during the sampling state, it brings reliability problems for the bootstrapped switch. When transistor size enters into the deep submicron era, the voltage difference between any two points in the four terminals of the transistor must not exceed 1.7VDD. To improve reliability, M5 and M9 are added to this circuit. The role of M5 is to ensure that the gate-source voltage of M4 is not greater than VDD when it turns on. While CLK is in low state, M5 ensures that the Vgd and Vds of M6 do not exceed VDD.
4.
Measurement result
The sigma–delta modulator is realized with CMOS 0.13 μm 1P8M mixed-signal process with a 0.6 V power supply voltage. The die photograph is shown in Fig. 7 whose overall area is 1.32 mm2 and the core area is 0.72 mm2.
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Figure7.
(Color online) Die photograph of sigma–delta chip.
Fig. 8 shows the measured power spectrum of output for a 400-Hz 500-mV peak-to-peak differential input sine wave, with a 0.6 V power supply. A 69.7 dB SNDR is achieved, and ENOB is 11.3 bit with 5.07 μW power consumption, which indicates that the sigma–delta modulator can achieve high output signal resolution under low power supply.
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Figure8.
(Color online) FFT spectrum result of sigma–delta modulator.
The SNDR versus input amplitude is illustrated in Fig. 9. This result shows the circuit maintains a large input quantization range close to 500 mV.
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Figure9.
(Color online) Relationship of SNDR and input amplitude.
The SNDR versus power-supply voltage curves (signal reference/swing fixed) is shown in Fig. 10. From 0.6 to 0.8 V, the sigma–delta modulator maintains a high SNDR unaffected by the supply voltage variation.
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Figure10.
(Color online) Relationship of SNDR and power supply.
The performance of our work is compared with the previous work in Table 1. The previous works usually adopted feedback 2nd or 3rd-order structure and CMOS switches. The advantage of the 3rd-order modulator is that it can obtain a higher SNR; however, the structure is more complex and conditionally stable. Moreover, a stability design is required and the input amplitude range is also limited. Further, the output SNR of the 2nd-order structure is limited, which cannot further achieve a higher output resolution. In this paper, the feedback 2nd-order structure is used with a bootstrap switch, which is simple and unconditionally stable. Compared with the 3rd-order structure, the power consumption is reduced effectively with one integrator less. Then the sampling resolution is improved by the bootstrap switch. Finally, the highest output SNDR is achieved in the low-order structure, and the better design results are also obtained. In the 0.6 V power supply with less signal bandwidth, our work achieves the highest SNDR and lowest power consumption. The total performance stands in comparison with those results of references.
| Parameter | Ref. [8] | Ref. [9] | Ref. [10] | This work |
| Technology | 130 nm CMOS | 130 nm CMOS | 500 nm CMOS | 130 nm CMOS |
| Power supply (V) | 0.5 | 0.25 | 1.5 | 0.6 |
| Bandwidth (kHz) | 8 | 10 | 0.05 | 0.5 |
| Modulator order | 2 | 2 | 2 | 2 |
| Peak SNDR (dB) | 63.6 | 61 | 55.39 | 69.7 |
| ENOB (bit) | 10.2 | 9.8 | 8.9 | 11.3 |
| Power consumption (μW) | 17 | 7.5 | 58.3 | 5.07 |
| FoM (pJ/conversion step) | 0.9 | 0.41 | 1220 | 2 |
| Area (mm2) | — | 0.37 | 2.25 | 0.72 |
Table1.
Performance comparison.
Table options
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| Parameter | Ref. [8] | Ref. [9] | Ref. [10] | This work |
| Technology | 130 nm CMOS | 130 nm CMOS | 500 nm CMOS | 130 nm CMOS |
| Power supply (V) | 0.5 | 0.25 | 1.5 | 0.6 |
| Bandwidth (kHz) | 8 | 10 | 0.05 | 0.5 |
| Modulator order | 2 | 2 | 2 | 2 |
| Peak SNDR (dB) | 63.6 | 61 | 55.39 | 69.7 |
| ENOB (bit) | 10.2 | 9.8 | 8.9 | 11.3 |
| Power consumption (μW) | 17 | 7.5 | 58.3 | 5.07 |
| FoM (pJ/conversion step) | 0.9 | 0.41 | 1220 | 2 |
| Area (mm2) | — | 0.37 | 2.25 | 0.72 |
In conclusion, the design of this paper combines the characteristics of 2nd-order sigma–delta with simple structure and unconditional stability, and uses the advantage of low-voltage bootstrap switch for high resolution sampling. Unlike previous works with gain-boost class-C inverter, this work only obtains the highest SNDR by a simple cascode inverter, and the FoM value is also highly competitive. Therefore, our result achieves a good tradeoff between design complexity, SNDR, and power consumption.
5.
Conclusion
For low power and high resolution ADC application in wearable medical devices, this paper presents a low power 14 bit/500 Hz sigma–delta modulator based on a cascade inverter. Implemented with the CMOS 0.13 μm 1p8m mixed-signal process, the circuit adopts a 2nd feedback structure. In the low power supply voltage of 0.6 V, the circuit completes the high resolution sampling of the input signal with the bootstrap switch. In order to reduce the power consumption of the modulator, a cascode inverter replaces traditional OTA in integrator design. Measurement results show that with 256 kHz clock frequency, in the signal bandwidth of 500 Hz, the peak SNDR achieves 69.7 dB and ENOB is 11.3 bit. Also, the power consumption is only 5.07 μW. Compared with the previous work of the 2nd sigma–delta modulator, our work has the highest SNDR and lowest power consumption.
