1.
Introduction

The silicon on insulator lateral diffused metal oxide semiconductor (SOI LDMOS) has been widely used in intelligent and power applications in the last few years. A key issue in the development of the SOI LDMOS device is the design and realization of the RESURF technologies^[1–3], which were mainly used to improve the breakdown voltage of power devices. For SOI LDMOS the on-state resistance is also the major characterization parameter. In order to reduce the power consumption, methods for further improving the trade-off characteristics between the breakdown voltage (V_B) and the on-resistance (R_on) have always been a major issue in the design of LDMOS devices. Recently the variation of the lateral width (VLW) structure together with a high-k dielectric is employed to improve the 3-D RESURF effects^[4–7], achieving not only the maximum breakdown voltage, but also low specific on-resistance due to the high doping concentration of the drift region. In these previous works, the theoretical analysis of the breakdown voltage for the VLW LDMOS structure and other structures associated with it has been reported in detail, while the previous discussions mainly focuses on the breakdown voltage, whereas the specific on-resistance has not been discussed sufficiently^[8–10].



Beside considering the device on-state power consumption, the SOI transistors suffer severe self-heating problems where the thermal conduction toward the substrate is impeded by the buried oxide layer of low thermal conductivity beneath the SOI layer^[11–15]. In order to spread the heat accumulated in the active region for avoiding local temperature rising, which may lead to device failure^{[16, 17]}, a few methods have been adopted. One of the feasible methods is the partial SOI structure, which can alleviate the self-heating effects due to a small opening in the buried oxide layer, typically beneath the channel region^{[18, 19]}, so the heat generated near the channel can dissipate to the substrate reducing the self-heating effect. Another way of reducing the self-heating effect is utilizing a sapphire (Al₂O₃) substrate as an insulator layer under the silicon film, where its thermal conductivity is higher than oxide. This structure is known as silicon on sapphire (SOS), and shows better thermal and RF performance^[20–22]. However, SOS devices are high-cost and suffer higher trap density at the silicon/Al₂O₃ interface compared with SOI. The thermal conductivity of sapphire is not better than that of silicon^[22]. An alternative method is to replace the buried oxide by another insulator with high thermal conductivity. One of the interesting candidates for such a novel substrate is the semi-insulating silicon carbide (SiC), due to its high thermal conductivity and wide bandgap^[23].



In this work, an analytical model is proposed to analyze the specific on-resistance of the VLW LDMOS device. By analyzing and comparing the analytical values and the simulation results along with device dimensions, it can be concluded that the analytical model can guide device design to some extent. The analytical model about the doping concentration and the specific on-resistance can be directly obtained with dimensional parameters. Next, the thermoelectric simulations of the Si/SiC substrate VLW LDMOS transistor compared with the SOI transistor are presented by Technology Computer Aided Design Sentaurus. The results exhibit that the Si/SiC device is more robust against the self-heating effects than the SOI VLW LDMOS device even at high temperature applications.

2.
Device structure and mechanism

2.1
The VLW SOI LDMOS device description

Fig. 1 shows a schematic of a half-cell of the VLW SOI LDMOS device. The main feature of the VLW structure is the tapered dielectric stripe next to the slanted n-type drift region. The parameter w_sc is the width of the n stripe at the channel end while w_dd is the width of the dielectric stripe near the drain. The main parameters used in the simulation have been shown in the figure. As presented in^[4], the linear increased lateral width of the silicon pillar results in an almost ideally uniform lateral electric field distribution and the maximum breakdown voltage. Meanwhile, the high-k material which is used in the dielectric region in VLW devices can also modulate the electric field in the silicon region. As a result, apart from allowing a high breakdown voltage to be achieved on SOI, the proposed structure with its heavily doped n-type drift doping concentration forming a low-resistance drift region provides a low on-resistance current path in the on-state^[24–27].






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Figure1.
(Color online) Schematic of a half-cell of the VLW SOI LDMOS device.

2.2
Characterization of the specific on-resistance

In our simulation, the basic analytical expression of on-resistance for characterizing this structure is established. As can be seen in Fig. 1, the drain region directly contacts with both the silicon and the dielectric pillar. The electric flux goes through both the dielectric and the n-type silicon stripes, which means these two parts can be treated as one region^[5]; we therefore assume that region is an equivalent drift region with an effective permittivity ε_eff, where the permittivity of silicon and the dielectric material are ε_Si and ε_di, respectively.



For LDMOS devices, to obtain the optimal breakdown characteristics, the following conditions must be satisfied: the drift region is fully depleted, and the breakdown that occurs in the body and electric field of the drift-channel junction equals to that of the drift-drain junction. The analysis is as follows.



For VLW LDMOS, the distribution of the lateral surface electric field is almost ideally uniform, since we have derived in the article^[6] before in which it is inferred that the critical electric field value can be derived from the avalanche breakdown condition along the x-axis, as

$${E_{{ m{xc}}}} = - frac{b}{{{ m{ln}}frac{1}{{a{L_{ m{d}}}}}}},$$

(1)

in which, a = 7.03 × 10⁵ cm^?1 and b = 1.468 × 10⁶ V/cm, L_d represents the length of the drift region. So, the breakdown voltage and the doping concentration of N-drift region can be expressed as

$${V_{ m{B}}} = - frac{b}{{{ m{ln}}frac{1}{{a{L_{ m{d}}}}}}} times {L_{ m{d}}},$$

(2)

and

$${N_{ m{d}}} = {varepsilon _{{ m{eff}}}}frac{{{E_{{ m{xc}}}}{L_{ m{d}}}}}{{{ m{q}}t_{{ m{eff}}}^2}},$$

(3)

where ${varepsilon _{{
m{eff}}}} = {varepsilon _{{
m{si}}}}frac{{{w_{{
m{sc}}}}}}{{{w_{
m{d}}}}} + frac{{{varepsilon _{{
m{si}}}}{varepsilon _{{
m{di}}}}}}{{{varepsilon _{{
m{si}}}} - {varepsilon _{{
m{di}}}}}}{
m{ln}}frac{{{varepsilon _{{
m{si}}}}}}{{{varepsilon _{{
m{di}}}}}} times frac{{{w_{
m{d}}} - {w_{{
m{sc}}}}}}{{{w_{
m{d}}}}}$, $t_{{text{eff}}}^2 = t_{text{s}}^2left( {0.5 + }
ight.$ $ frac{varepsilon _{{text{eff}}}}{varepsilon _{text{box}}} times {frac{{{t_{{text{box}}}}}}{{{t_{text{s}}}}}} ) $ and from Eq. (3) we can see that the optimal drift region doping concentration is proportional to the drift region length. The longer drift region corresponds to heavier optimal doping concentration. In addition, the use of high-k material makes the equivalent permittivity improved, further improving the doping concentration of the drift region.



Among the electrical parameters, the on-state resistance R_on plays a relevant role in power LDMOS transistors. In this work, the on-resistance of the VLW LDMOS is mainly focused on the two components: the channel resistance R_channel and the drift region resistance R_drift. The composition of on-resistance of the VLW structure is shown in Fig. 2, by calculation of the R_channel and R_drift, the analytical expression can be demonstrated as follows respectively.






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Figure2.
(Color online) Schematic of resistance of the VLW structure.




For N channel LDMOS devices, the channel resistance can be expressed as^[28],

$${R_{{ m{channel}}}} ,,=,, frac{{{V_{{ m{ds}}}}}}{{{I_{{ m{ds}}}}}},, =,, frac{{{L_{ m{g}}}}}{{{mu _{{ m{ni}}}}{w_{{ m{sc}}}}{C_{{ m{ox}}}}left( {{V_{{ m{gs}}}} - {V_{{ m{th}}}}} ight)}},$$

(4)

in which L_g is channel length, μ_ni is inversion layer carriers mobility, C_ox is gate oxide specific capacitance, V_gs is gate-source voltage, V_th is threshold voltage, lastly because of the planar gate structure the channel width is w_sc.



Due to the N drift region exhibiting a tapered pillar, using the infinitesimal method, we can calculate the dR_drift as

$${ m{d}}{R_{{ m{drift}}}}, =, ho frac{{{ m{d}}x}}{{{ m{d}}{t_{ m{s}}}}},$$

(5)

where ρ is the resistivity of the material, and w_x is the width along the z axis at the position x in the drift region. In advance we define α = w_sc/w_d, β = w_dd/w_d, therefore, ρ and w_x can be expressed as

$$left{,,, {begin{split}&{ ho = frac{1}{{{N_{ m{d}}}q{mu _{ m{n}}}}},}&{{w_x} = left( {1 - alpha - beta } ight)frac{x}{L_{ m{d}}}{w_{ m{d}}} + alpha {w_{ m{d},}}}end{split}} ight.$$

(6)

respectively, where N_d is the drift region concentration, which equals to the amount of free carriers with low drain voltages. μ_n is electron mobility.



By calculating the integral of Eq. (5) from 0 to L_d, we can obtain R_drift as,

$${R_{{ m{drift}}}} ,=, mathop int limits_{ m{0}}^{{L_{ m{d}}}} ho frac{{ m{1}}}{{{ m{d}}{t_{ m{s}}}}}{ m{d}}x ,=, frac{{ m{1}}}{{{N_{ m{d}}}q{mu _{ m{n}}}{t_{ m{s}}}}} frac{{{L_{ m{d}}}}}{{left( {{ m{1}} - alpha - beta } ight){w_{ m{d}}}}} ,{ m{ln}}frac{{{ m{1}} - beta }}{alpha }.$$

(7)

So, the specific on-resistance of the device can be expressed as

$${R_{ m{on, sp}}} approx {R_{ m{channel}}} ,+, {R_{ m{drift}}}S,$$

(8)

where S is the chip area which the device occupied.

3.
Results and discussions

In this work we use the commercial semiconductor simulation software Sentaurus to verify the dependencies of device parameters on the specific on-resistance characteristics of the VLW LDMOS. The optimal N_d is referred to the doping concentration of the drift region to which the maximum breakdown voltage corresponds based on the blocking characteristic simulation, and the specific on-resistance obtained by simulation also utilizes the optimized N_d.



Fig. 3 presents the simulation results, and the analytical values of the R_on.sp and the optimal N_d with different drift lengths. As we can see, the analytical model can predict the specific on-resistance of the device with the given parameters. The insert graph shows the simulated breakdown voltage V_B corresponding to L_d at the respective optimal N_d. As observable in Fig. 3, the calculated N_d values are in good agreement with the simulation results, indicating that the analytical model can guide the design of devices. Meanwhile, the simulated specific on-resistance fits the calculations very well. Actually, the channel resistance contributes a tiny fraction of the total on-resistance, by calculation the R_channel is almost two orders of magnitude lower than R_drift, this can be verified from Fig. 4 that the electron current density in the channel is much higher than the drift region especially at position A where the drift region width w_sc is 0.1 μm as stated above, for the sake of observation, only showing a part of the region with high electron density nearby the channel region. It can also be obtained from the figure that the drift region doping concentration is essentially proportional to the length of the drift region, simultaneously, from Eqs. (3) and (7), it can be inferred that the specific on-resistance is basically proportional to L_d, which is consistent with the simulation results.






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Figure4.
(Color online) The contour of electron current density of the device (L_d = 40 μm), and the electron current density distribution curve located below is obtained by the cutline at y = ?0.05 μm along the x axis.






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Figure3.
The R_{on, sp} and the optimal N_d via different drift region length L_d.




The drift region resistance R_drift is inversely proportional to the drift region doping concentration. The other component channel resistance R_channel is inversely proportional to the width of the current flow channel at the P-well/N-drift junction (w_sc), although it does not contribute a significant portion. Therefore by analysis, the R_{on, sp} is decreased with decreasing of w_sc due to the increasing of N_d. Fig. 5 shows the dependencies ofw_sc on the R_{on, sp} and the V_B. It can be seen that the V_B decreases with w_sc increasing. The corresponding optimal N_d is also shown for the given width w_sc. With w_sc increasing, the current flow path is broadened, which improves the on-resistance characteristics of the device. It can be observed that there exists a tiny deviation between the calculated results and the simulation results, which gradually increase with w_sc, since the factors such as grid distribution may affect the results obtained from the simulation. However, it does not influence the trend of the entire results. When w_sc increases to 1.0 μm, it is no longer sufficient for the structure to modulate the electric field distribution, leading to V_B falling sharply. Accordingly, a design can be obtained with appropriate dimensions with rated voltage.






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Figure5.
The R_{on, sp} and the V_B via different w_sc, and the calculated N_d based on the formula and optimal N_d for each w_sc by simulation is marked out.




Fig. 6 shows the dependencies of ε_di on the optimal N_d and the R_{on, sp}. The analytical values and simulation results represent that the optimal N_d increases and the R_{on, sp} decreases with the increasing ε_di. The V_B calculated from Eq. (2) is 369 V for the given L_d, furthermore the insert graph shows the dependence of V_B on ε_di by simulation with respective optimal N_d. For VLW structure, the value of ε_di increasing means that more carriers are required to compensate the charges induced by the dielectric. Simultaneously corresponding to Eq. (3), ε_eff increases with the increasing ε_di for a group of device dimensional parameters, and hence a high N_d is allowed in the VLW SOI LDMOS device, eventually resulting in low R_{on, sp}. However, higher ε_di meaning higher N_d to deplete in the drift region, but in the simulation higher N_d cannot be fully depleted, eventually leading to premature breakdown. The analytical calculated values may have some deviation with the simulation results when a low ε_di value is chosen. As the dielectric permittivity ε_di increases, the modulation effect of the slanted structure could be enhanced, so the calculated values fit the simulated results much better.






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Figure6.
The dependencies of R_{on, sp} and N_d on ε_di.




To simulate the self-heating effect in the SOI LDMOS, Poisson’s equation, the current continuity equations, and the heat equation are solved in a completely coupled manner to obtain the lattice temperature. In our simulation, two sets of curves are generated for the cases with and without lattice temperature effects by solving the above equations. As shown in Fig. 7, the Si/SiC VLW LDMOS is implanting an identical device with the 6H-SiC substrate in place of the buried oxide layer, which is very similar to the SOI implantation. The 6H-SiC is used in the proposed structure because of its wide bandgap (3.03 eV), high critical electric field and high thermal conductivity, which is about three hundred times higher than that of oxide^[29]. By hydrophilic wafer bonding and simple MOS-processing techniques, the substrates can be fabricated^[30], and thermal and electrical characterizations are performed to evaluate the substrates.






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Figure7.
(Color online) Device structures of simulated Si/SiC YLW LDMOS device.




3D simulations have been carried out by Sentaurus TCAD. The substrate electrode is grounded and set as the thermode contact for thermoelectric simulations. Thermal conductivities of materials are set to be a power function of temperature. The on-state performance of the two structures are carried out to verify the ability of handling the self-heating effects by nonisothermal simulations.



The output characteristic curve for both SOI and Si/SiC VLW LDMOS transistors are shown in Figs. 8(a) and 8(b), respectively. The gate bias is held at 5.5, 6, 8, 10 V, and the drain bias is ramped from 0 to 30 V. This operating region tests the high-current operation and whether the self-heating effect occurs at large gate and drain biases. The influence of the self-heating effect (SHE) on the SOI device is much more severe, as can be seen in Fig. 8(a), the max drain current has a 40% degradation when V_gs = 10 V compared with the results of no SHE (NSHE). There is a typical change caused by SHE where the drain current is decreased with the increase of drain voltage. The fact that the low thermal conductivity of the buried oxide trapped the heat can raise temperature in the localized area. Since the mobility is sensitive to the temperature and decreases as the temperature rises, the drain current also diminishes due to the degradation in the mobility and emergence of negative differential resistance. However, by studying the negative differential resistance on the I_d–V_d curves in Fig. 8(b), it can be concluded that the Si/SiC VLW LDMOS is less affected by SHE than a SOI device under the same operating conditions, due to the lack of buried oxide layer and the high thermal conductivity of 6H-SiC substrate.






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Figure8.
(Color online) The effect of self heating on output characteristics of (a) SOI and (b) Si/SiC YLW LDMOS.




Fig. 9(a) shows the dependence of the maximum junction temperature on the drain voltage at the given gate voltage. It can be seen from Fig. 9(a) that the temperature rises sharply in the SOI device, and the temperature at any given point is nearly four times higher than that in the Si/SiC device. Since the current density is higher along the conductive path at the junction of the channel and drift region, the resulting power dissipation can cause junction temperatures in the area to rise. The buried oxide of the SOI device is adiabatic, leading to a much higher junction temperature. Fig. 9(b) exhibits the difference between the maximum junction temperature and ambient temperature ΔT_c for nonisothermal I_d–V_d simulation, which is consistent with the output characteristics, and the drain voltage is set at 30 V. The ΔT_c of the Si/SiC device is much smaller than that of the SOI device, since the thermal conductivity of SiO₂ is significantly smaller compared to that of 6H-SiC at room temperature. According to the formula that McDaid reported pertains to the difference between the channel and ambient temperature^[31], the higher the thermal conductivity, the smaller the temperature rise. In addition, the sensitivity of the gate voltage to temperature is very low in the Si/SiC substrate, which means the risk of thermal induced failure can be avoided at high gate biases. The results indicate that the influence of the self-heating effect in SOI is much more serious than in the Si/SiC substrate, and the same conclusion can be drawn from the aforementioned output characteristics simulation.






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Figure9.
(Color online) (a) The maximum junction temperature compared between the SOI and Si/SiC YLW LDMOS. (b) The temperature difference ΔT_c versus V_GS, V_DS = 30 V.




The temperature distributions of SOI and Si/SiC VLW LDMOS transistors are shown in Fig. 10, with the gate and drain contact biased at 10 and 15 V bias voltage, respectively. During the simulation, the ambient temperature is set to 423 K. The maximum temperature in SOI structure reaches 499 K, whereas the Si/SiC substrate reaches 446 K. Since the carriers flowing through the channel region can be accelerated by the high electric field, the high energy carriers can exchange the energy with the lattice, leading to the lattice temperature increasing. The heat will be concentrated near the channel and drift region. Therefore, both devices have a hot spot located at the source side of the drift region, from which the heat flows toward other directions, forming a nonuniform temperature profile. However, the heat flow is impeded in SOI VLW LDMOS due to the buried oxide, which acts as a thermal barrier, resulting in the temperature elevating in the left part of the device, and threatens the stability of the device. In the Si/SiC VLW LDMOS, the SiC substrate dissipates most of the heat from the Si layer, which reduces the temperature gradient in the drift region. Hence, the Si/SiC transistor can be operated with a high power level at a given junction temperature, at the same power with much lower junction temperature, or at a similar power level at a much higher ambient temperature.






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Figure10.
(Color online) Temperature contour of (a) SOI and (b) Si/SiC YLW LDMOS with V_DS = 15 V, V_GS = 10 V.

4.
Conclusion

A detailed analysis of the on-state characteristic of VLW structure was presented in this manuscript. The dependencies of the dimensional parameters such as L_d, w_sc, and permittivity of dielectric ε_di on the optimal drift region doping concentration and the specific on-resistance have been studied. The simulation results are in good agreement with analytical values, indicating that the analytical model of the specific on-resistance can predict the on-state characteristic of VLW LDMOS accurately. The VLW LDMOS implemented on the Si/SiC substrate has been studied by thermoelectric simulation with comparison to SOI VLW LDMOS. The self-heating effect is greatly alleviated in Si/SiC VLW LDMOS than SOI by nonisothermal simulation. In addition, a lower maximum temperature is achieved in the Si/SiC structure with very uniform temperature distribution. It can be concluded that the Si/SiC is beneficial to the development of dense and reliable high temperature circuitry.