1.
Introduction
Pressure sensors are playing an important role in modern industries. Since Tufte et al. demonstrated a silicon piezoresistive pressure sensor in the 1960s[1], silicon-based pressure sensors have been widely adopted in different applications for their high-performance, low cost and small size. In particular, microelectromechanical systems (MEMS) have received a great deal of attention during the past few decades since micromachining technology has greatly benefited from the success of the integrated circuit industry. The silicon pressure sensor is one of the very first MEMS components appearing in the microsystem area.
According to the Yole market report[2], MEMS pressure sensors are expected to grow rapidly for consumer (especially for smartphones and tablets), automotive, industrial, medical, and high-end (aeronautic, military, defense) applications. Also, they are promising in Internet of Things (IoT) applications[3]. Fig. 1 shows the MEMS pressure sensor market forecast[2], in which it grows from $1.9 billion in 2012 to $2.8 billion in 2018. Automotive applications are currently dominating the MEMS pressure sensor market. The automotive, medical, industrial and high-end markets are growing 4%–7%, while the consumer market is growing 38% in volume due to new opportunities in smartphones and tablets.
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Figure1.
(Color online) MEMS pressure sensor market forecast by Yole[2].
Applications for low cost, low power consumption and high accuracy are driving the development of the MEMS pressure sensor[4]. An absolute pressure sensor is one of the most important pressure sensors. They find applications such as in indoor and outdoor navigation, altimeter and barometer for portable devices, weather station equipment, and sport watches, etc.. Among the absolute pressure sensors, silicon membranes over vacuum sealed cavities are generally required. The mechanical properties of crystalline silicon are excellent[5]: it has high strength, high stiffness, high mechanical repeatability, high Q, and no mechanical hysteresis. Also, crystalline silicon is available in large quantities with high purity and low defect density. Many efforts have been made to develop the crystalline silicon membranes over the sealed cavities for pressure sensors since the first silicon piezoresistive pressure sensor[6–13].
Wet etching and double-side processing of silicon wafers for the absolute pressure sensors have been researched and developed for a long time. The pressure measurement is usually performed in three different approaches: piezoresistive (Figs. 2(a) and 2(b)), capacitive (Fig. 2(c)), and resonant (Fig. 2(d)). All these sensors require the sealed vacuum cavity and deformable diaphragm. Fig. 2(a) shows the piezoresistive pressure sensor by using the backside anisotropic wet etching to form the deformable diaphragm and anodic bonding to form the sealed vacuum cavity[6, 7]. Fig. 2(b) shows the piezoresistive pressure sensor by using a high-temperature silicon direct bond, followed by thinning of a wafer and fabrication of the piezoresistors[8], which results in smaller chip sizes and better performances. Similarly, the capacitive pressure sensor in Fig. 2(c) and the resonant pressure sensor in Fig. 2(d) require the deformable diaphragm through the wet etching and the sealed vacuum cavity through anodic bonding or wafer direct bonding. Silicon on insulator (SOI) wafers have also been used for the absolute pressure sensors in order to precisely control the diaphragm and operate in high temperature[9, 10].
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Figure2.
Schematic diagram of pressure sensors. (a) Piezoresistive pressure by anodic bonding. (b) Piezoresistive pressure by wafer direct bonding. (c) Capacitive pressure sensor by anodic bonding or wafer dir-ect bonding. (d) Resonant pressure sensor by wet etching and bonding.
Double-side processing of silicon wafers requires the front-to-backside alignment of the silicon wafers, which is not compatible with the modern integrated circuits process. Furthermore, double-side alignment has the low photography accuracy, causing the low yield. Wet etching of bulk silicon micromachining has usually low efficiency, resulting in high costs.
Wet etching and font-side processing of silicon wafers for the absolute pressure sensors has received a great deal of attention in recent years. Robert Bosch developed the Advanced Porous Silicon Membrane (APSM) process for pressure sensors[11, 12]. Fig. 3 shows the APSM schematic process flow. The main process steps are: local anodic etching of layered porous silicon with different porosities, thermal rearrangement of the porous silicon, and epitaxial growth of the silicon membrane layer. Front side processing on the silicon substrate is only used, which makes monolithic integration of circuitry possible. The commercial piezoresistive pressure sensor with integrated ASIC through the APSM process has been launched by Robert Bosch. Fabrication and processing of the porous silicon are not available in most of IC foundry[13] though they are commercially available.
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Figure3.
Advanced Porous Silicon Membrane (APSM) process[11]. (a) Etching of mesoporous seed layer and nanoporous cavity layer. (b) Thermal rearrangement of porous silicon. (c) Sealing of cavity by lateral overgrowth during Si epitaxy.
Li et al. developed a thin film under bulk (TUB) MEMS technology based on (111) silicon wafers[14]. Fig. 4 shows the TUB schematic process flow. The main process steps are: In the (111) orientation wafer, two rows of small holes are opened along the <211> orientation to form the hexagonal shaped diaphragm by laterally excavating the silicon beneath the diaphragm. Front side processing on the silicon substrate is only used, which is fully compatible with the modern integrated circuits process. However, (111) orientation wafers are not popular in most of IC foundry, and multiple steps of silicon wet/dry etching yield the cost. Additional depositions are also needed for sealing the cavity.
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Figure4.
TUB schematic process flow[14]. (a)(b) Formation of piezoresistors. (c)(d) DRIE etching for the definition of the cavity height. (e) Anisotropic etching for releasing the cavity, and thick polysilicon deposition for sealing the cavity.
The silicon-on-nothing (SON) technology was primarily proposed to replace silicon-on-insulator structures in order to enhance the performance of CMOS circuits[15]. However, the air gap was formed by the etching step after device fabrication so that the process sequences were too complicated for IC fabrication. The empty-space-in-silicon process was developed as a new SON technology in 2000[16, 17]. It uses the silicon surface migration of arrays of etched trenches to create a sealed cavity underneath a silicon diaphragm by hydrogen annealing. By using only one lithographic step, the silicon beams and membranes defined in lateral and vertical dimensions, as well as the crystalline silicon membranes over sealed cavities, can be realized in bulk silicon by the silicon migration technology. Therefore, it was soon used for pressure sensors[18]. Due to these advantages, they have found many applications in the area of MEMS in recent years. This paper reviews the state of the art fabrication of the crystalline silicon membranes over sealed cavities.
2.
Fabrication
2.1
Basic process
Front-side processing crystalline silicon membranes over sealed cavities by using the silicon migration technology are described in Fig. 5[16, 17]: (1) Array of trenches are fabricated on Si (001) wafers using deep reactive ion etching (DRIE) with an etching mask of silicon dioxide, as shown in Fig. 5(a); (2) After removal of the etching mask, the wafers are annealed in a hydrogen ambient at 1000–1150 °C. A heat-treatment induces the surface migration of silicon to minimize the surface energy, leading to widening of the void at the base and shrinking of the opening at the top, as shown in Figs. 5(b) and 5(c). Upon further heat-treatment, coalescence of the voids at the bases of adjacent trenches and closing of the space at the top result in the formation of a continuous cavity, as shown in Fig. 5(d).
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Figure5.
Schematic illustration of front-side processing crystalline silicon membranes over sealed cavities by using the silicon migration technology[16].
Silicon DRIE is well established in the IC/MEMS industry. The two most well-known high-aspect-ratio silicon etch processes are the Cryogenic etching process and the Bosch process with alternating etch and passivation cycles. Mask selectivity for SiO2 hard masks is > 100 : 1 with the cryogenic dry etching and > 300 : 1 with the Bosch process, respectively. By making use of parameter ramping, trenches of > 50 : 1 aspect ratio can be fabricated while keeping the sidewalls straight and vertical.
In order to remove native oxide and to promote smooth surface migration, the annealing ambient has to be kept in a low H2O partial pressure condition[16, 17]. Under such conditions, thermal etching of silicon can be suppressed. A hydrogen ambient under controlled pressure condition is suitable to maintain such appropriate conditions for migration. The typical annealing condition is 1100 °C, 10 Torr in 100% hydrogen ambient.
Since Sato et al. reported microstructure transformation by adopting H2 annealing for patterned Si substrates[16], there have been many works on the silicon migration technique, dealing with the controllability of the final structure through the initial porous array morphology and through processing parameters (time, temperature, and pressure). Numerical models were also developed around this structure reorganization to help in understanding the mechanisms and predicting the final structure.
2.2
Process parameters
Surface self-diffusion of silicon driven by the minimization of surface energy for spontaneous closure of the openings of high-aspect-ratio holes during hydrogen annealing is a dominant mechanism[19, 20].
The topological change induced by the surface-migration of silicon is governed by
$$ v = - frac{D}{{kT}}nabla mu ,$$  | (1) |
where v is the drift velocity of surface silicon atoms, D is the surface diffusion coefficient, k is the Boltzmann constant and T is the process temperature. The chemical potential μ = KγΩ, where K is the local mean curvature, γ is surface tension, and Ω is the molecular volume. The diffusion coefficient of silicon atoms on the surface is a function of the annealing temperature. The diffusion length at the annealing temperature determines the amount of migrated atoms. For example, the 0.6 μm diameter trench could be transformed to form silicon membranes over the sealed cavities by annealing at 1100 °C for 10 min, while the 1.2 μm diameter trench will be transformed to form silicon membranes over the sealed cavities by annealing at 1200 °C. Thus, the annealing condition depends on the size of the initial trenches. A larger trench, the diameter of which is over 5 μm, poses a difficulty in fabricating the silicon membranes over the sealed cavities under the practical annealing conditions at 1000–1200 °C. It is practical to utilize the combination of small trenches for fabricating the large area silicon membranes over the sealed cavities.
The surface self-diffusivity of silicon is clearly increased in reduced pressure H2 ambient. This diffusivity enhancement provides a kinetic path at moderate temperatures for Si micro- and nano-structures to minimize their free energy. This minimization is mostly expressed through the reduction of the surface area by smoothing, rounding, and agglomeration. Hydrogen atmospheres are therefore preferred for reorganization of macroporous arrays. It is found that the surface annealed at 8 × 10?5 Pa is smoother than that annealed at 5 × 10?3 Pa. The formation of SON is due to diffusion of silicon atoms at the surface. The movement speed to the direction of surface normal is in proportion with a diffusing constant. The diffusing constant decreases in proportion to ?4 power of pressure. The movement speed to the direction of the surface increases according to the reduction in pressure. The reorganization of porous structures depends on the atoms movement speed. Sufficient atomic movement tends to make a surface have the smallest energy, so that the surface is flatter.
The annealing time depends on process parameters such as pressure, temperature and trench size[21, 22].
2.3
Size control
The relationship between the initial trench and the resulting sealed cavity was experimentally investigated for the precise control of the size and the shape of the cavity[19–24].
The dimensions of the initial trenches are defined as in Fig. 6(a), where a stands for the width (diameter) of the trench, b stands for the depth of the trench and c stands for the distance between the neighboring trenches, respectively. The dimensions of the spherical voids during annealing are defined as in Fig. 6(b), where d stands for the diameter of the spherical voids and z stands for the distance between the surface of the silicon substrate to the center of the spherical voids. The dimensions of the resulting sealed cavity are defined as in Fig. 6(c), where Ts stands for a slight recess between the top surfaces of the membrane and the substrate, Tm stands for the thickness of the membrane and Tc stands for the depth of the cavity, respectively.
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Figure6.
(Color online) Dimension definition of the initial trench and the resulting sealed cavity.
Experiments have demonstrated the relations among the dimensions under typical annealing condition 1100 °C, 10 Torr for 10 min in 100% hydrogen ambient[23].
$$frac{d}{a} = 0.11,left( {frac{b}{a}} ight) + 1.4,$$  | (2) |
$$frac{z}{a} = 0.56,left( {frac{b}{a}} ight) + 0.3,$$  | (3) |
$${V_{ m s}} = frac{{4pi }}{3}{left( {frac{d}{2}} ight)^3},$$  | (4) |
$${V_{ m t}} = {a^2}b,$$  | (5) |
$$S = {left( {a + c} ight)^2},$$  | (6) |
$${T_{ m c}} = frac{{{V_{ m s}}}}{S},$$  | (7) |
$${T_{ m s}} = left( {frac{{{V_{ m t}} - {V_{ m s}}}}{S}} ight),$$  | (8) |
$${T_{ m m}} = z - {T_{ m s}} - frac{{{T_{ m c}}}}{2},$$  | (9) |
where b/a stands for the aspect ratio of the initial trench, which ranges from approximately 3 to 9.5, Vs stands for the volume of the spherical void, S stands for the unit area containing one trench and Vt stands for the volume of the initial trench, respectively. In order to form the sealed cavity, a + c < d.
Case 1[25]. The square trench consists of a = 1.3 μm, b = 8.1 μm and a + c = 2.4 μm. Wafers with 4 × 14 mm2 processed areas were annealed at 1200 °C and 8 × 10?5 Pa for 15 min. The resulting cavity is: Tm = 2.4 μm, Tc = 2.5 μm, and Ts = 0.78 μm, respectively.
Case 2[26]. The square trench consists of a = 0.9 μm, c = 0.5 μm, and b = 5.4 μm. Wafers in an array of 16 × 16 with the lateral dimension of a single cell being 100 × 100 μm2 were annealed at 1150 °C for 10 min. The resulting cavity is: Tm = 1.5 μm, Tc = 1.2 μm, and Ts = 0.4 μm.
2.4
Surface flatness and roughness
Various tools, such as Raman spectroscopy, secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), transmission electron microscopy (TEM), atomic force microscopy (AFM), etc., have been utilized to characterize the properties of the silicon membranes over sealed cavities[19–28]. No defects were observed at the migrated silicon region. The thin films annealed in hydrogen were reported to be perfectly monocrystalline and to feature a level of stress below the detection level.
Fig. 7(a) shows a cross-sectional SEM image of the silicon membranes over the sealed cavities immediately annealed at 1150 °C for 35 min. Fig. 7(b) shows the profiles along the horizontal lines through the center of the migrated silicon region[23].
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Figure7.
(a) Cross-sectional SEM image of the silicon membrane over the sealed cavity. (b) Height profiles along the horizontal lines through the center of the migrated silicon region[23].
For the silicon membranes over sealed cavities immediately after their formation through the surface-diffusion-driven shape change induced by annealing at 1150 °C, the surface roughness is approximately 15 nm. Additional annealing at 1000–1150 °C was utilized to flatten the silicon membrane surface[27, 28].
2.5
Limitations
The annealing condition depends on the size of the initial trenches. The larger trenches have to be prepared so as to fabricate the SON structure with a large area. However, a larger trench of the diameter over 5 mm poses a difficulty in fabricating a SON structure under the practical annealing conditions. The strength of the SON structure is another factor to limit the size of the SON structure. The fabrication of the SON is completed at high temperature and low pressure ambient. Thus, it is considered that the SON layer is compressed under atmospheric pressure. If the pressure difference is large, it will cause the silicon membrane to touch the bottom. The atmospheric pressure limits the area of the SON structure.
3.
Applications
3.1
Piezoresistive pressure sensors
Front-side processing crystalline silicon membranes over sealed cavities by using the silicon migration technology utilize only one lithographic step, and it is fully compatible with integrated circuit manufacturing technology.
Based on the silicon migration technology, ST Microelectronics developed the VENSENS (VENice process for SENSors) process and launched the first commercial barometers with the range of 260 to 1260 mbar[18, 29]. Fig. 8 shows the chip of LPS331 pressure sensors, where the dimensions of the sealed cavity are Tm = 6.85 μm and Tc = 2.35 μm, respectively.
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Figure8.
(Color online) ST pressure sensor process[18]. (a) LOCOS (LOCal Oxidation of Silicon) isolation. (b) Piezoresistive sensor implantation. (c) Interconnect implantation. (d) Top view of the pressure sensor chip. (e) Cross-section of the sealed cavity.
3.2
Capacitive pressure sensors
Hao et al. from Japan proposed a capacitive absolute pressure sensor by using the silicon migration technology[25]. As shown in Fig. 9, the sensing element consists of a circular single crystal silicon membrane covering a vacuum cavity. To realize the capacitive sensing, a thin Au/Ti film on glass wafer, which serves as top electrode and bottom electrode, is added on the top of the membrane by anodic bonding. The radius of the sensing membrane is 100 μm. The resulting cavity is Tm = 2.4 μm, Tc = 2.5 μm, and Ts = 0.78 μm, respectively. The average sensitivity of the sensor array with 15 diaphragms is 2.88 fF/kPa.
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Figure9.
(a) A schematic view of the capacitive pressure sensor. (b) Cross-section of the sealed cavity[25].
3.3
Tactile sensors
Zeng et al. from the Hong Kong University of Science and Technology demonstrated a process for the monolithic integration of micromechanical devices and complementary metal–oxide–semiconductor (CMOS) circuits based on the silicon migration technology[26]. They designed and fabricated a 16 × 16 active-matrix tactile sensor integrated with a 16-stage CMOS ring counter for row scanning. As shown in Fig.10, a pixel consists of a piezoresistive pressure sensor with a sensitivity of 0.03 μV/V/Pa at VDD = 3 V. The lateral dimension of the pixel is 100 × 100 μm2. The resulting cavity is Tm = 1.5 μm, Tc = 1.2 μm, and Ts = 0.4 μm.
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Figure10.
(Color online) (a) A schematic view of the monolithic integration for the CMOS circuit with a piezoresistive pressure sensor. (b) Top view of a pixel. (c) Top view of a 16 × 16 active-matrix tactile sensor[26].
3.4
Photonic crystal pressure sensors
Wong et al. from Stanford University proposed a photonic crystal pressure sensor by using the silicon migration technology[30]. As shown in Fig. 11, the combination of isotropic and anisotropic etching with selective removal of passivation layers followed by hydrogen annealing yields monolithic crystalline silicon sensors. The process produced the pressure sensors that combine photonic crystal (PC) mirror pressure-sensing diaphragms with silicon-on-nothing reference cavities. The sensor in two configurations for low pressure was demonstrated. (1) A gold coated fiber was directly mounted above the sensor. The configuration has three reflecting surfaces: the gold-coated fiber-tip, the PC mirror and the bottom of the cavity. (2) Light from an AR-coated fiber was collimated onto the sensor. Further, the AR-coated fiber and lens remove the reflection from the fiber-tip and the sensor reflectivity of a Gaussian beam with FWHM of 80 μm which is directly measured.
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Figure11.
(Color online) (a) Pressure sensor process flow. (b) Cross section of the pressure sensor[30].
3.5
Other applications
Fabrication of crystalline silicon membranes over sealed cavities by using the silicon migration technology is simple and flexible. Besides the pressure sensors, it has found applications in other micro/nano areas.
Fluidic resonators with integrated microchannels have been used for mass, density and volume measurements of single micro/nanoparticles and cells, but they are limited by the fabrication complexity. Kim et al. reported a simple and cost effective approach for fabricating hollow microtube resonators based on the silicon migration technology[31]. They demonstrated that vacuum-packaged hollow microtube resonators have quality factors as high as ~13 000.
Ultrathin single crystal Si films are versatile for high performance flexible and semitransparent electronic devices. Park et al. demonstrated single crystal Si membranes with controlled thicknesses from 330 to 470 nm by using the silicon migration technology[32]. A defect-free, flexible and wafer scale Si membrane with thickness of 470 nm was transferred onto a PDMS substrate. The ultrathin flexible Silicon film on PDMS shows an optical transmittance of about 30%–70% in visible and near-infrared light.
A thin monocrystalline silicon absorber layer without resorting to the expensive step of epitaxy is very appealing for reducing the cost of solar cells. Based on the silicon migration technology, Depauw et al. demonstrated that the energy-conversion efficiency of 1-mm-thin cells over 1 × 1 cm2 areas was improved from 2.6 to 4.1% by depositing a stack of amorphous silicon layers as rear-side passivation[33].
4.
Conclusions
Fabrication and applications of crystalline silicon membranes over sealed cavities for pressure sensors by using the silicon migration technology are reviewed in detail. By using only one lithographic step, the silicon beams and membranes defined in lateral and vertical dimensions, as well as the crystalline silicon membranes over the sealed cavities, can be realized in bulk silicon by the silicon migration technology. This emerging technology is very promising not only for the pressure sensors, but also for MEMS.
