Small-signal model parameter extraction of E-mode N-polar GaN MOS-HEMT using optimization algorithms

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本站小编 Free考研考试/2022-01-01

1.
Introduction

An enhancement mode (E-mode) GaN-based high electron mobility transistor (HEMT)^[1] is one of the emerging devices of today’s technology for radio frequency integrated circuit (RFIC) design due to its unique material properties and excellent microwave and noise performance^[2]. These devices have excellent noise figure, high temperature, high power, high frequency, higher breakdown voltage and good radiation hardness which makes them attractive for low noise applications^{[3, 4]}. Due to a positive threshold voltage and high breakdown voltage E-mode GaN-based low noise amplifiers (LNAs)^[5] can avoid a limiter circuit for protection and hence, give rise to a simplified circuit design and improved robustness with reduced cost.

High frequency and low noise characteristics of GaN HEMT can be obtained by reducing the gate length (L_g) and source–drain spacing (L_sd)^{[4, 6, 7]}. But most of the literature does not present the enhancement mode high frequency GaN HEMT because it turns into a depletion mode when its gate length is scaled down^[8]. An enhancement mode high frequency low noise GaN HEMT can be obtained by both vertical and lateral scaling of the device^[9]. N-polar GaN MOS-HEMT is one of the leading candidates for short channel enhancement mode low noise application^[10].

An accurate small-signal equivalent circuit (SSEC) model is required for a wide range of applications starting from understanding its device physics, analysis of device performance, the extraction of intrinsic noise parameters, construction of large-signal models, the characterization and comparison of fabrication processes, and the design of monolithic microwave integrated circuits (MMICs)^[11]. Different small-signal models (SSM) have been proposed for GaN HEMT in various works in the literature^{[12, 13]}. So in this paper an accurate small-signal model is developed for the proposed short-channel enhancement mode N-polar GaN MOS-HEMT.

SSEC models for GaN HEMTs are extensively used in the design of RF front end circuits such as a low noise amplifier (LNA) and other RF circuit switches. There are different parameter extraction techniques available in the literature, which can be mainly classified into two categories: direct determination methods^[14] and optimization methods^[15]. The advantage of numerical optimization methods is that they minimize the error between measured and modeled S-parameters versus different frequencies depending upon different optimization techniques and search range, while the direct method extraction of SSEC model parameters are generally simpler and quicker. In this paper, an improved new analytical method is proposed to extract parasitic capacitances, inductances and resistances. This method is a combination of direct extraction and numerical optimization methods. The advantages of the improved methods are as follows.

(1) The parasitic capacitances, which are treated as depletion-layer extension, are accurately extracted for different pinch-off conditions.

(2) To avoid device performance degradation due to the gate leakage current, the parasitic resistances and inductances are extracted at the pinch-off condition.

(3) These extracted parameters are treated as the initial values for optimization in Matlab and advanced design system (ADS) for more accurate results.

In this paper a short-channel high frequency enhancement mode N-polar GaN MOS-HEMT structure is presented^[10]. From the device simulation results an accurate small-signal equivalent circuit model is developed by using the above described methods, which can be suitable for the RFIC design. The small-signal parameters are first extracted using an analytical technique then the initial values are optimized by using different optimization algorithms such as the Quasi Newton method^[16], PSO method^[17] and Firefly algorithm^[18]. Then the optimized small-signal equivalent circuit is simulated using commercially available Keysight’s ADS tool to verify the accuracy of small-signal model parameters. In order to verify the developed model, the small-signal model results are compared with Silvaco TCAD simulation results as well as the available experimental data of 112 nm N-polar GaN MOS-HEMT from the literature. The current gain of the SSEC model is also validated with experimental data from the literature for validation of the developed model^[10]. The Firefly based optimization technique is evolved as a leading optimization algorithm to solve different engineering problems^[18]. To the best of the author’s knowledge, for the first time the Firefly algorithm has been applied for small-signal model parameters optimization for GaN based MOS-HEMT structure and compared with other optimization techniques, which shows superior performance as compared to previously described optimization algorithms^[16–18].

The organization of this paper as follows. In Section 2, the device structure of the E-mode N-polar GaN MOS-HEMT device structure along with its SSEC model is presented. A brief description of small-signal parameter extraction is presented in Section 3. In Section 4 an overview of the Firefly optimization algorithm is described. In Section 5 the optimization techniques of small-signal model parameters using different optimization algorithms are described and compared. S-parameters and current gain simulation results of the small-signal model are compared with TCAD device simulation results and available experimental data from the literature in Section 6. Finally, the conclusions are drawn in Section 7.

2.
Device structure and small-signal model

Fig. 1 shows the device structure of the enhancement mode N-polar GaN MOS-HEMT with a double deck T shaped metal gate structure^[10]. The device structure consists of a 5 nm GaN channel with a 2 nm AlN back barrier, 2.5 nm AlN cap layer, 5 nm unintentionally doped (UID) Al_0.40Ga_0.60N layer, 30 nm graded AlGaN modulation doped back barrier and GaN buffer grown on SiC substrate from top to bottom. For reducing EOT, the gate dielectric layer consists of a stack of two high-k dielectric layers of 2.5 nm ZrO₂ and 2 nm HfO₂. The output conductance, which is the critical parameter for analog circuit design, can be reduced by using a graded AlGaN modulation doped back barrier. By removing the AlN layers from both the source and drain access regions, 2DEG is maintained under both the sidewalls.

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Parameter	Initial value	Search range (min)	Search range (max)	Firefly algorithm
R_s (Ω)	10	0	20	12
R_d (Ω)	28	0	30	26.395
R_g (Ω)	9	0	30	11.659
L_s (pH)	20	0	50	26
L_d (pH)	51	0	100	60
L_g (pH)	19	0	50	32
C_pd (fF)	44.46	10	100	36.892
C_pg (fF)	46.66	10	100	48.346
C_pgd (fF)	3.6	1	10	2.34
C_gs (fF)	46	1	100	84
C_gd (fF)	6.56	1	20	4.536
C_ds (fF)	15	1	30	18
R_in (Ω)	4.33	1	10	2.5
G_m (m?)	550	400	600	486
R_gd (Ω)	80.092	10	200	76.98
g_ds (mS)	0.74	0	2	0.635
Τ (ps)	1.55	0.1	2	1.265
G_gs (mS)	0.235	0	2	0.156
G_gdf (mS)	0.000 09	0	1	0.000 97