1.
Introduction
The principal objectives of the recent research are to reduce required power, area, and cost of semiconductor devices with high performance, efficiency, and reliability, so that the growth of semiconductor technology is maintained and Moore’s law is kept alive. In order to fulfil these requirements, many emerging and novel devices have come into existence. Some of them were extensions of the complementary metal–oxide–semiconductor (CMOS) technology such as carbon nanotube field effect transistors (CNT-FETs)[1], Nanowire FETs[2], III–V channel replacement devices[3] and tunnel FETs[4], others were developed beyond CMOS technology such as negative gate-capacitance FET[5], spin FET[6], NEMS switch[7], and all-spin logic devices[8]. Along with this progress, numerous information storing techniques have evolved in the domain of volatile and non-volatile memory (NVM) and it is found that NVM emerged with more pace than volatile memory. The emerging memory devices are ferroelectric random access memory (Fe-RAM)[9, 10], phase change memory (PCM)[10, 11], spin-transfer torque random access memory (STT RAM)[10, 12], and resistive switching based memory[13] apart from static RAM (SRAM), dynamic RAM (DRAM) and flash memory[8, 10]. The key challenges faced in memory design are high endurance (i.e. ability to maintain Roff, Ron ratio greater than unity), large retention (i.e. ability to retain information for a long time with large data storage), low cost, fast read/write speed, and compatibility with the CMOS process. Resistive RAM (RRAM), in other words a memristor, is able to accept these challenges and play a crucial role in building futuristic memories[13].
2.
Memristor
In 1971, Leon[14] noticed an absent link between charge (q) and magnetic flux (φ); in order to relate these parameters, he propounded a new nonlinear passive device called the Memristor[14]. It was acknowledged as the fourth fundamental electric circuit element after the capacitor (C), resistor (R), and inductor (L). In fact, the memristor completed the symmetry as shown in Fig. 1 and produced the sixth possible relation, besides the five availed relations among four basic electrical parameters viz. charge (q), voltage (v), current (i), and magnetic flux (φ), all of which are summarized in Table 1. Memristor means in short memory + resistor; it shows dissipative resistance as well as non-volatile memory capability. The memristor memorizes the last resistance or amount of charge that passed through it, corresponding to the magnitude and direction of applied voltage across the device. So the memristor can be described by the state dependent Ohm Law. A memristor is not merely a non-linear resistor, but is a resistor with charge as a state variable[15].
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Figure1.
(Color online) Spotted section: the sixth missing link between charge and flux.
| S.No | Circuit element | Inventor | Invention year | Relating parameter | Relation | Symbol |
| 1 | Capacitor | Ewald George Von Kleist | 1745 | Charge (q) and voltage (v) | dq = Cdv |  |
| 2 | Resistor | George Simon Ohm | 1827 | Voltage (v) and current (i) | dv = Rdi |  |
| 3 | Inductor | Michael Faraday | 1831 | Magnetic flux (φ) and current | dφ = Ldi |  |
| 4 | Memristor | Leon Chua | 1971 | Magnetic flux (?) and charge (q) | dφ = Mdq |  |
| 5 | Basic law of electricity | Charge and current | $qleft( t ight) = mathop smallint limits_{ - infty }^t ileft( tau ight){ m{d}}tau $ or $i = frac{{{ m{d}}q}}{{{ m{d}}t}}$ | |||
| 6 | Basic law of magnetism | Flux and voltage | $varphi left( t ight) = mathop smallint limits_{ - infty }^t vleft( tau ight){ m{d}}tau $ or $v = frac{{{ m{d}}varphi }}{{{ m{d}}t}}$ | |||
Table1.
Description of four fundamental circuit elements.
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| S.No | Circuit element | Inventor | Invention year | Relating parameter | Relation | Symbol |
| 1 | Capacitor | Ewald George Von Kleist | 1745 | Charge (q) and voltage (v) | dq = Cdv | |
| 2 | Resistor | George Simon Ohm | 1827 | Voltage (v) and current (i) | dv = Rdi | |
| 3 | Inductor | Michael Faraday | 1831 | Magnetic flux (φ) and current | dφ = Ldi | |
| 4 | Memristor | Leon Chua | 1971 | Magnetic flux (?) and charge (q) | dφ = Mdq | |
| 5 | Basic law of electricity | Charge and current | $qleft( t ight) = mathop smallint limits_{ - infty }^t ileft( tau ight){ m{d}}tau $ or $i = frac{{{ m{d}}q}}{{{ m{d}}t}}$ | |||
| 6 | Basic law of magnetism | Flux and voltage | $varphi left( t ight) = mathop smallint limits_{ - infty }^t vleft( tau ight){ m{d}}tau $ or $v = frac{{{ m{d}}varphi }}{{{ m{d}}t}}$ | |||
The fundamental equations, those that characterize the memristor, are Eqs. (1) and (2) as follows
$$v = Rleft( w ight)i,$$  | (1) |
$$frac{{{ m{d}}w}}{{{ m{d}}t}} = i,$$  | (2) |
where w is a state variable proportional to amounts of charge in the memristor and i is the current through the memristor. A frequency dependent (i, v) characteristic (hysteresis curve) will be obtained if the sinusoidal input is applied to the memristor. It was proven that the memristor is a fundamental element because the behaviour of the memristor is unique and could not be replicated by other fundamental elements[14]. So now there are four fundamental circuit elements instead of three, all are depicted in Table 1. In 1976, Chua and Kang generalized the memristor concept as memristive devices and systems[16] and characterized them by two of the most basic equations, Eqs. (3) and (4). Chua and Kang suggested some fingerprints and signatures for devices and systems to be memristive, such as the current–voltage characteristics of the memristor will give pinched hysteresis loops, as in Fig. 2, for any periodic input voltage v(t), the lobe area of pinched hysteresis loops reduces as the frequency of the input signal increases, and pinched hysteresis loops became straight lines as the frequency crosses a certain value[16, 17].
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Figure2.
(Color online) Frequency dependent pinched hysteresis I–V characteristics.
$$v = Rleft( {w,i} ight)i,$$  | (3) |
$$frac{{{ m{d}}w}}{{{ m{d}}t}} = fleft( {w,i} ight),$$  | (4) |
In a similar fashion, as the resistance of the resistor and the conductance of the conductor are linked, the memristance of the memristor and the memductance of the memductor are defined. The memristance of the memristor depends upon the amount of the charge passed through it and the memductance depends upon the amount of flux going through it. So mathematically the memristance can be obtained from the charge controlled memristor i.e. φ = fM (q).
$$varphi = {f_{ m M}}left( q ight).$$  | (5) |
Differentiating Eq. (5) w.r.t time
$$frac{{{ m{d}}varphi }}{{{ m{d}}t}} = frac{{ m{d}}}{{{ m{d}}t}}{f_{ m M}}left( q ight),$$  | (6) |
Eq. (6) can also be written as
$$frac{{{ m{d}}varphi }}{{{ m{d}}t}} = frac{{ m{d}}}{{{ m{d}}q}}{f_{ m M}}left( q ight)frac{{{ m{d}}q}}{{{ m{d}}t}},$$  | (7) |
or
$$vleft( t ight) = frac{{{ m{d}}{f_{ m M}}left( q ight)}}{{{ m{d}}q}}ileft( t ight),$$  | (8) |
$$vleft( t ight) = Mleft( q ight) cdot ileft( t ight),$$  | (9) |
where
$$Mleft( q ight) = frac{{{ m{d}}{f_{ m M}}left( q ight)}}{{{ m{d}}q}},$$  | (10) |
is the incremental memristance in Ohm units.
Similarly, mathematically the memductance can be obtained from a flux controlled memristor, q = gM (φ).
$$q = {g_{ m M}}left( varphi ight).$$  | (11) |
Now, differentiating Eq. (11) w.r.t time
$$frac{{{ m{d}}q}}{{{ m{d}}t}} = frac{{ m{d}}}{{{ m{d}}t}}{g_{ m M}}left( varphi ight).$$  | (12) |
It can also be written as
$$frac{{{ m{d}}q}}{{{ m{d}}t}} = frac{{ m{d}}}{{{ m{d}}varphi }}{g_{ m M}}left( varphi ight)frac{{{ m{d}}varphi }}{{{ m{d}}t}},$$  | (13) |
or
$$ileft( t ight) = frac{{{ m{d}}{g_{ m M}}left( varphi ight)}}{{{ m{d}}varphi }}vleft( t ight),$$  | (14) |
$$ileft( t ight) = Wleft( varphi ight)·vleft( t ight),$$  | (15) |
where
$$Wleft( varphi ight) = frac{{{ m{d}}{g_{ m M}}left( varphi ight)}}{{{ m{d}}varphi }},$$  | (16) |
is the incremental memductance of Siemens units.
It can be seen from Eqs. (10) and (16) that if the memristance is independent of state variable charge and the memductance (inverse of memristance) is independent of state variable flux, then the memristor will become a resistor and the memductance will become simple conductance. There is no difference in memristance and resistance if the memristor is linear. After the memristor theory, a hypothetical periodic table of 25 linear and non-linear circuit elements was presented by Chua in 1980[18]. This table has a memcapacitor, meminductor, and memristor along with three fundamental circuit elements (resistor, capacitor and inductor). The memcapacitor and meminductor were generalized but these are still to be realized[19]; however, the rest have only just been envisaged.
3.
Mathematical modeling of memristor
The memristor was fabricated for the first time and then modeled in HP’s lab in 2008 after about 38 years of its postulation[20]. After this successful endeavour, several memristor structures were fabricated and modeled for its better realization[21]. In their nonlinear micro and nano scale TiO2 model, Yang et al.[31] demonstrated that the switching polarity, rectification and conduction characteristics are determined by the distribution of oxygen vacancies at the platinum and TiO2 interfaces of the fabricated memristor. Contemporarily, based on the Simmons tunnel equations[32], Picket et al.[34] built a mathematical model of a memristor, which fully correlates the electrical and dynamic behaviour of the memristor and also sets a framework to describe the physical process involved in its resistive switchings. Yokopcic et al.[37] presented an improved memristor model, which is valuable in the designing of neuromorphic systems. Kvantisky et al.[38] tried to simplify the complexity of the Simmons tunnel model and gave a generic model, which is viably simulates many memristive devices. Moreover, Rak et al.[40] added another memristor micromodel, which is thoughtful in design and simulation of new memristor based circuits. Pershin et al.[41] developed a spice model of a memristor by introducing a threshold voltage, also they built models for a memcapacitor and a memductor. In order to understand and reveal the complex coupled electric-ionic conduction phenomena of the memristor, several models of a memristor have evolved. In this section, the linear memristor model[20], non-linear memristor model[32], the Simmons tunnel memristor model[34], the Yakopcic neuromorphic memristor model[37], and the TEAM model[38] are emphasized, since these models are helpful to perceive excellently the conduction behaviour and circuit designing aspects of the memristor.
3.1
Linear drift model
The linear model of a memristor was developed based on the fabricated structure of HP’s memristor in this model, a thin semiconductor metal oxide film (TiO2), consisting of two regions one deficient in oxygen (TiO2?x), say the doped region, and another with equally proportionate oxygen, say the insulating region, was sandwiched between two electrodes[20], as shown in Fig. 3. The oxygen deficient region (conducting) named RON and the insulating region ROFF were considered in a series.
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Figure3.
(Color online) Linear model of a memristor. Conducting and insulating layers are modeled as two series resistances.
$${R_{ m{T}}} = {R_{{ m{ON}}}}frac{{wleft( t ight)}}{D} + {R_{{ m{OFF}}}}left( {1 - frac{{wleft( t ight)}}{D}} ight),$$  | (17) |
where w(t) is the conductive width, and D is the total dimension of the device. The boundaries of the doped and un-doped regions, i.e. the values of RON and ROFF will vary according to the magnitude and polarity of the applied voltage across the device and the time interval up to which the voltage is applied. The applied voltage causes the oxygen vacancies to drift with dopants mobility μV. Thus, the voltage across the memristor is modeled as Eq. (18). The Blanc and Staebler relation (19)[22] of a dopant’s velocity and electric field is used to derive the state derivative relation (20). In order to obtain the memristance final relation (22) for the condition ROFF
$$Vleft( t ight) = left{ {{R_{{text{ON}}}}frac{{wleft( t ight)}}{D} + {R_{{text{OFF}}}}left[ {1 - frac{{wleft( t ight)}}{D}} ight]} ight}ileft( t ight),$$  | (18) |
$$v = {mu _V}E,$$  | (19) |
$$frac{{{ m{d}}wleft( t ight)}}{{{ m{d}}t}} = {mu _V}frac{{Vleft( t ight)}}{D},$$  | (20) |
$$Vleft( t ight) = {R_{{ m{OFF}}}}left[ {1 - {mu _V}frac{{{R_{{ m{ON}}}}}}{{{D^2}}}qleft( t ight)} ight]ileft( t ight),$$  | (21) |
$$Mleft( q ight) = {R_{{ m{OFF}}}}left[ {1 - {mu _V}frac{{{R_{{ m{ON}}}}}}{{{D^2}}}qleft( t ight)} ight].$$  | (22) |
3.1.1
Window function
Although the mobility of dopants and device length show significant effects on the linear and nonlinear kinetics inside a memristor[23], it has been seen in the simulation results (see Fig. 4) of the linear model that the conducting width and hence the memristance grow beyond their physical limits. The physical limits of normalized conducing width and memristance are taken to be 1 and 100 Ω in the saturation region (a), whereas they are 0 and 16 kΩ in the depletion region (b). It can be seen in the saturation region of Fig. 4(a) that the normalized conducting width or normalized state variable (x = w/D) grows up to 1.2 and the memristance decreases ?2 kΩ. In the depletion region of Fig. 4(b), ‘x’ reaches below ‘0’ and the corresponding memristance extends above 16 kΩ, which is not feasible. So this model requires a window function, which is multiplied with a derivative of state variable f(w, I) to limit these at the boundaries. There are many window functions available in the literature to achieve the nonlinear drift of dopants and the physical limit.
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Figure4.
(Color online) Excess growth of conductive thickness and the corresponding memristance from their limiting value for RON = 100 Ω, ROFF = 16 kΩ, winitial = 5 nm, μv = 10?14 m2/(V·s), at v(t) = 2 V sinusoidal and 100 Hz (a) in saturation {x→1, M(q)→100 Ω} and (b) in depletion {x→0, M(q)→16 kΩ}.
a) Strukov’s window
Strukov’s window function (23)[20] restrict w, M(q) at the boundaries but another problem arose of sticking states. It gives a zero value at w = 0 and w = D, so the state derivative or velocity becomes 0. Thus, even though voltage is reversed, the state variable does not return back. Means states are locked and this problem is known as the sticking states problem.
$$fleft( w ight) = frac{{wleft( {1 - w} ight)}}{{{D^2}}}.$$  | (23) |
Since a memristor has nanoscale dimensions, therefore even at very small applied voltage, an exponential field arises. Thus, non-linear drift of dopants is also a specific property of the memristor[24]. This window function lacks non-linearity, since its behaviour is like a rectangular window. So, there is a need of a non-linear window function that accounts for the non-linear drift of dopants at the boundaries.
b) Joglekar’s window
This window function (24) well approximates linear ionic drift in the range 0 < w < D and non-linear ionic drift at the boundaries[25].
$$fleft( x ight) = 1 - {left( {2x - 1} ight)^{2p}},$$  | (24) |
where x = w/D and ‘p’ is a positive integer, which controls the linearity and non-linearity of the window function and is known as the control parameter. This window does not resolve the state sticking problem. Locking of the state is seen in Fig. 5(a) in the linear memristor model by implementing Jogelkar’s window function. To verify the locking state, a voltage (±1 V sin2 (2πft)) is applied. Then it can be observed that though at t = 25 s, the voltage changes its polarity but the state variable does not return back and remains stuck at 1. Further, this window function is generalized to consider flexibility and non-linearity[26].
c) Biolek’s window
Biolek proposed a new window function (25) that resolved the problem of the sticking state by including the memristor current ‘i’ together with state variable ‘x’ and ‘p’[27], as shown in Fig. 5(b). It can be seen that the state variable varies according to the polarity of the applied voltage, i.e., it does not get stuck at any particular state. Here a positive current is correlated with the increasing doped width and negative current correlated with decreasing the doped width.
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Figure5.
(Color online) (a) Boundary locked: state variable does not change its state as the polarity of applied voltage changes using Jogelkar’s window. (b) Boundary unlocked: state variable changes its states as the polarity of applied voltage changes for Biolek’s window function.
$$fleft( x ight) = 1 - {left( {x - { m{sgn}}left( { - i} ight)} ight)^{2p}},$$  | (25) |
where sgn(i) = 1, when i ≥ 0, sgn(i) = 0, when i ≤ 0.
d) Prodromakis’s window
This window function (26)[28] is well approximated by the non-linearity issue at the boundaries by utilizing the quadratic equation in its expression. State variable and memristance variations are shown in Figs. 6(a) saturation and 6(b) depletion regions. It can be observed that both state variable and the corresponding memristance are restricted within the device’s physical dimensions. The parameters are kept the same in Fig. 4 for the simulation of the linear model without a window function; the state variable does not grow beyond ‘1’ in saturation and below ‘0’ in depletion. Also the memristance is limited in between 100 to 8000 Ω in saturation and 8 to 16 kΩ in depletion; however, it also fails to resolve the sticking of states at boundaries, since f(0, 1) = 0. Here p and j are control parameters.
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Figure6.
(Color online) Prodromakis’s window function limits the boundaries growth within the device’s physical limit and includes non-linearity at the (a) saturation and (b) depletion boundaries in the linear memristor model for the same parameters used in Fig. 4.
$$fleft( w ight) = jleft{ {1 - {{left[ {{{left( {frac{w}{D} - 0.5} ight)}^2} + 0.75} ight]}^p}} ight}.$$  | (26) |
e) Zha’s window
Zha’s window function (27)[29] was derived as a combination of Biolek’s and Prodromakis’s window functions. It appraises the non-linearity as well as abolishes the stuck state problem, but the discontinuity problem persists due to the use of a step function.
$$fleft( w ight) = jleft( {1 - {{left{ {0.25{{left[ {x - {text{sgn}}left( { - i} ight)} ight]}^2} + 0.75} ight}}^p}} ight),$$  | (27) |
sgn(i) = 1, when i ≥ 0, sgn(i) = 0, when i ≤ 0.
The stochastic variations of dopants are also modeled by a current as well as state dependent window function[30]. It poses an exponential function, which provides an ability to realize an exponential electric field developed in a nanoscale memristor for small voltages.
3.2
Nonlinear memristor model
A 50 nm metal oxide of TiO2 film was fabricated between two Platinum electrodes and experimentally manifested memristive switching in nanoscale devices by Yang and Picket[31]. The oxygen vacancies (TiO2?x) were created in the right half of TiO2 by an annealing process. Two metal/oxide interfaces of the device were modeled by an ohmic interface (in case of heavy doping or TiO2?x) Fig. 7(a). and rectifying interface (in case of low doping or TiO2) Fig. 7(b). The model has a highly nonlinear behaviour, which was presented by current-voltage relation (28). The first term of the equation characterizes the ON state and the second term is the estimation of rectifier I–V expression and characterizes the OFF state of the memristor.
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Figure7.
(Color online) (a) Memristor device structure and (b) its equivalent non-linear circuit[31].
$$ileft( t ight) = w{left( t ight)^n}beta sinh left( {alpha vleft( t ight)} ight) + chi left[ {exp left( {gamma vleft( t ight)} ight) - 1} ight],$$  | (28) |
where α, β, γ, and χ are fitting parameter, ‘n’ determines the effect of state variable on current. State derivative equation (29) carries a window function f(w) along with a linear voltage function g(v(t)).
$$frac{{{ m{d}}w}}{{{ m{d}}t}} = afleft( w ight)gleft( {vleft( t ight)} ight).$$  | (29) |
3.3
Simmons tunnel memristor model
In 1963, Simmons formulated a generalized expression for electric tunneling through an insulating film separated by two similar electrodes (30)[32], and also for dissimilar electrodes[33]. The derived formulae deployed a rectangular barrier for similar electrodes and a trapezoidal barrier for dissimilar electrodes including image forces. Based on these expressions, the Simmons tunnel model for a memristor was developed[34]. A conductive channel of TiO2?x was created by the electro-formation method and a thin electric tunneling gap was formed at one interface, see Fig. 8(a). The tunneling gap ‘w’ was modeled by a voltage source vg and the conductive channel was modeled by series resistance Rs, so the tunneling current through the device is expressed as Eq. (36) with gap voltage.
$$i = frac{{{j_0}A}}{{Delta {w^2}}}left{ {varphi _I}{{ m{e}}^{ - Bsqrt {{varphi _I}} }} - left( {{varphi _I} + eleft| {{v_{ m{g}}}} ight|} ight){{ m{e}}^{ - Bsqrt {{varphi _I} + eleft| {{v_{ m{g}}}} ight|} }} ight},$$  | (30) |
where
m g}}}
ight|left( {frac{{{w_1} + {w_2}}}{w}}
ight) - left( {frac{{1.15lambda w}}{{Delta w}}}
ight)ln left( {frac{{{w_2}left( {w - {w_1}}
ight)}}{{{w_1}left( {w - {w_2}}
ight)}}}
ight)$
m g}}}
ight|} }}
ight)$
The gap voltage is obtained by the following relation
$$v = {v_{ m g}} + ileft( t ight){R_{ m s}},$$  | (31) |
where v is the applied voltage. State derivative equations are given by Eqs. (32) and (33) for OFF switching and ON switching respectively. The
m {off}}}}}}
ight){
m{exp}}frac{w}{{{w_{
m c}}}}$
$$frac{{{ m{d}}w}}{{{ m{d}}t}} = {f_{{ m{off}}}}sinh left( {frac{i}{{{i_{{ m{off}}}}}}} ight){ m{exp}}left[ - { m{exp}}left(frac{{w - {a_{{ m{off}}}}}}{{{w_{ m c}}}} - frac{{left| i ight|}}{b} ight) - frac{w}{{{w_{ m c}}}} ight],;;;i > 0,$$  | (32) |
$$frac{{{ m{d}}w}}{{{ m{d}}t}} = {f_{{ m{on}}}}sinh left( {frac{i}{{{i_{{ m{on}}}}}}} ight){ m{exp}}left[ - { m{exp}}left(frac{{w - {a_{ m {on}}}}}{{{w_{ m c}}}} - frac{{left| i ight|}}{b} ight) - frac{w}{{{w_{ m c}}}} ight],;;;i < 0.$$  | (33) |
This model is an accurate but quite complex model of the memristor since current voltage equations are not explicit to each other.
3.3.1
Simmons spice model with rectangular barrier
A spice model on the basis of the Simmons tunnel memristor model for similar electrodes was developed[35]. Here the barrier of the tunneling gap is rectangular since similar electrodes have an equal work function that causes the same barrier height. In this spice model, state derivative Eqs. (32) and (33) were modeled by two different current controlled sources Goff and Gon. Whereas increasing and decreasing the tunneling width was modeled by the voltage across capacitor Fig. 8(b). In this spice model, it was seen that the ON switching current was 20% more than that of experimental results for a certain voltage.
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Figure8.
(a) Memristor device structure of the Simmons tunnel model[34]. (b) Spice modeling of Simmons tunnel’s tunneling width by capacitor and state variable derivatives for OFF and ON switching by current sources Goff and Gon[35].
3.3.2
Simmons spice model with trapezoidal barrier
The spice model of the Simmons tunnel for similar electrodes[35] was further extended to dissimilar electrodes[36]. Two different electrodes with different work functions create a trapezoidal barrier instead of a rectangular barrier for the same electrodes, as shown in Fig. 9. The extended model was based on electric tunnel effects of a dissimilar electrode derived by Simmons[33]. In this model, a parallel memcapacitor with a memristor was accounted and showed that memcapacitance is an inherent property of the memristor. The operating frequencies determined the behaviour of the model as a memcapacitor or memristor.
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Figure9.
Different work function of two metal electrodes resulting in a trapezoidal barrier in thin insulating film[36].
3.4
Yakopcic neuromorphic memristor model
Yakopcic proposed a mathematical model[37] by identifying the disparities of previously reported models and published device characterization. This model bore various fitting parameters (34) to provide more flexibility to the device structure. Derivative of state variable (35) is a multiplication of composite functions, first is g(V(t)), which provides the programming threshold voltage and includes instant phase transitions constants Ap, An, and the second is window function f(x(t)).
$$Ileft( t ight) = left{ {begin{array}{*{20}{c}}{{a_1}xleft( t ight)sinh left( {bVleft( t ight)} ight),;;;;;;;;;;Vleft( t ight) geqslant 0,}{{a_2}xleft( t ight)sinh left( {bVleft( t ight)} ight),;;;;;;;;;;Vleft( t ight) leqslant 0,}end{array}} ight.$$  | (34) |
$$frac{{{ m{d}}x}}{{{ m{d}}t}} = gleft( {Vleft( t ight)} ight)fleft( {xleft( t ight)} ight),$$  | (35) |
$$gleft( {Vleft( t ight)} ight) = left{ begin{array}{l}{A_{ m p}}left( {{{ m e}^{Vleft( t ight)}} - {{ m e}^{{V_{ m p}}}}} ight),;;;;;;;;;Vleft( t ight) > {V_{ m p}}, - {A_{ m n}}left( {{{ m e}^{ - Vleft( t ight)}} - {{ m e}^{{V_{ m n}}}}} ight),;;;;;;;Vleft( t ight) < - {V_{ m n}},0,;;;;;;;;;;;;;;;;;;;;;;;;;; - {V_{ m n}} leqslant Vleft( t ight) leqslant {V_{ m p}}.end{array} ight.$$  | (36) |
In this model, spikes obtained by a linear DC sweep input were more similar to neural spikes rather than a sinusoidal input. Thus, it was more emphasized for the neuromorphic application. The model’s validity was tested with TiO2, Si, Ag, and the chalcogenide based memristor. Its validity was also tested with spintronic devices, RRAM devices, and PCM (phase change memory).
3.5
Threshold adaptive memristor (TEAM) model
TEAM model tried to simplify the complexity of the Simmons tunnel model. It has two distinct current, voltage relations one for linear drift (37) and another for nonlinear drift (38)[38]. Here the state derivative Eq. (40) is modeled as the multiplication of two polynomials, one is the function of the device current and the other is a function of state variable w.
$$vleft( t ight) = left[ {{R_{{ m{ON}}}} + frac{{{R_{ m {OFF}}} - {R_{ m {ON}}}}}{{{w_{{ m{off}}}} - {w_{{ m{on}}}}}}left( {w - {w_{ m {on}}}} ight)} ight] ileft( t ight),$$  | (37) |
$$vleft( t ight) = {R_{ m {ON}}}{{ m e}^{left( {frac{lambda }{{{w_{ m {off}}} - {w_{ m {on}}}}}} ight)left( {w - {w_{ m {on}}}} ight)}}ileft( t ight),$$  | (38) |
where w∈[won, woff], and RON and ROFF are bounded resistances and satisfy the following relation
$$frac{{{R_{ m {OFF}}}}}{{{R_{ m {ON}}}}} = {{ m e}^lambda },$$  | (39) |
$$frac{{{ m{d}}wleft( t ight)}}{{{ m{d}}t}} = left{ begin{array}{l}{k_{{ m{off}}}}{left( {frac{{ileft( t ight)}}{{{i_{{ m{off}}}}}} - 1} ight)^{{alpha _{{ m{off}}}}}} {f_{{ m{off}}}}left( w ight),;;;;0 < {i_{{ m{off}}}} < i,0,qquadqquadqquadqquadqquad {i_{{ m{off}}}} < i < {i_{{ m{on}}}},{k_{{ m{on}}}}{left( {frac{{ileft( t ight)}}{{{i_{{ m{on}}}}}} - 1} ight)^{{alpha _{{ m{on}}}}}} {f_{{ m{on}}}}left( w ight),;;;;;{ m{}}i < {i_{{ m{on}}}} < 0,end{array} ight.$$  | (40) |
where ioff & ion are threshold currents and koff (+) ve, kon (?) ve, αoff, αon are constants. foff (w) and fon (w) are proposed as the window function, which are not necessarily the same and given as
m{off}}}}left( w
ight) = {
m{exp}}left[ { - {
m{exp}}left( {frac{{w - {a_{{
m{off}}}}}}{{{w_c}}}}
ight)}
ight]$
m{exp}}left( { - frac{{w - {a_{{
m{on}}}}}}{{{w_{
m c}}}}}
ight)}
ight]$
This model does not have a scaling factor in its window, but this model can be extended for an insulating layer separated by dissimilar electrodes. Its spice model is the same as that of the Simmons tunnel model except it bore two additional anti parallel diodes in Fig. 10. The TEAM model is further extended as the voltage threshold adaptive memristor (VTEAM) model[39] and makes it a voltage controlled device.
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Figure10.
Micro spice TEAM model[38].
3.6
Some more spice memristor models
In order to simulate the behaviour of a memristor, spice plays a key role and hence several spice models are available in the literature. A SPICE macro model for the memristor can be helpful in designing and testing of new circuits built with a memristor[40]. Although this model was quite fast and stable within the valid range of the parameters, it was unable to pick the initial state of the memristor. Soft and hard switching are separately considered by another voltage controlled SPICE model[41]. Instead of the window function, a ternary function is exploited to limit the boundaries and thus the memristance of the device. A methodology to develop various spice models for mem circuit elements, e.g. memristor, memcapacitor, and meminductor, is well described by Biolek et al.[42]. Vourkas et al. gave a voltage controlled SPICE model[43] with a programmable threshold. This model provides the best fitting with the characterization data. Here, two SPICE sub-circuits are used to solve boundary conditions.
4.
Memristor in memory design
The memristor, either as a crossbar or discrete has vital applications in analog and digital electronics. It is widely used in the designing of neuromorphic circuits[44], chaotic circuits[45], logic gates[46], variable gain amplifiers[47], oscillators[48, 49], polarity-dependent memory switch[50], multilevel memory[51], logic circuits[52], and redox resistive memories[53]. Non-volatile and nanoscale properties are a memristor’s merits in comparison to the other memory cell structure and made the memristor more promising in memory designing. Here some memory cells are summarized that utilize a memristor in their design. The significant outcomes and various parameters such as write/read time, energy consumed, static noise margin, and write/read delay of these memory cells are briefed and compared to traditional memories.
4.1
Hybrid memory cell
A hybrid memory cell consists of two ambipolar transistors and a memristor[54], see Fig. 11. This cell has a fast read/write operation and operates at the low temperature as compared to NAND/NOR-based Flash memory[55] of CMOS; Table 2 compares a hybrid memory cell with NAND/NOR Flash. An ambipolar transistor will behave as a NMOS transistor if its polarity gate (shown by an arrow) voltage is ‘0’, and behaves as a PMOS transistor if polarity gate voltage is ‘1’. The write time of the hybrid memory cell is measured by observing the memristance of the memristor, so the write time is the time, required to set the memristor to its desired memristance state. Fig. 12(a) shows the memristance range versus write time variations, it can be seen that for the memristance range 100–19 kΩ the required write time is 219 ns. To write ‘1’ initially the memristor should be in OFF state for node voltage VA > VB, and this condition came when BL = VDD and BL’ = GND. The conductive width moves from left to right and memristance goes from ROFF to RON. Similarly, a write ‘0’ operation is performed when BL = GND and BL’ = VDD. This makes node voltage VB > VA and memristance go from RON to ROFF. The memristance variation corresponding to write ‘1’ and write ‘0’ operation is shown in Fig. 12(b). Read operation or data of the memory cell can be obtained by sensing the voltage difference between bit lines in high memristance state ROFF or low memristance state RON of the memristor. Therefore, consecutive read operations occur, when memristance changes its state. Thus, the read time is given as
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Figure11.
Hybrid memory cell exploiting a memristor and two ambipolar transistors[54].
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/7/PIC/17080019-12.jpg'" class="figure_img" id="Figure12"/>
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Figure12.
(a) Variation of the write time of hybrid memory cell for a range of memristance. (b) Consecutive Write ‘1’ and Write ‘0’ operation with changing memristance values.
$${T_{ m R}} = {T_{ m W}}/2N,$$  | (41) |
where TW is the write time and N is the number of consecutive read operations. So, the calculated read time for a hybrid memory cell is 0.095 ns for N = 100 and TW = 219 ns. The drawback of this memory cell was that it required a refresh operation after successive read operations because of a low threshold voltage and thus the low voltage across the memristor.
| Parameter | Hybrid memory cell | NAND flash[55] | NOR flash[55] |
| Write time (ns) | 21 | 106 | 103 |
| Read time (ns) | 1.095 | 105 | 15 |
| Write operating voltage (V) | 0.9 | 15 | 15 |
| Read operating voltage (V) | 0.9 | 1.8 | 1.8 |
Table2.
Comparison of hybrid memory cell with NAND/NOR flash.
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| Parameter | Hybrid memory cell | NAND flash[55] | NOR flash[55] |
| Write time (ns) | 21 | 106 | 103 |
| Read time (ns) | 1.095 | 105 | 15 |
| Write operating voltage (V) | 0.9 | 15 | 15 |
| Read operating voltage (V) | 0.9 | 1.8 | 1.8 |
4.2
1T1R memory cell and array
The One Transistor One Memristor (1T1R) shown in Fig. 13 is the basic structure of the large memory array[56] that provides high density, non-volatility, low power consumption, and has great potential to replace traditional Flash. The 1T1R has the same structure as the DRAM, the only difference is that it has a memristor in place of the capacitor. To perform the read operation the load line (LL) charges the bit line (BL) via a memristor and access transistor. The write operation is performed by changing the memristance state of the memristor. In the array, the Word Line (WL) is used to select a particular cell and the Bit Line (BL) is shared in a column to read and write. An energy and performance model was developed and compared to the proposed architecture utilizing the TiO2 and HfO2 base memristor. The amount of energy consumed during a write and read operation in different components of the TiO2 based RRAM array is shown in Fig. 14. In order to store a 3 bit/cell in a RRAM array, it is determined that the write energy, 4.06 pJ/b is consumed for 100 ns write access time as shown in Fig. 14(a). Whereas the read energy consumed by the RRAM array is shown in Fig. 14(b), which needed 188 fJ/b for 1ns read access time to store n = 3 bit/cell. The optimized HfO2 based array utilized 365 and 173 fJ/b energy for 1 and 200 ns write and read access time respectively, when storing the 3 bit/cell. This memory cell requires a refresh operation after successive read operations because of the low threshold voltage. So this challenge can be accepted in the design of memristor based memory cells.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/7/PIC/17080019-13.jpg'" class="figure_img" id="Figure13"/>
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Figure13.
Unit 1T1R cell of array structure[56].
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Figure14.
(Color online) Energy consumption in several components of TiO2 based RRAM array for multiple (n) bit storage during (a) write operation, and (b) read operation.
4.3
Memristor in SRAM
SRAM is frequently used in today’s memory designing, but it lags because of its volatile nature and dissipates more energy in standby mode due to leakage. The memristor geared up its uses in memory designing by providing it non-volatility, low leakage, and Instant ON features. There are various ways by which a memristor is used in SRAM design 7T1R[57] as shown in Fig. 1(a), 8T2R[58] Fig. 16(a), 9T2R[59] Fig. 1(b). 7T1R which have one 1T1R connected to data the nodes of the conventional 6T SRAM cell, so when the power goes, the state of the node is stored in RRAM1 or the memristor and restored back to the node through transistor Q7, when power comes back. Since the Static Noise Margin (SNM) is found to be an important metric in defining the stability and robustness of a memory cell, so in order to measure the Write SNM (WSNM), the 7T1R butterfly curve is plotted in Figs. 15(b) and 15(c) to store ‘0’ and ‘1’ respectively at 32 nm technology. The measured WSNM of Figs. 15 (a) and 15(b) are 0.297 and 0.313 V, which are less than the WSNM of 6T SRAM which had a value of 0.390 V[60]. Whereas 8T2R and 9T2R have WSNMs of 0.322 and 0.332 V respectively, these values are more than that of 7T1R. The WSNM of 7T1R can be increased by increasing the memristance of the RRAM1.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/7/PIC/17080019-15.jpg'" class="figure_img" id="Figure15"/>
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Figure15.
(Color online) (a) Basic structure of 7T1R SRAM[57]. (b) WSNM of 7T1R SRAM for storing ‘0’. (c) WSNM of 7T1R SRAM for storing ‘1’.
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Figure16.
More configurations of SRAM utilizing memristor. (a) 8T2R SRAM[58]. (b) 9T2R SRAM[59].
8T2R consists of two 1T1R connected to the data nodes D and DN and each is programmed to a high resistance state and a low resistance state. 9T2R have one more transistor in addition with two 1T1R, which is used to restore the data from an access node. One end of both is connected to a single bit line and the other end with a common source line, i.e. sources of Q7 and Q8 connected to the source line for programming of RRAM. A comparison of an average read delay and write delay arose in 6T SRAM, 7T1R SRAM, 8T2R SRAM, and 9T2R SRAM, which are plotted in Fig. 17 with various featured sizes. It is found that the average read and write delays for 6T SRAM[60] and 7T1R SRAM are almost comparable to each other, whereas 9T2R shows maximum read and write delay.
onerror="this.onerror=null;this.src='http://www.jos.ac.cn/fileBDTXB/journal/article/jos/2018/7/PIC/17080019-17.jpg'" class="figure_img" id="Figure17"/>
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Figure17.
(Color online) (a) Average read delay, (b) average write delay of various considered SRAM cells configuration with different feature size.
| Parameter | Traditional memories | Other emerging technologies | ||||||||
| DRAM | SRAM | NOR FLASH | NAND FLASH | FeRAM | MRAM | PCRAM | STTRAM | MEMRISTOR | ||
| Cell element | 1T1C | 6T | 1T | 1T | 1T1C | 1T1R | 1T1R | 1T1R | 1T1R | |
| Feature size (nm) | 36–65 | 45 | 90 | 22 | 180 | 65 | 45 | 40 | 9 | |
| Density (Gbit/cm2) | 0.8–13 | 0.4 | 1.2 | 52 | 0.14 | 1.2 | 12 | 15 | 154–309 | |
| Read time (ns) | 2–10 | 0.2 | 15 | 100 | 45 | 35 | 12 | 35 | 8.5 | |
| Write time (ns) | 2–10 | 0.2 | 107 | 106 | 65 | 35 | 100 | 35 | 10 | |
| Retention time | 4–64 ms | N/A | 10 years | 10 years | 10 years | > 10 years | > 10 years | > 10 years | > 10 years | |
Table3.
Comparison of various parameters of existing memory structures extracted from[12, 56] .
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| Parameter | Traditional memories | Other emerging technologies | ||||||||
| DRAM | SRAM | NOR FLASH | NAND FLASH | FeRAM | MRAM | PCRAM | STTRAM | MEMRISTOR | ||
| Cell element | 1T1C | 6T | 1T | 1T | 1T1C | 1T1R | 1T1R | 1T1R | 1T1R | |
| Feature size (nm) | 36–65 | 45 | 90 | 22 | 180 | 65 | 45 | 40 | 9 | |
| Density (Gbit/cm2) | 0.8–13 | 0.4 | 1.2 | 52 | 0.14 | 1.2 | 12 | 15 | 154–309 | |
| Read time (ns) | 2–10 | 0.2 | 15 | 100 | 45 | 35 | 12 | 35 | 8.5 | |
| Write time (ns) | 2–10 | 0.2 | 107 | 106 | 65 | 35 | 100 | 35 | 10 | |
| Retention time | 4–64 ms | N/A | 10 years | 10 years | 10 years | > 10 years | > 10 years | > 10 years | > 10 years | |
5.
Conclusion
Here, a comprehensive study of the memristor is presented, starting from its existence as a fourth fundamental electrical component to the memory applications stage. Various window functions are implemented and discussed in order to better understand their behaviour. It is found that Biolek’s window function removes the sticking of states and Prodromakis’s window function provides better non-linearity at the boundaries. Its various models are compared in detail with their merits and demerits. The Simmons tunnel model is one of the most accurate models among all the available models, but it is quite complex. A memristor’s nanoscale size makes it more difficult to understand its basic tunneling mechanism and coupled electric-ionic motion. So there is a need for an accurate mathematical model which has characteristics that best match with the experimental data and its behaviour. Although there are several advantages of memristor-based memory cells, there are certain challenges remaining. Such as, it is seen that a hybrid memory cell requires an additional refresh operation. The 1T1R needed a read operation before every write operation and SRAM cells with the memristor need to be explored. This paper is very helpful to researchers in building the basic concept of modeling and memory applications of the memristor.
