1.
Introduction

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have been scaled down in the last four decades, which opens the way for improvements in the switching speed, density, functionality and cost of integrated chips. But nanotechnology now faces problems that together result in high power consumption of devices, difficulty in further reducing the supply voltage, and leakage current that degrade the switching ratio of ‘ON’ and ‘OFF’ current^[1]. Recently, researchers highlighted the need for new devices that can compete with CMOS technology^{[2, 3]}. In case of a MOSFET, the charge carriers transfer from the source region to the channel region over a barrier by a process that is called thermionic emission. The inter band tunneling is the primary mechanism in tunnel FET in which charge carriers transfer from one energy band to another energy band. In 1934, the first time tunneling mechanism was identified by Zener^[4].



Tunnel FET is a semiconductor device in which the source–drain current is controlled by the gate and operates under a reverse bias condition. The charge carriers transfer into the channel only in the energy window ??, because from the source the energy distribution of charge carriers is limited^[5]. On the other hand, with a minor change in the gate voltage, the valence band in the channel can be raised, which effectively reduces the tunneling width. In a tunnel FET, as a significance of the band to band tunneling (BTBT) mechanism, the SS varies according to the applied gate and source bias increases with the gate-to-source bias. There are better voltages scaling in the tunnel FET as compared to MOSFET because the SS remains less than 60 mV/decade above many orders of magnitude of drain current^{[6, 7]}.



In the case of tunnel FETs, I_ON critically depends on the transmission probability, T_WKB, of the inter band tunneling barrier; therefore, it is a big challenge to realize high ON currents in tunnel FET. T_WKB can be calculated using the Wentzel–Kramer–Brillouin (WKB) approximation^[8],

$${T_{_{ m{WKB}}}} approx exp left( { - frac{{4lambda sqrt {2{m^*}} sqrt {{E_{ m{g}}}^3} }}{{3qhbar ({E_{ m{g}}} + Delta textit{?} )}}} ight),$$

(1)

where both effective mass m* and the energy bandgap E_g depend on the material system. Here, λ describes the spatial extent of the transition region at the source–channel interfaces known as the screening tunneling length and to be determined by the specific device geometry and doping profile, q is the charge of the electron and h is the Plank constant.



III–V semiconductor MOSFETs are attractive candidates for ultimately scaled technology nodes because III–V compounded semiconductors have higher carrier mobility^{[9, 10]}.



In this paper, we investigated the physics, design and optimization of DG tunnel FET, and considered the potentials and drawbacks of this energy-efficient device that could bring down the voltage supply of devices. Further, we compared its performance in various material systems such as silicon, and group III–V compounds like GaAs, Al_xGa_1?xAs and CNT.

2.
Previous study

In a critique review, we focussed on the TFET. Boucard et al. in 2007 had proposed a tunnel FET (double gate) device with high-k gate dielectric and they simulated the device with the gate length 50 nm, finding that the results of the I_on/I_off ratio were high as compared to traditional MOSFET^[8]. Zhang et al. in 2012 proposed a systematic charge model for double gate DG-TFETs in which the terminal charge and accompanying capacitances in terms of terminal voltages were considered. The experimental demonstrations show that a 100/0 channel charge partition scheme is beneficial in the case of TFETs, but found to be different in the case of MOSFETs^[11]. Appenzeller et al. in 2005, implemented the first tunneling device based on carbon nanotube, which had a SS (subthreshold swing) of less than 60 mV/dec^[6]. Many researchers have shown great intrest in tunnel FET devices in the last few years due to subthreshold slope (SS) that remains less than 60 mV/decade. The tunnel FET reduces the power dissipation and supply voltage V_DS due to the BTBT current transport mechanism^[12–15]. This device has a limitation of a low ON current, which results in low performance. Researchers are continuing their efforts to improve the ON current and SS by using various channel materials and structural engineering techniques. One method to increase the ON current is to use a DG structure as a replacement for the single gate^[16–19]. The DG structure is benefcial for better field control to enhance the volume inversion, which futher increases the ON current two times larger than the single gate structure, and it also improves the delay saturation in output characterstics^{[11, 20]}. Semiconducting CNT can be used as a channel material in a field-effect transistor (FET)^{[21, 22]}.

3.
Structure of device DG tunnel FET

The device structure of a DG tunnel FET is shown in Fig. 1. Length of channel (L_C), source length (L_S) and drain length (L_D) are the same and are equal to 50 nm, while the channel thickness (t_ch = 10 nm). The device has been simulated by using the SILVACO ATLAS TCAD device simulator^[5]. The high-k (HfO₂) has been used as an insulator for the present work. Fig. 2 shows the I_DS–V_GS characteristics of DG tunnel FET designed with Si as the channel material. For validating its performance, a comparison has been made with existing device characteristics^[8]. The device parameters as adopted from Ref. [8] are the work function of the gate-metal = 4.4 V, the doping concentration for N-type = 5 × 10¹⁸ cm^–3, P-type = 5 × 10²⁰ cm^–3, and intrinsic = 5 × 10¹⁵ cm^–3. The characteristics of the proposed device and Ref. [8] are in close agreement, which demonstrates the performance of the device. The properties of different channel materials used in DG tunnel FET for comparison are given in Table 1. Al_xGa_1?xAs is a tertiary semiconductor material with very close lattice constant as GaAs, but having a larger bandgap. The mole fraction x is a number ranging from 0 to 1. Thus, it represents an alloy between binary GaAs and AlAs. Figs. 3(a)–3(c) show the simulated schematic views of the DG tunnel FET with different channel materials.






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Figure1.
Schematic diagram for DG tunnel FET with high-k dielectric.






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Figure2.
(Color online) I_DS–V_GS characteristic of design DG tunnel FET and the existing device^[6].






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Figure3.
(Color online) Simulated schematic view of DG tunnel FETs with various channel materials. (a) Silicon. (b) GaAs. (c) Al_xGa_1?xAs.

4.
Results and discussion

Fig. 4 shows the variation of drain current with respect to gate voltage for different channel materials Si, Al_xGa_1?xAs and GaAs. As gate voltage increases the drain current increases due to an increase in the inversion charge density. It is inferred from Fig. 4 that the drain current of the GaAs based device is higher as compared to Si and AlGaAs. This is due to a higher mobility of charge carriers in GaAs (Table 1), which inturn increases the drain current.

Property	Si	GaAs	AlxGa1?xAs	CNT
Dielectric constant	11.9	13.1	12.90?2.84x	4.8
Energy gap at 300 K (eV)	1.12	1.424	1.422 eV + 1.2475x	0.75
Intrinsic carrier concentration (cm?3)	1.45 × 1010	1.79 × 106	2.1 × 105	–
Mobility (Drift) μn (cm2/(V·s))	1500	8500	8.1?2.2x + 104x2	79 000
Mobility (Drift) μp (cm2/(V·s))	475	400	370?970x + 740x2	79 000
Thermal conductivity at 300 K (W/cm·°C)	1.5	0.46	0.55?2.12x + 2.48x2	6600

Table1.
Properties of the various channel materials used in SILVACO ATLAS TCAD simulation.



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Property	Si	GaAs	AlxGa1?xAs	CNT
Dielectric constant	11.9	13.1	12.90?2.84x	4.8
Energy gap at 300 K (eV)	1.12	1.424	1.422 eV + 1.2475x	0.75
Intrinsic carrier concentration (cm?3)	1.45 × 1010	1.79 × 106	2.1 × 105	–
Mobility (Drift) μn (cm2/(V·s))	1500	8500	8.1?2.2x + 104x2	79 000
Mobility (Drift) μp (cm2/(V·s))	475	400	370?970x + 740x2	79 000
Thermal conductivity at 300 K (W/cm·°C)	1.5	0.46	0.55?2.12x + 2.48x2	6600

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Figure4.
(Color online) I_DS–V_GS characteristic of DG tunnel FET for various channel materials: Si, GaAs and Al_xGa_1?xAs.




Fig. 5 shows the variation of drain current (log scale) with respect to gate voltage for different channel materials viz Si, Al_xGa_1?xAs, GaAs. OFF-state current, subthreshold steepness, and threshold voltage (V_t) of devices based on Si, Al_xGa_1?xAs and GaAs have been found and summerized in Table 2. It can be inferrred from the results that for Al_xGa_1?xAs based device, SS is low and I_ON/I_OFF ratio is high as compared to other devices (Table 2). Fig. 6 shows the energy band diagram of DG tunnel FET for various channel materials viz Si, Al_xGa_1?xAs and GaAs in ON state. Dielectric (t_ox) = 3 nm (physical) and L_intrinsic = 50 nm. Drain doping (n⁺) = 5 × 10¹⁸ cm^?3 and source doping (p⁺) = 5 × 10²⁰ cm^?3.






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Figure5.
(Color online) I_DS–V_GS characteristic in log scale of DG tunnel FET for various channel materials Si, GaAs, Al_xGa_1?xAs.






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Figure6.
(Color online) Energy-band diagram of DG tunnel FET for various channel material Si, Al_xGa_1?xAs, GaAs in ON state.

Device with different channel materials	IOFF	ION	ION/IOFF	SS (mV/decade)	Vt
Silicon	4.11 × 10?17	17.7 × 10?5	4.32 × 1012	30.7985	0.682591
GaAs	1.16 × 10?18	36.6 × 10?5	3.15 × 1014	16.121	0.590537
AlGaAs	1.01 × 10?20	32.8 × 10?5	3.24 × 1016	14.5095	0.627576

Table2.
Various output parameters for different channel materials (SILVACO ATLAS TCAD simulation).



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Device with different channel materials	IOFF	ION	ION/IOFF	SS (mV/decade)	Vt
Silicon	4.11 × 10?17	17.7 × 10?5	4.32 × 1012	30.7985	0.682591
GaAs	1.16 × 10?18	36.6 × 10?5	3.15 × 1014	16.121	0.590537
AlGaAs	1.01 × 10?20	32.8 × 10?5	3.24 × 1016	14.5095	0.627576

Fig. 7 shows the variations of energy gap (E_g) with mole fraction x of its component and is given by 1.422 + 1.2475x eV for x = 0.45. It is observed from Fig. 7 that as we increase the value of x, the band gap increases.






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Figure7.
(Color online) Variations of energy gap (E_g) with mole fraction x of its component ranging from 0 to 0.6.




Fig. 8 shows the variations of transfer characteristics of Al_xGa_1?xAs DG tunnel FET with different mole fraction x. It is inferred from Fig. 8 that as the mole fraction x increases, the value of drain current decreases. This is due to an increase in the band of the material with an increase in mole fraction x. Thus, the lower value of x for aluminum is preferred for the device. Table 3 summarizes the parameters in terms of I_OFF, I_ON, I_ON/I_OFF, SS and V_t for different mole fractions of aluminium.






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Figure8.
(Color online) I_DS–V_GS characteristic of Al_xGa_1?xAs DG tunnel FET for different values of aluminum mole fraction.

Mole fraction	IOFF	ION	ION/IOFF	SS (mV/decade)	Vt
x = 10	1.24 × 10?21	7.70 × 10?5	6.21 × 1016	14.074	0.785767
x = 20	1.18 × 10?21	1.19 × 10?5	1.01 × 1016	14.1381	1.00271
x = 30	6.86 × 10?21	1.24 × 10?6	1.81 × 1014	24.6429	1.24419
x = 40	2.20 × 10?21	8.67 × 10?8	3.94 × 1013	27.9075	1.3300

Table3.
Various output parameters for different mole fractions of aluminum.



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Mole fraction	IOFF	ION	ION/IOFF	SS (mV/decade)	Vt
x = 10	1.24 × 10?21	7.70 × 10?5	6.21 × 1016	14.074	0.785767
x = 20	1.18 × 10?21	1.19 × 10?5	1.01 × 1016	14.1381	1.00271
x = 30	6.86 × 10?21	1.24 × 10?6	1.81 × 1014	24.6429	1.24419
x = 40	2.20 × 10?21	8.67 × 10?8	3.94 × 1013	27.9075	1.3300

With scaling down of Si based tunnel FET below 5 nm, short channel effects and leakage currents degrade the performance of the device. CNT is one of the most promising materials, which can replace Si for ultrathin body devices due to the small diameter (1–3 nm) of CNT^[23]. CNT exhibits various properties such as aggressive channel length scaling due to the absence of mobility degradation and variable bandgap with a single material. The bandgap of the CNT is inversely proportional to its diameter^[6]. CNT require a low bias value at the gate compared to Si based DG tunnel FET. Simulations for DG tunnel FET with CNT as the channel material have been performed using the Nano TCAD ViDES Device simulator, as shown in Fig. 9. The simulation parameters for the CNT based device are diameter (d) = 1 nm, length of channel (L_c) = 20 nm, oxide thickness (t_ox) = 1 nm, gate metal work function = 4.1, and the doping concentrations for N-type and P-type regions are 5 × 10^?3 and ?5 × 10^?3 molar fraction.






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Figure9.
Schematic diagram for DG tunnel FET with high-k dielectric.




Fig. 10 represent the comparative variations of I_DS for Si, Al_xGa_1?xAs and CNT based devices with gate voltage V_GS when all devices are optimized at constant V_t. The CNT based DG tunnel FET shows better switching properties as compared to the Si and Al_xGa_1?xAs based DG tunnel FET. The output parameters obtained during simulation are also summarizes in Table 4.






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Figure10.
(Color online) I_DS–V_GS characteristic of DG-tunnel FET for various channel materials Si, Al_xGa_1?xAs, and CNT.

Device with different channel materials	ION	IOFF	ION/IOFF	SS (mV/decade)
Silicon	2.14 × 10?6	4.27 × 10?10	5.011 × 103	37
AlxGa1?xAs	9.30 × 10?6	3.70 × 10?12	2.51 × 106	32.5
CNT (d = 1 nm)	3.03 × 10?6	2.00 × 10?12	1.51 × 106	29.4

Table4.
Various output parameters for different channel materials obtained from TCAD simulation.



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Device with different channel materials	ION	IOFF	ION/IOFF	SS (mV/decade)
Silicon	2.14 × 10?6	4.27 × 10?10	5.011 × 103	37
AlxGa1?xAs	9.30 × 10?6	3.70 × 10?12	2.51 × 106	32.5
CNT (d = 1 nm)	3.03 × 10?6	2.00 × 10?12	1.51 × 106	29.4

5.
Conclusions

The performance analyses of a double-gate tunnel field-effect transistor (DG tunnel FET) have been carried out with different channel materials viz. Silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (Al_xGa_1?xAs) and carbon nano tube (CNT) using TCAD SILVACO ATLAS and Nano TCAD ViDES Device simulators. Aluminum gallium arsenide (Al_xGa_1?xAs) is a tertiary semiconductor material with very close lattice constant as binary GaAs. Simulation results show that the group III–V compound based channel material demonstrates better performance as compared to its Silicon counterpart. It has been found that the Al_xGa_1?xAs based DG tunnel FET gives the highest I_ON/I_OFF current ratio as compared to Si and CNT based DG tunnel FET. DG tunnel CNTFET provides better performance in terms of steep inverse subthreshold (slope 29.4 mV/decade) as compared to DG tunnel FET with Si (37 mV/decade ) and Al_xGa_1?xAs based DG tunnel FET (32.5 mV/decade), and also good control of the OFF current. Thus DG tunnel CNTFET has been found to be a promising future nanoscale device. The simulated results will be useful for the scientific and research community working in this area.