1.
Introduction

There is ever increasing demand for mobile and portable equipment that can support complex software applications that require low power and high speed computation, which needs optimized design of each component of the hardware^[1].



Leakage power consumption and short-channel effects increase exponentially with the device scaling and ever increasing chip area enjoyed by SRAM, which continues to be a major cause of power dissipation^[2]. Since SRAM stays mostly idle, leakage power is the major power consumer^[3]. Numerous solutions have been sought including silicon on insulator, hetero-devices, FinFETs^[4–6], strained silicon and micro electro-mechanical systems^[7] to solve this problem. These solutions require additional processing steps and thus increased complexity, cost and sensitivity to process variability^[8].



In the conventional 6T cell (shown in Fig. 1(a)) the data stability is adversely affected during read operation by the discharge of the precharged bit-line through the NMOS driver connected to the node storing logic ‘0’. The use of weak access devices helps improve read static noise margin RSNM^[9]. Other configurations frequently used are WRE 8T call (Fig. 1(b)), LP 10T cell (Fig. 1(c)) and conventional 8T cell (Fig. 1(d). Fig. 1(e) )shows the proposed cell.






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Figure1.
(a) 6T cell. (b) WRE 8T cell. (c) LP 10T Cell. (d) Conventional 8T cell. (e) Proposed WARI 8T cell.




A comparison of 6T and the proposed 8T cell during write operation is shown in Figs. 2 and 3.






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Figure2.
Comparison of (a) 6T and (b) the proposed cell.




Writing of logic-1 in a conventional cell node (assumed to store logic 0) is especially difficult due to the deterioration of the strength of the write-access device with the rise in node voltage during write operation. This lengthens the write delay and reduces the write margin and write-ability of the cell.



Fig. 3 compares the write operation in the conventional 6T cell with the write operation of the proposed design. Power interrupt assists in the write operation of the proposed design by reducing the strength of feedback in the cell and strengthening of the write access device. The proposed cell node, which is not driven by feedback (during write operation), operates at a lower voltage (assuming the node stores a logic 0) and improves the voltage drive (VDS) and strength to the write access device MACC when attempting to write logic 1.






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Figure3.
Waveforms of nodal voltages during write operation of WARI 8T and 6T.




Several solutions have been employed, which are basically aimed at either interrupting the feedback loop during the write^[10–13] or by using a pass transistor to increase the current driving capability of access devices to assist in the write operation. Here the cell^{[10, 11]} uses an nMOS pass transistor to interrupt the feedback loop but since it passes logic 1 weakly it causes incomplete voltage swing in the internal nodes. The PMOS device was added to the NMOS pass device to provide complete voltage swing in the internal nodes^{[13, 14]}. The PMOS device for feedback interrupt was used to replace the NMOS device providing complete voltage swing in the internal nodes. Sharifkhani and Sachdev^[14] boosted the voltage applied to the gate of access devices during write operation by the use of an on-chip voltage level shifter, which increased the area overhead and power consumption. Zhai et al.^[11] used a distributed virtual supply and ground rails to weaken the feedback loop during the write operation in a 6T cell. Different cell topologies are available in Refs. [16–20].



A weak access device improves the read static noise margin RSNM and stability of the cell during the read operation, but on the other hand lowers the write ability. The proposed design uses dedicated write access device read isolation devices. Thus, the conflict of transistor sizing does not arise. The cell is isolated from the read bit-line so that maximum stability during read operation is guaranteed. The leakage power dissipation is also addressed. In the proposed design, bit-line leakage is reduced by the use of high V_t access devices and standard V_t devices for the inverters of the cell ensuring reduced bit-line leakage current without increasing delay. The proposed cell will be known as write-assisted-read-isolated 8T or WARI 8T cell.

2.
Proposed SRAM cell circuit description

2.1
Easier write operation in WARI 8T Cell

The PMOS device M5 whose gate along with the gate of write access device M5 is connected to the write word line WWL. Fig. 1(e) shows the proposed WARI 8T cell and Fig. 5 shows its transient analysis.



The implementation of the proposed WARI 8T cell is shown in Fig. 4. Here a replica bit-line REBL (loaded with 'n' WARI 8T cells) is used to determine the time required to completely discharge from VDD to 0 V and provide delay to the write word line signal WWL applied to the cell array. The voltage sensing circuit (M1 to M7) is used to determine the time instant when REBL reaches 0 V.



During the start of the write cycle, one of the outputs of the column decoder goes high and data signal (DATA_IN) is applied to the selected column (precharged to VDD) of the cell array. Also the write-enable signal WRE goes high, which causes the replica bit-line REBL (pre-charged to VDD) to start to discharge towards Gnd through the inverter (as seen in figure). The output of the sense circuit (M1–M7) goes high when REBL reaches 0 V. The WRE is already high, which turns the output of the NAND gate low, allowing the output of the row decoder (WWL) to be applied to the cell array. The WWL signal weakens the feedback in the WARI 8T cell by switching-off the supply to the left inverter and turns on the access device, which allows data to be written to the cell.



As shown in Figs. 2 and 3, the write operation in the proposed design is completed before the conventional 6T cell due to the absence of resistance due to feedback in the WARI 8T cell and improved strength of the write -access device.



When the new data written into the cell WWL is raised high, it turns the write access device M6 on and the HVT pull-up device M5 off. Write access device M6 connects the input of the right inverter to the write bit-line WBL to enable new data to be written into the cell and at the same time M5 weakens the left inverter by interrupting the supply, making the writing of a new data easier (Fig. 5). The W/L of the read access device is kept minimum to where the write access device is significantly wider than the read access device ensuring improved write-ability.

2.2
RBL isolation for improved RSNM in WARI 8T

An 8T dual V_t cell (Fig. 4) with the bit-line isolation with read operation and write assist has been proposed. The proposed cell uses separate access devices for read and write operations. The cell is isolated from the read bit-line to ensure read stability is not deteriorated. This is done by providing a separate discharge path for the precharged bit-line through M7 and M8. Sizing of inverter NMOS driver devices M1 and M3 are set to 2, for PMOS pull up devices M2 and M4 as 4.5 and access device M6 as 6^[20]. Sizing of read access devices M7 and M8 is optimized for minimum read delay and read bit-line RBL parasitic capacitance and resistance. The proposed cell during read operation allows the read bit-line RBL to discharge through a path different than the driver device of cell i.e. through M7 and M8 if logic 1 is stored on the internal node B of the cell. Since the driver device of the cell does not participate in bit-line discharge, thus, data stability is unaffected during read operation, and RSNM is the same as SNM during data retention.






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Figure4.
Implementation of the proposed cell.

2.3
Read device aspect ratios

The read devices M7 and M8 help in isolating the cell from the bit-line during read operation. M7 is a high V_t device whereas M8 is a standard V_t device. High V_t M7 reduces bit-line leakage current during no-read periods. Since M7 and M8 do not take part in data retention and provide a different path for the read bit-line RBL to discharge thus their aspect ratios do not affect the read noise margin RSNM. Thus their W/L can be kept relatively large to maintain a low read delay. Since any increase in the size of M7 and M8 connected to the read bit-line increases the cumulative parasitic capacitance for the large number of cells in a column rapidly, it can eventually offset the gain in read speed; therefore, the sizing of the read devices should be done judiciously.



To reduce the RBL leakage current, M7 and M8 are HVT devices whose I_on/I_off is relatively low as compared to the SVT devices. In the Zhai et al.^[11] cell a transmission gate is used for read and write access, which leaves the access device conflict unresolved and only improves the voltage swing on the internal nodes of the cell.

2.4
Write noise margin

The inverter feedback loop is weakened during the write operation. This is done by switching-off device M5 and interrupting the power supply to both the inverters during write operation. Leakage power for WARI 8T during no-write operation is least among all the cells since write-access device M5 is a high V_t device.



The source terminal of NMOS pull-down devices is kept connected to the ground terminal during write operation. The gate to source capacitance of the right inverter NMOS device is charged to a logic voltage across the ground by the write-access device M5 according to the logic status of the write bit-line during write operation. Since the magnitude NMOS gate-source capacitance is small, the current capacity of the write-access device has a negligible effect over write-delay and WSNM, thus the width can be kept relatively small thereby reducing the WBL parasitic.



The WSNM variation with supply voltage is plotted in Fig. 6. and found to be best for WARI 8T among all the cells compared. Since the power supply during the write operation is interrupted and the logic voltage is stored in the gate-to-source capacitance of the right inverter devices thus the WSNM depends to some extent on the right inverter sizing and increases slightly with the right inverter size shown in Fig. 7.






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Figure6.
Variation of WSNM with supply voltage.






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Figure7.
Right inverter sizing versus RSNM, WSNM and HSNM at 0.4 V supply.




The WSNM for WARI 8T was found to be improved by 2.1×, 5.7×, and 2.54× compared to WRE8T, LP10T and 6T respectively at supply voltage of 0.41 V, and 2.4×, 5.36×, and 4.1× respectively at a supply voltage as low as 0.4 V.



WSNM decreases with the increase in HVT pull-up device M5 width, shown in Fig. 8. due to the increase in leakage current across the device with width and resulting in potential build-up at the output node of the left inverter. Thus results in loss of the gain in WSNM obtained by power supply interruption and inverter feedback loop weakening. Variation of the high V_t pull-up device aspect ratio from 1.125 to 14 showed little effect over the RSNM and HSNM of the proposed WARI 8T, but a reduction in WSNM from 1.19 to 0.194 V, as shown in Fig. 8.






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Figure8.
High V_t supply interrupt device width versus SNM.

2.5
Cell modelling for write operation (with load)

The proposed design is simpler than the conventional designs and provides separate read circuitry (devices M7 and M8) that allows discharge of the read bit-line RBL (precharged to VDD) without disturbing the cell devices and cell operation, thus offering improved speed and read noise margin. Fig. 9 shows the WARI 8T cell write operation with capacitive load.






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Figure9.
WARI 8T cell write operation with capacitive load.

2.5.1
Improvement of the WARI 8T cell write operation

Assuming cell node QD stores logic 0 and QB stores logic 1:



1. The equivalent model of node QBD (assumed initially stores logic 1) has connected to node QBD a PMOS device M4 turned on (gate terminal connected to node QD at logic 0) operating in triode region (V_DS < V_GS – V_TH) modeled as R_PUR connected to V_DD that charges QBD towards V_DD and NMOS device M3 operating in cut-off represented by a grounded capacitor C_QBD.



2. Since during write, the supply to the left inverter is interrupted, equivalent NMOS (driver device M1) grounded resistance at node QD is R_PDL = ∞ and capacitance is modeled as grounded C_QD. Also during write, V_WBL = V_DD thus, access device M6 operates in the saturation region (V_DS > V_GS – V_TH) is modeled as constant current source I_MACC-driving saturation current in the direction of WBL to QD. Where WBL load capacitance is represented by a grounded C_BIT.



3. The right pull-up device M4 is modeled as a resistor RPUR since it operates in the triode region that charges towards V_DD the capacitance at node QBD, which is modeled as CQBD.

$${C_{{ m{QBD}}}}frac{{{ m{d}}{V_{ m QBD}}}}{{{ m{d}}t}}{ m{ = }}{{{I}}_{{ m{PUR}}}},$$

(1)

$${I_{{ m{PUR}}}} = frac{{{V_{ m DD}} - {V_{ m QBD}}}}{{{R_{ m PUR}}}}.$$

(2)

4. Since the supply to the left inverter is interrupted, thus the device capacitance at node QD is modelled as capacitance C_QD. Since access device M6 operates in the saturation region thus it is modelled as constant current source I_MACC. WBL load capacitance is represented by C_BIT and nodal capacitance by C_QD of the cell.

$${C_{{ m{QD}}}}frac{{{{ m{d}}_{V{ m{QD}}}}}}{{{ m{d}}t}} = {I_{{ m{MACC}}}},$$

(3)

$${{{I}}_{{ m{MACC}}}} = frac{{{beta _{ m MACC}}}}{2}{left( {{V_{ m DD}} - {V_{ m THN}}} ight)^2},$$

(4)

$${V_{{ m{QD}}}} = frac{{left( {left| {{b_{ m{L}}}} ight| - sqrt {{b_{ m{L}}}^2 - 4{a_{ m{L}}}c_{ m{L}}} } ight)left( {1 - {{ m e}^{frac{{ - {a_{ m{L}}}{ m{t}}}}{{{C_{{ m{QD}}}}sqrt {{b_{ m{L}}}^2 - 4{a_{ m{L}}}{c_{ m{L}}}} }}}}} ight)}}{{left| {2a} ight|left( {1 - frac{{|{b_{ m{L}}}| - sqrt {{b_{ m{L}}}^2 - 4{a_{ m{L}}}{c_{ m{L}}}} }}{{|{b_{ m{L}}}| + sqrt {{b_{ m{L}}}^2 - 4{a_{ m{L}}}{c_{ m{L}}}} }}{e^{frac{{ - {a_{{ m{L}}.{ m{t}}}}}}{{{C_{{ m{QD}}}}sqrt {{b_{ m{L}}}^2 - 4{a_{ m{L}}}{c_{ m{L}}}} }}}}} ight)}},$$

(5)

where ${a_{
m L}} = frac{{{beta _{
m MACC}}}}{2}$, ${b_{
m L}} = - left[ {{beta _{
m MACC}}left( {{V_{
m DD}} - {V_{
m THN}}}
ight) + frac{1}{{{
m{RPDL}}}}}
ight]$, ${c_{
m L}} = frac{{{beta _{
m MACC}}}}{2}{left( {{V_{
m DD}} - {V_{
m THN}}}
ight)^2}$.



Node QD, assumed to initially store logic ‘0’ whereas a logic ‘1’ is attempted to be written in WARI 8T cell. Improvement in the proposed circuit is seen as a faster increase of nodal voltage V_QD given by Eq. (3). a_L and c_L are positive whereas b_L is negative.

2.5.2
Improved WM and faster write due to reduction in b_L

In the proposed cell, PDL device M1 in operating in triode earlier (with QD = 0 and QB = V_DD) as shown in the figure. The left inverter switches off due to interrupted supply causing R_PDL to become infinite, thus 1/R_PDL becomes 0, which causes reduction in b_L. Here, increment and decrement in each of the terms is shown by ↑ and ↓ within parenthesis in the numerator and denominator of Eq. (3). b_L reduces in the proposed design, which causes both first and second terms in the numerator to increase. Whereas the denominator decreases, which shows a faster increase in V_QD compared to non power interrupted designs.

$${{{V}}_{{ m{QD}}}} = frac{{left( uparrow ight)left( {1 - downarrow downarrow } ight)}}{{left| {2a} ight|left( {1 - frac{ uparrow }{ downarrow } downarrow downarrow } ight)}}.$$

(6)

In conventional 6T or 8T^[5] SRAM, charging of node QD by the write access device is opposed by the feedback of back-to-back inverters and any attempt to write into the cell is successful after overcoming this resistive force, whereas here, due to supply cut-off to the left inverter and thus absence of R_PDL resistance and discharge path of node QD, the charging-time reduces compared to conventional designs. Breaking of the feedback loop by switching-off M5 and supply to the left inverter allows node QD (input to the right inverter) to be charged directly by the M6 without being opposed by the QBD node (output of the right inverter), which reduces the write-delay.



1. Here, due to absence of feedback of cell, write operation takes place without being opposed by the output of the right inverter (unlike in the conventional 6T or 8T cell ).



2. Apart from easier charging of the C_QD node capacitance by the access device due to absence of discharge path R_PDL.



3. An increase in the strength of access device MACC with Source connected to node QD (assumed to be at 0 V) due to improved V_GS and V_DS results in faster charging of node capacitance C_QD leading to an improved write margin and write-ability to the proposed design compared to conventional 6T and 8T cells.



The proposed WARI 8T cell shows reduced write delay and write power with increase in write bit-line capacitance, which acts as a load. The proposed design shows the lowest write-delay at the highest WBL load capacitance of 1.28 pF and remains almost flat throughout the capacitance range of 1 fF to 1.28 pF unlike the earlier designs. Fig. 10 shows the variation of write delay with write bit line capacitance.






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Figure10.
Variation of write delay with write bit line capacitance.

3.
Simulation results

In this section compare WARI 8T, WRE 8T, conventional 6T and LP 10T cells.In Fig. 11 the write access device channel ratio was varied from 1.125 to 14 and WSNM was found to be constant for WARI8T and WRE8T cells and 2×, 5.02×, and 2.52× higher than WRE8T, LP10T and 6T respectively.






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Figure11.
Variation of WSNM with write access device width.




In Fig. 12 the leakage power for WARI 8T is only 4.3%, 3.6% and 2.3% at a supply voltage of 0.41 V and 52%, 96% and 53% at a supply voltage of 1 V as compared to WRE8T, LP10T and 6T respectively. The curve for the leakage power of WARI 8T did not increase as much as for other cells due to the use of high Vt devices for read and write access.






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Figure12.
Variation of leakage power with supply voltage.




The read noise margin is also significantly higher than the other cell in the supply voltage range of 0.49 to 0.89 V. RSNM was found to be 1.2×, 1.42×, and 1.24× higher than the WRE8T, LP10T and 6T cells respectively. WRE8T was found to have a higher RSNM than the 6T and LP10T cells. Write power consumed by WARI 8T is also least of all the cells compared for a supply voltage variation between 0.4 and 0.61 V, as shown in Fig. 15. While LP10T has the least RSNM and the same trend is followed with the entire range of supply voltage as shown in Fig. 15.






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Figure13.
Variation of RSNM with supply voltage.




In Fig. 14, the variation of the read access device aspect ratio from 1.125 to 14 showed a constant RSNM for the WARI 8T cell whereas a lot of variation in RSNM for all the other cells. An improvement of 2.09×, 5.24×, and 2.53× as compared to WRE8T, LP10T and 6T cells respectively at an aspect ratio of 1.125 for the read access device was observed.






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Figure14.
Variation of RSNM with read access device width.




Variation of write power dissipation with supply voltage from 0.41 to 1 V has been plotted in Fig. 17. There is a 24×, 6.3×, and 46.6× times reduction in the write power at 0.41 V supply as compared to WRE8T, LP10T and 6T respectively. The write power, which increases more rapidly than the other compared cells but continues to stay lowest among the four cells for WARI8T from supply voltage of 0.41 to 0.55 V, which then exceeds the power for LP10T cell but is still lower than WRE8T and 6T cells. The WRE8T still continues to consume power lower than the 6T cell.



Fig. 15 confirms that the proposed WARI 8T circuit consumes much less power during read, write and idle periods compared with the WRE 8T, 6T and LP10T (Low-Power 10T) SRAM cells of Refs. [16–19], respectively.






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Figure15.
Variation of write power with supply voltage.




Read power dissipation with supply variation from 0.41 to 1 V has been plotted on a logarithmic scale in Fig. 16. There is a 2.2 × 10⁴, 7.43 × 10³, and 4.5 × 10⁴ times less write power for WARI8T at 0.41 V supply as compared to WRE8T, LP10T and 6T respectively. Read power continues to stay the lowest among all the four cells compared. The LP10T follows WARI8T, followed by WRE8T and 6T in being the most read power efficient cells in bulk CMOS.






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Figure16.
Variation of read power with supply voltage.




Fig. 17 shows read power, write power and leakage powers for WARI 8T, WRE 8T, LP10T and 6T respectively. Read and write powers are least for WARI 8T, followed by LP10T, WRE 8T, conventional 8T and 6T respectively.



As expected the WSNM is large as compared to RSNM and HSNM. This is due to the write assistance provided by turning off the high V_t pull-up device, which weakens the feedback loop. The RSNM and HSNM are found to be equal due to the read-isolation technique used, which provides a separate discharge path for the read bit-line using M7 and M8 without using the cell.



Fig. 18 shows the WSNM, RSNM, HSNM and leakage power dissipation in microwatts for all the four cells. It is found that WSNM improved by about 4 ×, 2.4 ×, and 5.37 × as compared to WRE8T, LP10T and 6T respectively. RSNM for WARI8T is better than 6T and WRE8T but lower than LP10T. RSNM is 1.21×, 1.16×, and 1.45× WRE8T, LP10T and 6T, but only 0.77× that of LP10T. HSNM is equal to RSNM and 0.7×, 1.45×, and 0.97× that for WRE8T, LP10T and 6T respectively. HSNM for the WARI8T is a little less than the WRE8T and 6T cells but is more than the LP10T cell. Leakage power is least for the WARI8t cell. The leakage power is 0.936×, 0.83×, and 0.49× WRE8T, LP10T, conventional 8T and 6T cells respectively.






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Figure18.
(Color online) Comparison of relative WSNM, RSNM, HSNM and leakage power (in 10 μW) for 6T, WRE8T, conventional 8T, LP10T and proposed WARI 8T.




In Fig. 19 the parametric sweep plotted for supply voltage from 0.4 to 1 V, temperature from 23 to 73 °C and cell pull-up ratio from 1 to 12 has been plotted. It shows the operating corners of the WARI8T cell during read operation.






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Figure19.
(Color online) RSNM of WARI 8T cell parametric sweep for supply voltage 0.4 to 1 V, temperature 23 to 73 °C cell pull-up ratio 1 to 5.




In Fig. 20 the parametric sweep plotted for supply voltage from 0.4 to 1 V, temperature from 23 to 73 °C and cell ratio from 1 to 5 has been plotted. It shows the operating corners of the WARI8T cell during write operation.






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Figure20.
(Color online) WSNM of WARI 8T cell parametric sweep for supply voltage 0.4 to 1 V, temperature 23 to 73 °C, cell pull-up ratio 1 to 5.

3.1. Delay for write and read

Table 1 shows simulation results for noise margins for read write and data retention, write delay and power consumption during read, write and retention. Write delay of the cell is defined as the time duration from the assertion of the WWL wordline of write until voltages of internal nodes of cell (q and qb in Fig. 5) become equal. Read delay of the cell defined as the time that RWL word-line of read is asserted until the time 50% of VDD voltage difference between the bitline and its bitline bar appear^[18].

Parameter	WARI 8T	WRE 8T	LP10T	6T
WSNM (V)	0.81	0.34	0.15	0.20
RSNM (V)	0.15	0.14	0.12	0.12
HSNM (V)	0.20	0.28	0.14	0.21
Write power (μW)	0.02	0.43	0.11	0.82
Read power (μW)	1.83 × 10?5	0.40	0.14	0.82
Leakage power(μW)	0.02	0.44	0.53	0.82
Write delay(ps)	17	39	79	7

Table1.
WSNM, RSNM, HSNM, write power, read power, leakage power, write delay and read delay at 0.4 V supply.



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Parameter	WARI 8T	WRE 8T	LP10T	6T
WSNM (V)	0.81	0.34	0.15	0.20
RSNM (V)	0.15	0.14	0.12	0.12
HSNM (V)	0.20	0.28	0.14	0.21
Write power (μW)	0.02	0.43	0.11	0.82
Read power (μW)	1.83 × 10?5	0.40	0.14	0.82
Leakage power(μW)	0.02	0.44	0.53	0.82
Write delay(ps)	17	39	79	7

Write access device M6 (see Fig. 1(e)) charges node QD during the write operation with power interruption applied with reduced feedback strength and improved strength of M6. The power interruption is applied to the left inverter (M1–M2) using HVT device M5. The right inverter continues to operate normally. Due to feedback weakening with the disconnected supply during write operation, the write delay is reduced and is least among all the cells. Write delay for WARI 8T has been found to be 2.5× of 6T cell, 0.75× of WRE 8T cell and 0.33× of LP 10T cell.



Figs. 21 and 22 show the variation of write delay with write access device sizing and supply voltage variation respectively.






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Figure21.
Write delay versus write access device sizing variation of the proposed WARI 8T cell.






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Figure22.
Read delay versus supply voltage variation of the proposed WARI 8T cell.

3.2. Minimum supply and data retention voltage

Minimum supply voltage (VDD_min.) can be determined either using SNM^[24] or an approximate transient based^[25]. The first does not use the transient behavior of SRAM. The second technique produces errors in tails where higher failure probabilities exist. In this paper, we considered transient behavior (Fig. 5) as well as read and write SNM analysis (Figs. 19 and 20) for parametric sweep of the supply voltage, temperature and cell ratio and pull-up ratio. Monte Carlo simulation with parameters of transistors varied using a Gaussian distribution to model the process variations was used.






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Figure5.
(Color online) Transient analysis of WARI 8T cell.

3.3. Read noise margin

Due to intrinsic parameter fluctuation^[22–24] like random dopant fluctuation, line edge roughness and oxide thickness fluctuation the performance and yield of the device is greatly affected. To simulate these effects statistical and corner analysis of the SRAM cell has been carried out. The simulation result for corner analysis of the read noise margin is shown in Table 1. Simulation of RSNM and WSNM of WARI 8T, 6T, WRE8T and LP 10T SRAM cell is shown in Figs. 17 and 18 respectively. The statistical analysis leakage energy due to the sub threshold leakage current is modelled^{[22, 23]} as:






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Figure17.
(Color online) Read power, write power and leakage power.

$$begin{split}{I_{{ m{sub}}}} = & {A_{{ m{sub}}}}{ m{exp}}left( {frac{q}{{n'kT}}left( {{V_{{ m{GS}}}} - {V_{t0}} - gamma '{V_{{ m{SB}}}} + eta {V_{{ m{DS}}}}} ight)} ight)& times left( {1 - { m{exp}}left( { - frac{q}{{kT}}{V_{{ m{DS}}}}} ight)} ight),end{split}$$

(7)

where ${A_{{
m{sub}}}} = {mu _0}{C_{{
m{ox}}}}frac{W}{{{L_{{
m{eff}}}}}}{left( {frac{{kT}}{q}}
ight)^2}{{
m e}^{1.8}}$, μ₀ is zero bias mobility, C_ox is the gate oxide capacitance per unit area, W and L_eff denotes the width and effective length of the transistor, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. V_t0 is the zero biased threshold voltage, γ' is the linearized body-effect coefficient, η represents the drain-induced barrier lowering coefficient, and n' is the sub threshold swing coefficient.



The gate tunnelling leakage current has been modelled^{[22, 23]} as

$$begin{split}{J_{{ m{Tunnel}}}} =& frac{{4varPi {m^*}q}}{{{h^3}}}{left( {kT} ight)^2}left( {1 + frac{{gamma kT}}{{2sqrt {{E_B}} }}} ight) & times { m{exp}}left( {frac{{q{Phi _{ m{s}}} - q{Phi _{ m{F}}} - frac{{{E_{ m{G}}}}}{2}}}{{kT}}} ight){ m{exp}}left( { - gamma sqrt {{E_{ m{B}}}} } ight),end{split}$$

(8)

where m* (= 0.19M₀) is the electron transfer mass, M₀ is the electron rest mass, h is the Planck constant, E_B is the height of the barrier, and E_G is the silicon band gap energy. The parameter $ phi $_F is the Fermi energy level either in the Si substrate for the gate tunnelling current through the channel or in the source/drain region for the gate tunnelling current through the source/drain overlap and γ is defined as,

$$ gamma = frac{{4varpi {T_{{ m{ox}}}}sqrt 2 {m_{{ m{ox}}}}}}{h},$$

(9)

where $sqrt 2 $m_ox ( 0.32M₀) is the effective electron mass in the oxide, and T_ox is the gate oxide thickness.



3.4. Leakage power consumption



The power consumed by the cell in idle mode is important since most of the time a cell is idle and contributes a large extent to the total power budget of the chip. The leakage component in MOS Isub is dominating^[17], so, to reduce the total leakage current, I_sub should be reduced. Whereas Morifuji et al.^[20] found suppression of gate leakage current (I_g) useful to reduce the leakage power in low-voltage SRAMs. Read and write access devices have been replaced by high V_t devices to minimize leakage from bit-lines during no read and write operation. The high V_t PMOS device to interrupt the power supply during write is also used to reduce leakage from the supply and apply a reduced data retention voltage during the hold or idle period. There are three series-connected transistors in both the inverters, which are known as the stacking effect^[7], and reduce the sub threshold leakage currents for devices of both the inverters of the proposed WARI 8T cell. Also, the device sizing is kept minimum to minimize the gate and sub threshold power consumed by the cell.



Leakage powers of WARI 8T are 0.0432×, 0.036×, and 0.023× compared to the WRE8T, LP10T and 6T respectively.

3.5. Average write power

The simulation results for power consumed during read and write operation is shown in Table 1. Power consumed by the WARI 8T cell during the write operation was found to be least out of all the cells compared; this was due to feedback loop weakening and use of high V_t devices. The write power is at least 86% improved compared to the nearest LP10T cell, 95% compared to WRE 8T and 97.9% compared to the 6T cell.



3.6. Average read power



The WARI 8T consumes 0.25×, 0.76×, and 0.125× read power compared with WRE 8T, LP10T and 6T cells respectively as shown in Fig. 16. This is due to the use of one read bit-line instead of two as in LP10T and 6T cells and the use of high V_t read access device M7 to charge and discharge the read bit-line node.



3.7. Process corners



The write performance of the proposed 8T cell is discussed using the write-margin at process corners (FF SS FS and SF), which have been included in Fig. 23 and Table 2.






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Figure23.
Write margin of the proposed 8T cell for process corners.

Process corner	FF	FS	SF	SS
Write-margin (mV)	77	69	48	26

Table2.
Write-margin and write-time for proposed BNBL WA 11T scheme for FF, FS, SF and SS process corners.



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Process corner	FF	FS	SF	SS
Write-margin (mV)	77	69	48	26

4.
Conclusion

A new write assist and read isolate dual V_t bulk MOS based SRAM cell (WARI 8T) has been proposed. The simulation was performed at the 45 nm technology node and results were compared with other cells available in the literature and simulated in the same technology.



In the proposed cell, an improved write operation is provided by power supply interruption and weakening of the voltage at the cell nodes. Read isolation is provided using a high V_t access device for an improved read noise margin, read delay and average power consumption. The proposed cell offers superior read, hold and write noise margins over the conventional cells. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V.



The write power for WARI8T is at least 86% improved compared to the nearest LP10T cell, 95% compared to WRE 8T, and 97.9% compared to the 6T cell. There is a 2.2 × 10⁴, 7.43 × 10³, and 4.5 × 10⁴ times less write power at 0.41 V supply as compared to WRE8T, LP10T and 6T respectively. The WARI 8T consumes 0.25×, 0.76×, and 0.125× read power compared with WRE 8T, LP10T and 6T cells respectively. The leakage power of WARI 8T is 0.0432×, 0.036×, and 0.023× compared to the WRE8T, LP10T and 6T respectively.



WSNM improved by about 4×, 2.4×, and 5.37× as compared to WRE8T, LP10T and 6T respectively. RSNM for WARI8T is better than 6T and WRE8T but lower than LP10T. RSNM is 1.21×, 1.16×, and 1.45× compared to WRE8T, LP10T and 6T cells. HSNM is 0.7×, 1.45×, and 0.97× that for WRE8T, LP10T and 6T respectively.



A new write back scheme has been suggested for half-selected cells, which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption.