周高磊 ,毛陆虹 ,谢 生 ,宋瑞良,魏 恒
AuthorsHTML:周高磊 ¹ ，毛陆虹 ¹ ，谢 生 ² ，宋瑞良 ³ ，魏 恒 ³
AuthorsListE:Zhou Gaolei,Mao Luhong,Xie Sheng,Song Ruiliang,Wei Heng
AuthorsHTMLE:Zhou Gaolei¹，Mao Luhong¹，Xie Sheng²，Song Ruiliang³，Wei Heng³
Unit:1. 天津大学电气自动化与信息工程学院，天津 300072；
2. 天津大学微电子学院，天津 300072；
3. 中国电子科技集团第五十四研究所，石家庄 050050

Unit_EngLish:1. School of Electrical and Information Engineering，Tianjin University，Tianjin 300072，China；
2. School of Microelectronics，Tianjin University，Tianjin 300072，China；
3. The 54 th Research Institute of China Electronics Technology Group Corporation，Shijiazhuang 050050，China

Abstract_Chinese:设计了一款传输速率为 25 Gb/s 的高输出摆幅 CMOS 光接收机模拟前端电路．该模拟前端电路包含跨阻放 大器、限幅放大器、输出缓冲器以及单端转差分和直流偏移消除模块．其中，跨阻放大器设计中采用反馈增强技术 降低输入阻抗，同时应用电感峰化技术消除输入端大电容的影响，从而降低了输入端极点的频率，提升了跨阻放大 器的带宽．三级互补型有源反馈限幅放大器在使用有源反馈技术扩展带宽的同时，利用互补型有源反馈结构极点分 裂的特性，消除了多级级联引起峰化增益，从而获得更加平坦的幅频增益．相比于交错有源反馈限幅放大器其结构 更为简单，信号线之间的串扰明显减小．而单端转差分电路使得该模拟前端电路输出信号呈现全差分特性，提升了 低供电电压 CMOS 工艺电路的输出摆幅．单端转差分电路可以同时实现直流偏移消除功能，节省了芯片的面积，提 升电路集成度．该高速光接收机模拟前端电路基于 SMIC 55 nm CMOS 工艺设计与仿真，版图面积为 830 μm× 850 μm．仿真结果表明：该光接收机模拟前端电路在输入端等效电容为 150 fF 的条件下，-3 dB 带宽为 24.3 GHz， 跨阻增益为 77.4 dB?，在此传输带宽内输入、输出反馈系数 s11、s22 均小于－10 dB；供电电压为 1.2 V 的情况下， 差分输出电压摆幅可达 400 mV；数据传输速率为 25 Gb/s 时，该接收机模拟前端电路功耗为 57.6 mW．
Abstract_English:In this study，we present a design for a high-swing analog front-end circuit for a 25 Gb/s optical receiver， which including a transimpedance amplifier，a limiting amplifier，an output buffer，a DC offset cancellation circuit and a single-to-differential circuit. Feedback gain-boosting and inductor peaking techniques are used in the design of the transimpedance amplifier to achieve low input resistance and isolate the capacitance of the input node，thereby enabling the attainment of a wider bandwidth by raising the frequency of the input node. To obtain flatness in the frequency response，three-stages limiting amplifier with complementing active feedback is proposed. Complemented active feed back technique could extend the bandwidth and reduce the peak gain by splitting the coinciding piles. Compared with the interleaving active feedback limiting amplifier，less crosstalk occurs between the signal paths due to the simpler structure. Additionally，a single-to-differential circuit is used to attain fully-differential output signal， thus the output swing could be improved efficiently. In addition，the DC offset can also be alleviated by the single to differential circuit，which enable a less area-consume and high-integration chip. The analog front-end circuit has an area of 830 μm×850 μm，and is fabricated using a SMIC 55 nm CMOS. The post simulation results indicate that the-3 dB bandwidth of the analog front-end(with a photodiode equivalent capacitance of 150 fF)is 24.3 GHz，and then transimpedance gain is 77.4 dB?. Parameters s11 and s22 are better than ?10 dB in the ?3 dB frequency range. A differential output swing of 400 mV is reached with a supply voltage of 1.2 V，and the power consumption of the circuit is 57.6 mW，when operating with a 25 Gb/s signal.
Keyword_Chinese:CMOS；光接收机；反馈增强；电感峰化；有源反馈
Keywords_English:CMOS；optical receiver；feedback gain-boosting；inductor peaking；active feedback

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