An 18-bit sigma –delta switched-capacitor modulator using 4-order single-loop CIFB architecture

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1.
Introduction

The idea of sigma–delta (Σ–Δ) modulation was first proposed in 1962 by Inoise et al.^[1], who described a modulator structure with a continuous-time integrator as circular filter and a Schmitt latch as a quantizer and implemented a 40-dB SNR analog to digital converter (ADC). In 1974, Richie et al. advanced the idea of employing a high-order circular filter to achieve high-performance ADCs^[2]. Subsequently, Candy et al. proposed a method of analyzing and designing Σ–Δ ADCs theoretically and also put forward the MASH (multi-stage noise shaping) structure^[3-8]. The MASH structure was first employed by Hayashi et al. to realize Σ–Δ ADCs^[8]. Because of the rapid development of the integrated circuit manufacture process technology, the concept of realizing a high system resolution in exchange for speed has been successfully applied, with 31-bit high-precision Σ–Δ ADCs currently being constructed. These high precision Σ–Δ ADCs usually employ high 4- or 5-order stages. Significant research on Σ–Δ ADCs has been undertaken in recent years and marked progress has been made; however, the implemented architectures are limited to 2- or 3-order stages with a precision below 16-bit^[9-12].

Structurally, the Σ–Δ ADC is divided into two parts: a front-end analog modulator and a back-end digital filter. The performance of the front-end analog modulator has a decisive influence on the performance of the Σ–Δ ADC. Principally, a higher precision can be achieved with higher-order front-end analog modulators. However, higher-order modulators (e.g., 4- or 5-order modulators) face stability issues. At the same time, the input signal range decreases with higher-order structures. Currently, the most widely used structures are of 4-orders or less. Increasing the modulator’s orders while maintaining stability is an important field of research. Caldwell et al.^[13] proposed an 8-order modulator in 2009 with an oversampling rate (OSR) of 3. The MASH structure cuts down the high-order single-loop to a low-order multi-loop to avoid stability issues; however, because of mismatch arising from the integrated circuit manufacturing process, designing Σ–Δ ADCs based on the MASH structure has been hard to accomplish. With continued advances in the manufacturing process and the persistence of high-order stability issues, the MASH structure has increasingly been used to implement high-precision Σ–Δ ADCs. Chiang et al.^[14] implemented a 14-bit Σ–Δ ADC with the MASH structure using a 2.5-V power supply and Yao et al.^[15] designed a 15-bit Σ–Δ ADC using a 130 nm process technology with a power supply of only 1.0-V and power dissipation of 7.4 mW. Chen et al. ^[9] proposed a promising Σ–Δ modulator for GSM systems and achieved an 80 dB dynamic range with a 1.8-V power supply and 16.7 mW power dissipation.

In this paper, a 4-order single-loop Σ–Δ switched-capacitor modulator with a CIFB (cascade-of-integrators feed-back) architecture is proposed for the design of a high-order single-loop modulator. This paper is structured as follows. In section 2, the 4-order single-loop CIFB Σ–Δ modulator architecture is proposed, and the noise transfer function (NTF) of the proposed structure is given and mapped to the CIFB parameters. Section 3 provides details on the implementation of the critical circuits. Section 4 presents the ASIC test results, and section 5 provides the conclusions for the paper.

2.
Σ–Δ modulator architecture

The performance of the Σ–Δ modulator depends primarily on the NTF. For physical implementation considerations, $Hleft( z
ight) = {
m{NTF}}left( z
ight)$

and $left| {Hleft( infty
ight)}
ight| = 1$

; and for stability considerations, $Hleft( z
ight)$

should satisfy the Lee Criterion: for a 1-bit quantizer Σ–Δ modulator, the ${
m{max}} left| {Hleft( {{{
m{e}}^{jw}}}
ight)}
ight| < 1.5$

^[16]. From the point view of signal filtering, the NTF could be written in the following format and it functions as an IIR high-pass filter. Therefore, by tuning the positions of the zeros and poles, an ideal NTF can be designed:

$$Hleft( z
ight) = {
m{NTF}}left( z
ight) = frac{{Nleft( z
ight)}}{{Dleft( z
ight)}} = mathop sum limits_{i = 0}^m {a_i}{z^i}/mathop sum limits_{j = 0}^n {a_j}{z^j}.$$

(1)

Fig. 1 shows the noise modulation results with different modulation orders. The results show that as the modulation order increases, more low-frequency noise is modulated into the high-frequency domain. The realization of a high precision ADC can be anticipated after back-end low-pass digital filter filtering of the high-frequency noise.

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i	a_i	g_i	b_i	c_i
1	0.00664	0.00007	0.0053	1
2	0.068261	0.00043	–	1
3	0.3165	–	–	1
4	0.819	–	–	1

DC gain	Phase margin	Power dissipation	GBW	Common offset	Single-side swing	Slew rate	Effective input noise
87.8 dB	66°	2.44 mW	28 MHz	100 nV	±2.2 V	5 V/μs	14 nV/Hz^1/2 (1 kHz)

Performance	This work	CS5372
SNR (dB)	93.79	93.09
THD (dB)	–101.64	–102.22
SINAD (dB)	93.13 dB	92.59
ENOB (bit)	15.18	15.09
SFDR (dB)	105.82	105.09
ENOB@FS (bit)	17.65	17.56

Parameter	ENOB	DOR	Dissipation (mW)	CMOS process (μm)	Power supply (V)	Orders	OSR	Quantizer (bit)	FOM-w
Geets^[21]	11.5	12.5 Msps	152	0.65	5	3	8	1	4.20
Balmelli^[22]	13.6	2.5 Msps	200	0.18	1.8	5	8	4	6.44
Brigati^[23]	16.9	400 sps	50	0.6	5	4	320	1	1022.1
Gerosa^[24]	9.1	256 sps	0.0018	0.8	1.8	3	16	8	12.8
Yao^[25]	14.3	500 ksps	7.4	0.13	1.0	4	64	1	0.73
Chen^[26]	12.0	48 ksps	30	0.5	5	5	64	1	8.30
This work	17.6	512 ksps	22	0.35	3.3	4	128	1	1.63