1.
Introduction

Wireless communication is becoming more and more popular, and mobile phones and WIFI have almost replaced corded phones and wired networks in daily life. As another example, iPhone 7 has removed the 3.5 mm headset interface and provides an optional Bluetooth ear pod; it is believed that iPhone 8 will contain wireless charging functionality. With the unification of the IoT standards, wireless signals will be omnipresent in our life in the future. But more and more wireless signals in the air will mean the problem of interference and blocking will be more critical, and for battery-powered portable devices, low power design is always an important consideration.



Direct conversion of the narrow-desired channel to a zero (IF) may significantly corrupt the signal by 1/f noise. Furthermore, the removal of the DC offset by means of a high-pass filter proves difficult. Thus, the use of low-IF architectures is much more popular. But in the low-IF receiver, it is undesirable to place the image interference within the signal band^{[1, 2]}. In theory, both the Hartley architecture and the weaver architecture can eliminate the image signal. But in real circuit implementation, the 90-degree phase shift circuit in the Hartley has a lot of defects; and the weaver architecture needs an additional mixer, not only the power consumption is increased, but also additional image interference is introduced in the second mixing process^[3]. Therefore, a poly-phase filter or active complex filters are often used to suppress the image signals.



Quadrature band-pass sigma–delta analog to digital converters (ADC), by using a complex filter in the loop, combine the complex filtering idea and the real bandpass sigma–delta ADC. The effective signal bandwidth is cut in half which doubles the over-sampling-ratio (OSR) giving ideal SNR improvement^[4–8]. Also, it is possible to choose the locations of the zeros of the noise-transfer function (NTF) to minimize errors due to quantization effects, and, finally, the following digital bandpass filter can filter out images from an imperfect preceding image-reject mixer. A single quadrature bandpass sigma-delta ADC can replace the complex image-reject filter and baseband ADC, which achieves chip area and power reduction. A receiver with quadrature bandpass Sigma-Delta modulator is illustrated in Fig. 1.






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Figure1.
Low-IF receiver with quadrature bandpass sigma–delta modulator.




In this paper, in order to implement a quadrature bandpass sigma–delta modulator with 76 dB peak SNDR, which is used for a 2.4 GHz low-IF receiver, a 3rd order switched capacitor structure is presented. In Section 2, transformation process from a real lowpass modulator to a quadrature bandpass modulator by pole movement is introduced, and circuit modeling and specification scan with MATLAB is also carried out. Section 3 describes the modulator’s circuit design, a capacitor series way to realize very small feedback coefficients is introduced in detail. The measurement results of the test chip, which is designed in SMIC 0.18 μm CMOS technology, are introduced in Section 4, and finally Section 5 gives a conclusion.

2.
System design

This section describes the system design of the quadrature bandpass sigma–delta modulator. The relationship between the integrator’s pole position and modulator’s passband frequency in real lowpass sigma–delta modulator is firstly studied, and then the complex integrator’s trans function is obtained from the real one by pole movement. A complex integrator, which is implemented with two identical cross coupling real integrators, is used as the core circuit of the quadrature bandpass sigma–delta modulator.



A 3rd order modulator system is first designed with sigma–delta toolbox^{[9, 10]}. The pole movement is calculated according to the IF and sampling frequency. A quadrature bandpass sigma–delta modulator is implemented by replacing the real integrators with the complex ones.

2.1
Real to quadrature modulator conversion

A 1st order lowpass sigma–delta modulator is shown in Fig. 2. The integrator has a pole which is equal to 1, which means its frequency is zero. When signal frequency is zero (in signal band, $ f ll $ f_s for oversampling system), the integrator has an infinity gain, then the input signal can be transferred to the modulator’s output without attenuation by negative feedback. But the quantization error is fed into the modulator from the quantizer, so the noise trans function (NTF) and signal trans function (STF) has a relationship as follows:






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Figure2.
1st order lowpass sigma–delta modulator.

$${ m {NTF}} ={ m{ STF}}/H_{mathop{ m int}} .$$

(1)

H_int is the integrator’s trans function, so the NTF gain is close to zero in the signal band, so the quantization noise is well shaped. According to the above analysis, it can be concluded that the integrator’s pole frequency determines the signal’s passband and quantization noise’s stopband. sigma– delta modulator is made up by cascaded integrators, but real trans function can only realize real pole or conjugate complex pole pair, which means the transfer function of real modulator is symmetrical with respect to DC, and it cannot reject image signal.



To get a trans function that is non-symmetrical with respect to DC, it can move the real pole toward the positive or negative frequency. When z is changed to z ? (d + jc), the new complex integrator has an un-conjugate complex pole which equals to 1 + d + jc, and the complex integrator’s trans function is described as below:

$$H(z) = frac{1}{{z - 1 - (d + jc)}}.$$

(2)

In the polar coordinates, this pole movement can realize by rotating from the real pole with an angle θ, the pole frequency f_p (co-defined by f_s and θ) and its value have an equation shown as below:

$$theta = frac{{{F_{ m p}}}}{{{F_{ m s}}}} times 360 = {tan ^{ - 1}} frac{c}{{1 + d}}.$$

(3)

The complex integrator expressed in Eq. (2) can be described by the signal-flow graph (SFG) illustrated in Fig. 3, in which double lines represent complex signals operation^[11].






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Figure3.
Signal flow graph of complex integrator.




The complex product of integrator output and feedback coefficient can be spread as below:

$$begin{split}&left[ {YR(z) + j times YI(z)} ight] times left[ {d + j times c} ight] & quad = left[ {d times YR(z) - c times YI(z)} ight] + j times left[ {d times YI(z) + c times YR(z)} ight].end{split}$$

(4)

In the real word, the circuit can only process real signal, but as described in the Eq. (4), the complex signal processing can be implemented by calculating the real part and image part separately. Hence, the complex integrator can be realized with two real integrators cross coupled with real coefficients, which is shown in Fig. 4. Another piece of good information from Fig. 4 is that the complex integrator’s real part and image part are identical to each other, so the circuit and layout design workload can be halved. The negative value for one of the feedback coefficients can be easily realized in a fully differential circuit.






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Figure4.
Complex integrator realized by cross-coupled real integrators.

2.2
?1 MHz IF quadrature bandpass sigma–delta modulator

A sigma–delta modulator’s dynamic range (DR) is determined by the modulator’s order (L) oversampling ratio (OSR) and quantizer’s bits (N), this relationship can be described as below^[9]

$${ m {DR}} = frac{{3(2L + 1)}}{{2{pi ^{2L}}}} times { m {OS}}{{ m R}^{2L + 1}} times {({2^N} - 1)^2}.$$

(5)

The receiver’s requirement for ADC quantization is 76 dB with a 48 MHz sampling clock. A 3rd order modulator is a safe consideration for design margin, and a 1.5 bit comparator is used due to its simple hardware implementation and inherent linearity. Ideally, a 103 dB DR can be achieved with this 3rd order modulator. The modulator’s NTF can be synthesized with sigma–delta toolbox^[9], and is shown as below:

$${ m {NTF}} = frac{{(z - 1)({z^2} - 1.998z + 1)}}{{(z - 0.669)({z^2} - 1.53z + 0.6635)}}.$$

(6)

As both of the zeros of NTF and the pole of integrator can define the noise stopband, the NTF’s zeros can be equivalent to the integrator’s pole. The modulator’s integrator poles are listed in Table 1. As described in Section 2.1, the optimal complex sigma–delta modulator can be built by rotating the real pole by ?1/48 * 2π radians in pole coordinate. Mathematically, this rotation can be implemented by multiplying the real pole by a complex number, which is shown as below:

$${{ m e}^{ - j , times , 360/48}} = 0.9914 - j times 0.1305.$$

(7)

After the pole movement, the complex integrator’s poles are listed in Table 1. As shown in Table 1, the real parts of the pole movements are almost zero; but the image parts introduce a reduction about 0.13. So, the creation of a quadrature bandpass sigma–delta modulator from the real modulator, which is described in Eq. (6), can be implemented by replacing the real integrator with complex ones shown in Fig. 4, and making the coefficients d equal to zero, and c equal to 0.13.

	Pole name	Real-SDM	Complex-SDM	Image-Delta
	Real-Pole	1	0.9914 ? j0.1305	0.1305
	Complex-Pole1	0.9989 + j0.0468	0.9842 ? j0.084	0.1308
	Complex-Pole2	0.9989 ? j0.0468	0.9964 ? j0.1768	0.1300

Table1.
Pole movement.



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	Pole name	Real-SDM	Complex-SDM	Image-Delta
	Real-Pole	1	0.9914 ? j0.1305	0.1305
	Complex-Pole1	0.9989 + j0.0468	0.9842 ? j0.084	0.1308
	Complex-Pole2	0.9989 ? j0.0468	0.9964 ? j0.1768	0.1300

In this paper, the modulator works under a 1.8 V power supply voltage, and for maximizing the dynamic range, the modulator’s reference voltage is set to equal to supply voltage. The integrator’s output swing can cover the range of 0.3–1.5 V. Through the coefficient scaling with delta–sigma toolbox^[9], a CRFB modulator with ideal coefficient values listed in Table 2 (real column) can make the modulator keep unsaturated with full-scale input, those scaled coefficients make the modulator’s SNDR achieve the peak value. For the consideration of real circuit implementation, the precise decimal value is replaced by the approximate fractions. In order to share the integrating capacitor in the switched capacitor integrator, the feedforward and feedback coefficient in the 2nd and 3rd order integrators are set the same values. The circuit realized coefficients are listed in the real columns in Table 2.

Name	Ideal	Real	Name	Ideal	Real
a1	0.1	1/8	c1	0.3561	2/8
a2	0.2425	2/8	c2	0.3778	3/8
a3	0.3561	3/8	c3	5.5	5.5
b1	0.044	1/16	g	0.006	1/240

Table2.
Modulator coefficient values.



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Name	Ideal	Real	Name	Ideal	Real
a1	0.1	1/8	c1	0.3561	2/8
a2	0.2425	2/8	c2	0.3778	3/8
a3	0.3561	3/8	c3	5.5	5.5
b1	0.044	1/16	g	0.006	1/240

The cross-coupled coefficient c in Fig. 4 will also share the integrating capacitor, hence, the final value of c is set to 1/8. The final quadrature bandpass sigma–delta modulator’s signal flow graph is shown in Fig. 5. For simplifying of quantizer implementation, c₃ is set to unit, and the reference voltage of the quantizer will set to 1.8/5.5 accordingly.






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Figure5.
Proposed quadrature bandpass sigma–delta modulator.

2.3
System simulation and modeling

The 1st order integrator’s input sampling noise cannot be shaped by the modulator, so it is another modulator bottleneck, here the capacitor value is calculated to be 140 fF, and the capacitor unit C₀ is set to 70 fF. The modulator in Fig. 5 is simulated in MATLAB with a ?0.6 dBFS input signal, and the complex output’s power spectrum density is shown in Fig. 6. As shown in Fig. 6, with FFT dynamic test method, we can find that this modulator has an SNDR up to 93 dB, so there is enough margin for circuit implementation.






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Figure6.
PSD of proposed modulator in MATLAB modeling.




With MATLAB modeling, NMOS and PMOS transistor in CMOS switch are 4 and 8 μm. With a large range scanning analysis, the opamp’s design specifications can be acquired as listed in Table 3^[12]. This paper’s modulator is a single loop structure, so there is no trans function mismatch issue between analog and digital circuit^[13], and low DC gain opamp can be employed, here folded-cascoded opamp is used for three integrators^[14].

Parameter	1st opamp	2nd opamp	3rd opamp
Slew rate (MV/s)	120	60	60
DC gain (dB)	50	52	52
GBW (MHz)	550	280	280
Von (mV)	40	60	60
Power current (μA)	490	240	240

Table3.
Opamp design specifications.



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Parameter	1st opamp	2nd opamp	3rd opamp
Slew rate (MV/s)	120	60	60
DC gain (dB)	50	52	52
GBW (MHz)	550	280	280
Von (mV)	40	60	60
Power current (μA)	490	240	240

3.
Circuit design

3.1
Switch capacitor modulator

The modulator in Fig. 5 is implemented with switched capacitor circuit, and the real 3rd order Sigma-Delta modulator is shown in Fig. 7(a), with cross-coupling between every integrator’s input and output shown as Fig. 7(b), the whole quadrature bandpass sigma–delta modulator is made of two identical real modulators. As shown in Fig. 7(a), C_S2 is shared by a₂ and c₁, C_S3 is shared bya₃ and C₂, those capacitors sharing circuits can reduce chip area. Two fully differential comparators with opposite reference inputs can define three voltage ranges according to three output levels.






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Figure7.
(a) Real 3rd order sigma–delta modulator. (b) Quadrature bandpass sigma–delta modulator.




In order to achieve good layout matching, all of the capacitors including opamp common mode feedback network use the same capacitor unit. All of the capacitor values in Fig. 7(a) are shown in Table 4.

Cap	1st integrator	2nd integrator	3rd integrator	Zero cap
CS	2C0	2C0	3C0	CZ3 = 1C0
CIQ	4C0	1C0	1C0
CFB	2C0	CS share	CS share	CZ3 = 28C0
CI	32C0	8C0	8C0	CZ3 = 1C0

Table4.
Modulator capacitor value.



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Cap	1st integrator	2nd integrator	3rd integrator	Zero cap
CS	2C0	2C0	3C0	CZ3 = 1C0
CIQ	4C0	1C0	1C0
CFB	2C0	CS share	CS share	CZ3 = 28C0
CI	32C0	8C0	8C0	CZ3 = 1C0

3.2
Zero coefficient implementation

The zero coefficient g is 1/240, and the 2nd order integrator’s integrating capacitor is 8C₀, so a capacitor equal to C₀/30 is needed for the implementation of g. A clock controlled series capacitor network shown in Fig. 7(a) can achieve this fraction. For a detailed introduction, when the network works in phase PH1, the zero feedback network is shown in Fig. 8. In this phase, the 3rd order integrator’s output voltage is sampled in the bottom plate of C_Z1.






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Figure8.
PH1 Phase network of zero feedback.




When the network works in phase PH2, the zero feedback network is shown in Fig. 9. First of all, the sampled charge will be redistributed between C_Z1 and C_Z2, and the equivalent sampling voltage will be V_OUT³ $times $ C_Z1/(C_Z1 + C_Z2), the equivalent feedback capacitor of the series capacitor net is equal to C_Z3 $ times $ (C_Z1 + C_Z2)/(C_Z1 + C_Z2 + C_Z3), then the exact zero feedback coefficient can be expressed as below, which is exactly equal to 1/240.






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Figure9.
PH2 Phase network of zero feedback.

$$C_{ m {Z1}} times C_{ m Z3}/(C_{ m Z1} + C_{ m Z2} + C_{ m Z3})/C_{ m I2}.$$

(8)

The quantizer has three output levels, when the comparison result is +1 or ?1, the reference voltage buffer’s capacitor load will be C_S1 + C_FB1 + C_S2 + C_S3; but when the comparison result is 0, the reference voltage buffer will have no capacitor loading. This dramatic load difference will introduce a signal-dependent noise. A quantizer result controlled dummy capacitor load will keep its capacitor loading unchanged. The dummy capacitor load is shown Fig. 10. For layout matching consideration, the dummy capacity is split and placed close to the different integrators.






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Figure10.
Dummy capacitor load for reference voltage buffer.

3.3
Comparator

In this paper, a fully differential and regeneration comparator is used, its schematic is shown in Fig. 11. Both the signal and reference voltage input are differential, it is very easy to achieve ±V_ref comparison. There is no DC current consumption in the comparator.






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Figure11.
Fully differential input comparator.

4.
Measurement result

Fig. 12 shows a photograph of the fabricated modulator that is integrated in a 2.4 GHz low-IF receiver. For noise and drive consideration, an independent and fast settling reference voltage generator is used for the modulator. The modulator is tested when the receiver is in test mode, and the input signal is fed from the test mux-array. In order to achieve good quadrature matching, the real and image parts of the modulator are totally symmetric. The modulator is designed in a 0.18 μm CMOS technology with MIM device enabled, and the chip occupies an area with 700 × 680 μm² including reference voltage generator.






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Figure12.
(Color online) Photograph of the fabricated modulator in transceiver.




The whole transceiver’s test board is shown in Fig. 13, the quadrature bandpass modulator’s differential input signals can be provided by the signal generator through test pin TIP/TIN and TQP/TQN, the signal fed to TIP/TIN is a sine wave with phase delay equal to π/2, and the signal fed to TQP/TQN is a sine wave with phase delay equal to π, they are real and imaginary part of an exponential signal with negative frequency, and the frequency is calculated by the equation: 317 × 48 MHz/16384 = 928.71 kHz, here 16384 is FFT points number, with the signal bin equal to 317 can avoid repeated sampling and make the input signal frequency close to the modulator’s center frequency. The modulator’s output signals (ADCI1 & ADCI0 and ADCQ1 & ADCQ0) are sampled by the logic analyzer at the rise edge of ADCCK, this synchronized clock comes from the modulator’s quantizer.






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Figure13.
(Color online) PCB test board of proposed modulator.




The modulators’ output signals are 2-bits two’s complement signals, they are converted to decimal and then expressed to a complex signal with the equation: ADCI + j*ADCQ, then FFT analysis of this complex signal is taken in MATLAB workstation to estimate the modulator’s frequency specification. Fig. 14 compares the post simulation and measured results with ?0.6 dBFS input. As this figure shows, the noise floor of test PSD is higher than the simulation result by about 14 dB, this noise floor raise is mostly because of the test signal input routing pass through a long way and noisy circuitry; when the receiver works in the normal mode, the modulator’s inputs are connected to the previous stage directly, and the noise floor can reduce.






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Figure14.
(Color online) PSD of post simulation and testing results.




Fig. 15 shows two tones input result with frequency equal to 897 kHz and 1.102 MHz, and input signal amplitude is ?0.6 dBFS. The largest distortion has been drowned out by the noise floor due to the test routing issue as mentioned above. As we can see the worst IM3 distortion is lower than ?59.86 dB.






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Figure15.
Two tones test PSD of proposed modulator.




The measured power dissipation is less than 3.78 mW at 1.8 V supply voltage. Table 5 provides a summary and comparison of the modulator’s key specifications. From the table, it can see that when order and OSR are comparable, this work has much better performance than work^[16]. CT modulator has the problem of pole drift caused by RC variations, and it needs additional calibration circuitry. In Ref. [15], much higher order and OSR are employed to achieve comparable specifications, it will dramatically increase the modulator’s complexity.

	Parameter	Ref. [15]	Ref. [16]	This work
	Bandwidth (MHz)	1	1	1
	IF (MHz)	0.5	1	?1
	fs (MHz)	64	32	48
	Modulator	5th CT	3rd CT	3rd SC
	DR (dB)	76	60	70
	SNDRpeak (dB)	75.5	58.6	> 69
	Image rejection (dB)	> 47	44.6	---
	IM3 distortion (dBc)	< ?82	?49	< ?58
	Power (mA)	2.44 @ 1.8 V	1.42 @ 1.2 V	2.1 @ 1.8 V
	Technology (μm)	0.18	0.13	0.18
	Area (mm2)	0.22	0.62	0.48

Table5.
Test results and comparison.



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	Parameter	Ref. [15]	Ref. [16]	This work
	Bandwidth (MHz)	1	1	1
	IF (MHz)	0.5	1	?1
	fs (MHz)	64	32	48
	Modulator	5th CT	3rd CT	3rd SC
	DR (dB)	76	60	70
	SNDRpeak (dB)	75.5	58.6	> 69
	Image rejection (dB)	> 47	44.6	---
	IM3 distortion (dBc)	< ?82	?49	< ?58
	Power (mA)	2.44 @ 1.8 V	1.42 @ 1.2 V	2.1 @ 1.8 V
	Technology (μm)	0.18	0.13	0.18
	Area (mm2)	0.22	0.62	0.48

5.
Conclusions

This paper demonstrates that a fully- integrated high-performance switched capacitor quadrature bandpass sigma– delta modulator with a center frequency of ?1 MHz can be implemented in 0.18 μm CMOS. A pole movement system design method is used to transform a real modulator to a quadrature one. For area saving consideration, integrator sampling capacitor sharing integrator is used, and a novel series capacitor network is employed to implement a very small feedback coefficient. Quantizer’s output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. A prototype 3rd order quadrature bandpass modulator integrated in 2.4 GHz low-IF receiver with 1 MHz bandwidth and ?1 MHz IF center frequency, shows a 69 dB testing SNDR, it can verify the study and design process described in this paper.