State Key Laboratory of Mechanics and Control of Mechanical Structures, Interdisciplinary Research Institute of Aeronautics and Astronautics, College of Aerospace Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China
Fund Project:Project supported by the National Natural Science Foundation of China (Grant No. 11902149), the Natural Science Foundation of Jiangsu Province, China (Grant No. BK20190380), and the Priority Academic Program Development of Higher Education Institutions of Jiangsu Province, China.
Received Date:15 June 2020
Accepted Date:28 July 2020
Available Online:04 December 2020
Published Online:20 December 2020
Abstract:The large volume change during lithiation/delithiation leads the silicon electrodes in lithium-ion batteries to severely degrade the mechanical performance and the silicon electrodes in lithium-ion batteries to further deteriorate electrochemical properties, which limits the commercial applications of silicon electrodes. After several year’s studies, the whole process of fracture for crystalline silicon anodes has been almost understood. However, the relationship between fracture behaviors and the lithiation depth has not been sufficiently studied. In this work, the in-situ observations of morphological changes (e.g., volume expansion, crack initiation, propagation, and debonding of lithiated silicon) during lithiation at the different current densities are reported for silicon micropillars fabricated by standard photolithography and a deep reactive ion etching process. Also, this work focuses on the relative depth of lithiation of silicon electrodes at the moment of crack initiation, which is one of the crucial parameters representing the utilization of active materials with no crack. The results show that the silicon micropillars are broken faster (i.e., crack initiation and pulverization in a shorter lithiation time) and more seriously at a large current density, exhibiting more prominent symmetry of morphology. However, the relative depths of lithiation at the different current densities have just a slight difference (i.e., 18%–22%), when cracks are initiated. Here in this work, a silicon micropillar fracture is confirmed by the optical observation, while the relative depth of lithiation is calculated according to the capacity data recorded by the charge/discharge battery test system. The small fluctuation of the relative depth of lithiation with the large wave of current density can be ascribed to the dominant role of local stress concentration caused by anisotropic volume change in fracture behavior, which is validated by the results obtained by the finite element model (i.e., the depth of lithiation predicted by numerical simulations is ~ 22.6%). Therefore, the relationship between fracture behavior and the lithiation kinetics is established, providing an effective strategy for estimating the utilization of active materials under crack-free operation. With the help of the theoretical mechanics model considering both volume change and concurrent movement of reaction front, the stress state in the lithiated silicon at the moment of crack initiation is given, showing the tensile hoop stress near the reaction front. Consequently, these results suggest that the fracture behaviors depend on the current density, but the position of crack initiation (i.e., the depth of lithiation with no crack) is unrelated to current density (at least in a relatively broad range) for large micron-sized crystalline silicon electrodes, thereby shedding light on the fracture mechanisms and the design of alloy anodes (e.g., size and structure) in lithium-ion batteries. Keywords:lithium-ion battery/ silicon electrode/ fracture behavior/ current density
微米尺寸硅电极脱/嵌锂过程中由于过大的体积变形会在电极内部产生较大的应力, 最终导致裂纹形成、扩展和电极颗粒粉化. 本文重点关注不同电流密度对硅电极裂纹形成阶段的影响. 裂纹形成时对应的锂化时间和电压关系如图5所示. 需要说明的是, 在电压大于0.12 V时硅电极并没有发生嵌锂变形[10], 意味着绝大部分硅电极的嵌锂过程发生在0.12 V以下. 因此, 为了消除副反应等影响, 将锂化时间定义为T = Tt – TU = 0.12 V. 这里Tt是当前所关心时刻对应的总放电时间(嵌锂时间), TU = 0.12 V是电压U = 0.12 V时对应的放电时间. 从图5可看出, 电流密度越大, 起裂时间越早, 并且从起裂阶段(如图4(c)、图4(g)和图4(k))到破坏阶段(如图4(d)、图4(h)和图4(l))的间隔时间越短. 图 5 不同电流密度下硅电极裂纹形成时对应的锂化时间和电压, 标尺为5 μm Figure5. Profile of voltage and lithiation time for crack initiation of silicon electrodes at different current density. Here, the scale bars are 5 μm.
本文所设计的硅柱电极尺寸在20 μm左右, 在恒电流放电下硅柱几乎都会发生断裂现象, 且断裂位置位于两个{110}晶面相交处附近, 这主要是由于单晶硅电极各向异性体积变形, 导致在两个{110}晶面相交处产生局部的应力集中或者应变集中, 最终造成硅电极裂纹形成, 如图6(b)所示. 在前文中提到, 电流密度越大, 裂纹形成对应的锂化时间越短. 但目前对于嵌锂深度与裂纹形成的关系及不同电流密度对硅电极裂纹形成阶段的影响还有待进一步分析. 因此, 这里统计分析了不同电流密度下硅电极裂纹形成时的相对嵌锂深度, 如图6所示. 本文中将相对嵌锂深度定义为(Capacityt –CapacityU = 0.12 V)与Capacitytheory的比值. 这里Capacityt指裂纹形成时充放电测试系统记录的容量, CapacityU = 0.12 V是电压为0.12 V时对应的容量, Capacitytheory是硅柱的理论容量. 因为我们关心的是硅柱的嵌锂程度, 所以在计算相对嵌锂深度时需要排除硅基底的嵌锂影响(如图7所示). 从图6(a)可以看出, 在三种不同电流密度放电(嵌锂)过程中, 即使起裂时锂化时间和锂化硅剥离时间差异明显, 硅电极起裂时相对嵌锂深度差异也不大(相对锂化深度在18%—22%之间), 这个现象需要并值得进一步分析和讨论. 现有研究已经表明(111)单晶硅锂化过程与晶向相关, 理想情况下形貌呈现出六重对称性, 未锂化晶体硅柱是六棱柱形状(如图1所示). 根据这一特点和圆内切正六边形与圆面积比值关系可计算出理想情况下未锂化硅的正六边形截面刚与硅柱圆截面内切时嵌锂深度为17.4%. 因此, 实验所得的相对嵌锂深度结果表明硅电极开裂发生在此情形(与圆截面内切)之后. 为了进一步解释实验现象, 利用ABAQUS建立了二维平面应变有限元模型, 如图6(b)所示. 在单晶硅电极锂化过程的有限元模拟中, 根据两相扩散假设, 通过预定义温度场方法模拟相边界移动速度. 在模型中, 晶体硅和锂化硅分别假设为各向同性的线弹性材料(弹性模量为185 GPa、泊松比为0.28)和弹塑性材料(弹性模量为35 GPa, 泊松比为0.22, 屈服强度为1.5 GPa). 由图6(b)可知, 对于理想嵌锂过程, 两相界面刚过圆截面内切处后不久, 在两个{110}晶面相交处发生了局部应力集中现象, 假设这时达到了裂纹形成的条件. 由模拟结果计算得到起裂时嵌锂深度约22.6%, 并且对于不同的相边界移动速度, 应力集中程度(或裂纹形成)几乎一致, 如图6(c)所示. 换句话说, 基于该有限元模型假设, 发现在不同的嵌锂速度下硅电极起裂时嵌锂深度相同. 这些模拟结果很好地解释了不同电流密度下相对嵌锂深度差异很小的实验结果. 这里需要说明的是, 有限元模型中忽略了锂化硅塑性变形的率相关性[32,33], 即忽略了应变率对锂化硅塑性变形的影响, 只考虑了相界面位置的影响. 对于实验结果所得的相对嵌锂深度小于模拟结果的原因, 可能来源于副反应和硅基底引起的锂损失、实验中非理想嵌锂过程的发生以及模型中忽略率相关塑性的影响所导致的应力偏小[34]. 图 6 (a) 不同电流密度下硅电极起裂时相对嵌锂深度; (b) 有限元模拟所得的应力云图; (c) 不同相边界移动速度下不同r/R (红色箭头标示)处径向应力分布 Figure6. (a) Relative lithiation depth for crack initiation of silicon electrodes at different current density; (b) hoop stress contour of Si micropillars obtained by finite element method; (c) hoop stress along the radial direction at different moving velocity of phase interfaces.
图 7 硅基底锂化后形貌, 标尺为500 nm Figure7. Morphology of the silicon substrate after lithiation. Here, the scale bar is 500 nm.
虽然晶体硅电极锂化过程中各向异性变形给理论分析带来了挑战, 但是依然可以通过一些合理的假设建立力学理论模型, 以描述晶体硅电极变形和断裂行为的主要特征[19,20]. 这里, 在理论模型中假设所有晶向的反应前端移动速度相同, 硅柱电极横截面在锂化过程中可分为3个区域(如图8所示): 全锂化区域(I < r ≤ rc)、反应前端(r = I )和未锂化晶体硅区域(0 ≤ r < I ). 基于锂化硅是各向同性的理想刚塑性材料的假设, 参考Jia和Li[19]建立的考虑反应前端移动和体积膨胀变形共存状态下硅柱电极锂化诱导应力的力学模型. 根据此模型, 全锂化区域(I < r ≤ rc)的应力分布可以表示为 图 8 (a) 锂化前硅柱圆截面示意图; (b) 锂化过程中硅柱圆界面示意图 Figure8. Cross-section of a silicon micropillar: (a) Before lithiation; (b) during lithiation.