西安电子科技大学微电子学院导师教师师资介绍简介-李聪

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基本信息
李聪博士
副教授/博士生导师/硕士生导师
博士学科：电子科学与技术
硕士学科：微电子学与固体电子学
工作单位：微电子学院

联系方式
通信地址：西安市太白南路2号415信箱
电子邮箱：licong@xidian.edu.cn
办公电话：+
办公地点：北校区新科技楼A-501

个人简介
李聪 1981年生，博士、副教授、博士生导师。分别于2003年、2006年及2011 年在西安电子科技大学取得学士、硕士以及博士学位。2006年留校参加工作，主要研究方向为新型半导体器件及电路研究。2008年在芬兰奥卢（oulu）大学访问研究，2011 年在欧洲微电子中心（IMEC）访问研究。2015年-2016年在美国佛罗里达大学（UF）访问研究。主持国家自然科学基金两项，参与多项*科研项目*，发表论文30余篇，专利5个。

主要研究方向
1．新型半导体器件模型与TCAD仿真
2. 超大规模集成电路（VLSI）设计自动化

科学研究
目前研究团队承担的科研项目：
横向合作项目：《先进集成电路EDA系统关键技术研究与模块开发》，2019-2021，参与
国家自然科学基金：《InGaAs围栅纳米线TFET器件研究》，2016年1月至2019年12月。主持
*科研项目*：《电子轰击型CMOS低噪声电路的仿真研究》，2018.07至2020.07.主持
横向合作项目：《先进集成电路EDA系统关键技术研究与模块开发》2019.02-2021.02. 主持
国家自然科学基金：《无结围栅纳米线MOSFET 的短沟道效应研究》，批准号：**，2013年1月至2015年12月。主持
中央高效基本科研业务费：《高k栅介质异质围栅MOSFET器件研究》，批准号：K，2011年至2013年。主持
国家自然科学基金：《高k介质MOS器件共振隧穿低频噪声模型及应用研究》，批准号：**，2011年1月至2013年12月。

学术论文
C. Li, J. Guo, H. Jiang, H. You, W. Liu, and Y. Zhuang, “A novel gate engineered L-shaped dopingless tunnel field-effect transistor,” Appl. Phys. A, vol. 126, no. 6, p. 412, May 2020, doi: 10.1007/s00339-020-03554-x.
Z. Yan, C. Li, J. Guo, and Y. Zhuang, “A GaAs Sb /In Ga0.47As heterojunction Z-gate TFET with hetero-gate-dielectric,” Superlattices and Microstructures, vol. 129, pp. 282–293, May 2019, doi: 10.1016/j.spmi.2019.04.006.
J.-M. Guo, C. Li, Z.-R. Yan, H.-F. Jiang, and Y.-Q. Zhuang, “Analysis of interface trap charges on performance variation in L-shaped tunnel field-effect transistor,” Micro & Nano Letters, vol. 14, no. 11, pp. 1140–1145, Sep. 2019, doi: 10.1049/mnl.2019.0129.
Z. Yan, C. Li, J. Guo, H. Jiang, J. Chen, and Y. Zhuang, “An Optimized GaAsSb/InGaAs Heterojunction L-shape Tunnel Field-Effect Transistor,” in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2018, pp. 1–3, doi: 10.1109/ICSICT.2018.**.
C. Li, X. Zhao, Y. Zhuang, Z. Yan, J. Guo, and R. Han, “Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement,” Superlattices and Microstructures, vol. 115, pp. 154–167, Mar. 2018, doi: 10.1016/j.spmi.2018.01.025.
C. Li, Z.-R. Yan, Y.-Q. Zhuang, X.-L. Zhao, and J.-M. Guo, “Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric,” Chinese Phys. B, vol. 27, no. 7, pp. 78502–078502, 2018, doi: 10.1088/1674-1056/27/7/078502.
J. Guo, C. Li, Z. Yan, H. Jiang, J. Chen, and Y. Zhuang, “Influence of trap-assisted tunneling on Subthreshold Slope of Ge/Si heterojunction L-shaped TFETs,” in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2018, pp. 1–3, doi: 10.1109/ICSICT.2018.**.
Z. Jiang, Y. Zhuang, C. Li, and P. Wang, “Tunnel Dielectric Field-Effect Transistors with High Peak-to-Valley Current Ratio,” Journal of Electronic Materials, vol. 46, no. 2, pp. 1088–1092, Feb. 2017, doi: 10.1007/s11664-016-5021-4.
Z. Jiang, Y. Zhuang, C. Li, P. Wang, and Y. Liu, “Impact of low/high-κ spacer–source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor,” J. Cent. South Univ., vol. 24, no. 11, pp. 2572–2581, Nov. 2017, doi: 10.1007/s11771-017-3671-x.
P. Wang, Y. Zhuang, C. Li, Y. Liu, and Z. Jiang, “Potential-based threshold voltage and subthreshold swing models for junctionless double-gate metal-oxide-semiconductor field-effect transistor with dual-material gate,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 29, no. 2, pp. 230–242, Mar. 2016, doi: 10.1002/jnm.2067.
P. Wang, Y. Zhuang, C. Li, Z. Jiang, and Y. Liu, “Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket,” Microelectronics Reliability, vol. 59, pp. 30–36, Apr. 2016, doi: 10.1016/j.microrel.2015.09.014.
Z. Jiang, Y.-Q. Zhuang, C. Li, P. Wang, and Y.-Q. Liu, “Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor,” Chinese Phys. B, vol. 25, no. 2, p. 027701, 2016, doi: 10.1088/1674-1056/25/2/027701.
Z. Jiang et al., “Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors, Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors,” Journal of Electrical and Computer Engineering, Journal of Electrical and Computer Engineering, vol. 2015, 2015, p. e630178, Sep. 2015, doi: 10.1155/2015/630178, 10.1155/2015/630178.
Z. Jiang et al., “Drive Current Enhancement in TFET by Dual Source Region, Drive Current Enhancement in TFET by Dual Source Region,” Journal of Electrical and Computer Engineering, Journal of Electrical and Computer Engineering, vol. 2015, 2015, p. e905718, May 2015, doi: 10.1155/2015/905718, 10.1155/2015/905718.
L. Yu-An, Z. Yi-Qi, M. Xiao-Hua, D. Ming, B. Jun-Lin, and L. Cong, “A unified drain current 1/ f noise model for GaN-based high electron mobility transistors,” Chinese Phys. B, vol. 23, no. 2, p. 020701, 2014, doi: 10.1088/1674-1056/23/2/020701.
P. Wang, Y. Zhuang, C. Li, Y. Li, and Z. Jiang, “Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack,” Japanese Journal of Applied Physics, vol. 53, no. 8, p. 084201, Aug. 2014, doi: 10.7567/JJAP.53.084201.
P. Wang, Y. Zhuang, C. Li, and Z. Jiang, “Analytical modeling for double-gate TFET with tri-material gate,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2014, pp. 1–3, doi: 10.1109/ICSICT.2014.**.
L. Shi, Y. Zhuang, C. Li, and D. Li, “Analytical modeling of the direct tunneling current through high- k gate stacks for long-channel cylindrical surrounding-gate MOSFETs,” J. Semicond., vol. 35, no. 3, p. 034009, 2014, doi: 10.1088/1674-4926/35/3/034009.
Y. Liu, Y. Zhang, and C. Li, “Quantum percolation tunneling current 1/f,” Sci. China Phys. Mech. Astron., vol. 57, no. 9, pp. 1637–1643, Jul. 2014, doi: 10.1007/s11433-014-5444-y.
C. Li, Y. Zhuang, P. Wang, Z. Jiang, and L. Zhang, “A new analytical model for junctionless cylindrical surrounding-gate MOSFETs,” in 2014 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Jun. 2014, pp. 1–2, doi: 10.1109/EDSSC.2014.**.
C. Li, Y. Zhuang, R. Han, and G. Jin, “Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET,” Microelectronics Reliability, vol. 54, no. 6–7, pp. 1274–1281, Jun. 2014, doi: 10.1016/j.microrel.2014.02.007.
C. Li, Y.-Q. Zhuang, L. Zhang, and G. Jin, “Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate,” Chinese Phys. B, vol. 23, no. 1, p. 018501, 2014, doi: 10.1088/1674-1056/23/1/018501.
C. Li, Y.-Q. Zhuang, L. Zhang, and G. Jin, “A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs,” Chinese Phys. B, vol. 23, no. 3, p. 038502, 2014, doi: 10.1088/1674-1056/23/3/038502.
Z. Jiang, Y. Zhuang, C. Li, and W. Ping, “The hetero material gateand hetero-junction tunnel field-effect transistor with pocket,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2014, pp. 1–3, doi: 10.1109/ICSICT.2014.**.
C. Li, Y. Zhuang, S. Di, and R. Han, “Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3655–3662, Nov. 2013, doi: 10.1109/TED.2013.**.
C. Li, Y. Zhuang, L. Zhang, and J. Bao, “Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric,” Chinese Phys. B, vol. 21, no. 4, p. 048501, 2012, doi: 10.1088/1674-1056/21/4/048501.
C. Li, Y.-Q. Zhuang, R. Han, L. Zhang, and J. Bao, “Analytical modeling of asymmetric HALO-doped surrounding-gate MOSFET with gate overlapped lightly-doped drain,” Acta Phys. Sin., vol. 61, no. 7, p. 078504, Apr. 2012.
C. Li, Y. Zhuang, and L. Zhang, “Simulation study on FinFET with tri-material gate,” in 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), Dec. 2012, pp. 1–3, doi: 10.1109/EDSSC.2012.**.
C. Li, Y. Zhuang, and R. Han, “New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs,” J. Semicond., vol. 32, no. 7, p. 074002, 2011, doi: 10.1088/1674-4926/32/7/074002.
C. Li, Y. Zhuang, and R. Han, “Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension,” Microelectronics Journal, vol. 42, no. 2, pp. 341–346, Feb. 2011, doi: 10.1016/j.mejo.2010.11.010.
C. Li, Y. Zhuang, R. Han, G. Jin, and J. Bao, “Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions,” Microelectronics Reliability, vol. 51, no. 12, pp. 2053–2058, Dec. 2011, doi: 10.1016/j.microrel.2011.04.017.
C. Li, Y.-Q. Zhuang, and R. Han, “Analytical Threshold Model for Nanoscale Cylindrical Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistor with High-κ Gate Dielectric and Tri-Material Gate Stack,” Japanese Journal of Applied Physics, vol. 49, no. 12, p. 124202, Dec. 2010, doi: 10.1143/JJAP.49.124202.

荣誉获奖
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科研团队
团队教师
李聪
硕士研究生
刘予琪（2016年毕业）-深圳国微电子
熊扬（2017年毕业）-上海格科微
赵小龙（2018年毕业）-联发科技（合肥）
闫志蕊（2019年毕业）-太原理工大学
朱文涛（2019年毕业）-中兴通讯
尹文倩（2019年毕业）-紫光展锐
郭嘉敏（2020年毕业）-上海AMD
张翔（2020年毕业）-深圳国微电子
毕海东（2020年毕业）-复旦微电子
操开波（2020年毕业）-中兴通讯
姜好峰
刘飞辰
刘鼎成

课程教学
目前本人承担的教学任务：
本科生课程：Physics of semiconductor devices （双语），微电子专业英语，集成电路专业英语
研究生课程：集成器件电子学，集成电路设计自动化（EDA）研讨课

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每年招收：博士研究生1名，硕士研究生3名，软件工程研究生2名

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