姚亚峰,邹凌志,王巍,钟梁
(中国地质大学(武汉) 机械与电子信息学院, 武汉430074)
摘要:
为减少传统流水线型CORDIC(Coordinate Rotation Digital Computer)算法的硬件资源消耗和输出时延,在包含查找表的三阶段CORDIC算法实现基础上,提出一种免去查找表环节的CORDIC算法实现方法.提出的改进算法直接使用四次移位相加的迭代运算替换查找表结构从而显著降低寄存器消耗,同时通过合并迭代降低迭代次数进而有效减少最大输出时延,并综合运用角度二极化重编码(Binary To Bipolar Recoding, BBR)方法和角度区间折叠技术保证了输出精度.使用Verilog HDL语言在ISE14.2软件平台上对三种算法进行具体实现,利用XST工具对其进行综合,并通过MATLAB建模计算得到算法的正余弦值输出误差.仿真实验结果表明:在输出位宽均设置为16位的情况下,免查找表CORDIC算法能够有效地输出正余弦值;与传统流水线型算法相比,免查找表算法的寄存器资源消耗减少大约74.42%,计算所需的时钟周期降低68.75%,其输出精度也有明显改善;与三阶段算法相比,免查找表算法的寄存器消耗减少大约43.3%.本文提出的免查找表CORDIC算法具有实时性强、输出精度高、硬件资源消耗少等优势,更适用于高速实时的现代数字通信系统应用.
关键词: 坐标旋转数字计算机 免查找表 二极化重编码 可编程逻辑门阵列 数字信号处理
DOI:10.11918/j.issn.0367-6234.201704019
分类号:TN492
文献标识码:A
基金项目:国家自然科学基金(61601334)
Low-consumption andLUT-omitted CORDIC algorithm
YAO Yafeng,ZOU Lingzhi,WANG Wei,ZHONG Liang
(Faculty of Mechanicaland Electronic Information, China University of Geosciences, Wuhan 430074, China)
Abstract:
In order to reduce the hardware resource consumption and output delay in the conventional pipeline CORDIC (Coordinate Rotation Digital Computer) algorithm, a LUT-omitted CORDIC algorithm is proposed on the basis of the three-stage CORDIC with look-up table (LUT). The proposed new algorithm adopts 4 iterations of shifter-adder instead of LUT to reduce the register consumption apparently, and merges some iterations to decrease the output delay effectively, and guarantees the output resolution by using a combination of Binary to Bipolar Recoding (BBR) and angle range folding. The improved algorithm is specifically implemented using Verilog HDL on ISE 14.2 software platform and synthesized using XST tools, and is modeled to analyze the output errors through MATLAB. Simulation experiment results show that the register resource consumption of the new algorithm, producing sine/cosine effectively, is reduced by about 74.42% compared with the conventional one, while the output width is set to 16 equally. The computing clock periods are decreased by 68.75%, and the resolution is also improved obviously. Compared with the three-stage algorithm, the consumption of register is reduced by about 43.3%. The proposed algorithm has some advantages such as brilliant real-time performance, high resolution, and low consumption. And it is more applicable for modern digital communication systems that demand for high speed and promising real-time performance.
Key words: coordinate rotation digital computer to omit look-up table binary to bipolar recoding field-programmable gate array digital signal processing
姚亚峰, 邹凌志, 王巍, 钟梁. 低消耗免查找表CORDIC算法[J]. 哈尔滨工业大学学报, 2017, 49(11): 109-114. DOI: 10.11918/j.issn.0367-6234.201704019.
![复制到剪切板](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/copy.gif)
YAO Yafeng, ZOU Lingzhi, WANG Wei, ZHONG Liang. Low-consumption andLUT-omitted CORDIC algorithm[J]. Journal of Harbin Institute of Technology, 2017, 49(11): 109-114. DOI: 10.11918/j.issn.0367-6234.201704019.
![复制到剪切板](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/copy.gif)
基金项目 国家自然科学基金(61601334) 作者简介 姚亚峰(1970—),男,副教授,硕士生导师 通信作者 王巍,993164156@qq.com 文章历史 收稿日期: 2017-04-05
Contents -->Abstract Full text Figures/Tables PDF
低消耗免查找表CORDIC算法
姚亚峰, 邹凌志, 王巍
![通讯作者](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/REcor.gif)
![993164156@qq.com](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/REemail.gif)
中国地质大学(武汉) 机械与电子信息学院,武汉430074
收稿日期: 2017-04-05
基金项目: 国家自然科学基金(61601334)
作者简介: 姚亚峰(1970—),男,副教授,硕士生导师
通信作者: 王巍,993164156@qq.com
摘要: 为减少传统流水线型CORDIC(Coordinate Rotation Digital Computer)算法的硬件资源消耗和输出时延,在包含查找表的三阶段CORDIC算法实现基础上,提出一种免去查找表环节的CORDIC算法实现方法.提出的改进算法直接使用四次移位相加的迭代运算替换查找表结构从而显著降低寄存器消耗,同时通过合并迭代降低迭代次数进而有效减少最大输出时延,并综合运用角度二极化重编码(Binary To Bipolar Recoding, BBR)方法和角度区间折叠技术保证了输出精度.使用Verilog HDL语言在ISE14.2软件平台上对三种算法进行具体实现,利用XST工具对其进行综合,并通过MATLAB建模计算得到算法的正余弦值输出误差.仿真实验结果表明:在输出位宽均设置为16位的情况下,免查找表CORDIC算法能够有效地输出正余弦值;与传统流水线型算法相比,免查找表算法的寄存器资源消耗减少大约74.42%,计算所需的时钟周期降低68.75%,其输出精度也有明显改善;与三阶段算法相比,免查找表算法的寄存器消耗减少大约43.3%.本文提出的免查找表CORDIC算法具有实时性强、输出精度高、硬件资源消耗少等优势,更适用于高速实时的现代数字通信系统应用.
关键词: 坐标旋转数字计算机 免查找表 二极化重编码 可编程逻辑门阵列 数字信号处理
Low-consumption andLUT-omitted CORDIC algorithm
YAO Yafeng, ZOU Lingzhi, WANG Wei
![Corresponding author](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/REcor.gif)
![993164156@qq.com](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/REemail.gif)
Faculty of Mechanicaland Electronic Information, China University of Geosciences, Wuhan 430074, China
Abstract: In order to reduce the hardware resource consumption and output delay in the conventional pipeline CORDIC (Coordinate Rotation Digital Computer) algorithm, a LUT-omitted CORDIC algorithm is proposed on the basis of the three-stage CORDIC with look-up table (LUT). The proposed new algorithm adopts 4 iterations of shifter-adder instead of LUT to reduce the register consumption apparently, and merges some iterations to decrease the output delay effectively, and guarantees the output resolution by using a combination of Binary to Bipolar Recoding (BBR) and angle range folding. The improved algorithm is specifically implemented using Verilog HDL on ISE 14.2 software platform and synthesized using XST tools, and is modeled to analyze the output errors through MATLAB. Simulation experiment results show that the register resource consumption of the new algorithm, producing sine/cosine effectively, is reduced by about 74.42% compared with the conventional one, while the output width is set to 16 equally. The computing clock periods are decreased by 68.75%, and the resolution is also improved obviously. Compared with the three-stage algorithm, the consumption of register is reduced by about 43.3%. The proposed algorithm has some advantages such as brilliant real-time performance, high resolution, and low consumption. And it is more applicable for modern digital communication systems that demand for high speed and promising real-time performance.
Key words: coordinate rotation digital computer to omit look-up table binary to bipolar recoding field-programmable gate array digital signal processing
坐标旋转数字计算机(Coordinate Rotation Digital Computer,CORDIC)是J.Volder于1959年提出的一种算法[1],这种算法通过一系列旋转角不断逼近目标角度,由移位相加迭代得到目标角度的正余弦值[2]. CORDIC算法具有硬件实现简单、速度快、精度可调等优点,在全数字锁相环、直接数字频率合成、快速傅里叶变换等领域有着广泛应用[3-6].传统的CORDIC算法采用流水线型结构[7],通过大量迭代来保证输出精度,因此存在硬件资源消耗过多、输出时延较长的问题.
随着现代数字通信系统集成化程度和精度的不断提高,许多学者对CORDIC算法提出改进方案.文献[8]提出一种贪婪搜索算法,采用跳过若干旋转角度和重复某些旋转角度的方法进行迭代,迭代次数有一定减少,但硬件复杂度明显增加.文献[9]采用一种混合结构,将旋转角度分为两部分处理,与传统流水线型CORDIC算法相比提高运算速度,但仍存在硬件消耗大、输出精度低的问题.文献[10]中的免缩放因子双步旋转算法免去缩放因子,减少迭代次数,但双步旋转的硬件实现结构较为复杂.文献[11]提出免缩放自适应CORDIC算法,虽然硬件资源消耗和误差有所减少,但是计算所需的时钟周期太长.文献[12-13]提出一种三阶段CORDIC算法,第一阶段通过查找表得到若干次迭代后的值,第二阶段采用移位相加的蝶形迭代运算,第三阶段进行合并迭代,相比于传统的流水线型CORDIC算法在精度和硬件消耗上都有一定改善,计算所需的周期少,具有一定代表性和优越性.
本文在文献[12-13]的基础上结合角度二极化重编码(Binary To Bipolar Recoding, BBR)、角度区间折叠、合并迭代等手段提出一种免查找表CORDIC算法,将三阶段缩减为两阶段实现.在典型的三阶段CORDIC实现方法基础上,将第一阶段的查找表直接替换为有限的几步移位相加迭代运算,有效减少寄存器消耗.此外,将第二阶段和第三阶段合并为一步迭代,大幅减少输出时延.用几步迭代运算代替查找表,使输出延时有所增加,但第二阶段的合并迭代只需要一个时钟周期,同时省去原有的蝶形运算阶段,整体只需要5个时钟周期就能得到输出结果,整体延时还有所降低.同时在综合采用角度二极化重编码和角度区间折叠技术后,改进算法的精度相比于传统实现方法也有一定改善.
1 CORDIC算法基本原理CORDIC算法通过一系列旋转角不断逼近输入角度,由移位相加迭代得到输入角度的正余弦值. 图 1为向量旋转图,在平面直角坐标系中将初始向量OA=(x1, y1)逆时针旋转角度θ到向量OB=(x2, y2),则坐标之间的关系为
Figure 1
![点击查看原图](http://hit.alljournals.cn/html/hitxb_cn/2017/11/PIC/hebgydxxb-49-11-109-1.jpg)
$\begin{array}{l}\left[\begin{array}{l}{x_2}\\{y_2}\end{array} \right] = \left[\begin{array}{l}\cos \theta \;\;\;\;\;\;-\sin \theta \\\sin \theta \;\;\;\;\;\;\;\;cos\theta \end{array} \right] = \\\cos \theta \left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;-\tan \theta \\\tan \theta \;\;\;\;\;\;\;\;\;1\end{array} \right]\left[\begin{array}{l}{x_1}\\{y_1}\end{array} \right].\end{array}$ (1)
将角度θ视为N个角度的累加和,即
$\begin{array}{l}\left[\begin{array}{l}{x_2}\\{y_2}\end{array} \right] = \cos {\theta _{N - 1}}\cos {\theta _{N - 2}} \cdots \cos {\theta _0} \cdot \\\left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;-\tan {\delta _{N-1}}{\theta _{N-1}}\\\tan {\delta _{N - 1}}{\theta _{N - 1}}\;\;\;\;\;\;\;\;\;\;1\end{array} \right]\\\left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;-\tan {\delta _{N-2}}{\theta _{N-2}}\\\tan {\delta _{N - 2}}{\theta _{N - 2}}\;\;\;\;\;\;\;\;\;\;\;1\end{array} \right] \cdots \cdot \\\left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;-\tan {\delta _0}{\theta _0}\\\tan {\delta _0}{\theta _0}\;\;\;\;\;\;1\end{array} \right]\left[\begin{array}{l}{x_1}\\{y_1}\end{array} \right] = \\K \cdot \left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;\;\;\;-\tan {\delta _{N-1}}{\theta _{N-1}}\\\tan {\delta _{N - 1}}{\theta _{N - 1}}\;\;\;\;\;\;\;\;1\end{array} \right] \cdot \\\left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;\;\;\;-\tan {\delta _{N-2}}{\theta _{N-2}}\\\tan {\delta _{N - 2}}{\theta _{N - 2}}\;\;\;\;\;\;\;\;1\end{array} \right] \cdots \\\left[\begin{array}{l}1\;\;\;\;\;\;\;\;\;\;-\tan {\delta _0}{\theta _0}\\\tan {\delta _0}{\theta _0}\;\;\;\;\;\;1\end{array} \right]\left[\begin{array}{l}{x_1}\\{y_1}\end{array} \right]\end{array}$ (2)
其中:K=cos θN-1cos θN-2…cos θ0称为校模因子,在N确定时可视为常数.令θi=arctan(2-i),在单次迭代时不考虑校模因子,那么有
2 免查找表CORDIC算法 2.1 角度二极化重编码对于取值为[0, π/8]的任意输入角度θ可用N位二进制小数示为
2.2 免查找表与合并迭代原理根据CORDIC算法的基本原理,可通过式(3)迭代得到输入角度的正余弦值
$\left\{ \begin{array}{l}{x_{k + 1}} = {x_k}-{r_k}\tan \left( {{2^{-k}}} \right){y_k}, \\{y_{k + 1}} = {y_k} + {r_k}\tan \left( {{2^{-k}}} \right){x_k}.\end{array} \right.$ (3)
式中k代表迭代次数.
在三阶段CORDIC算法中,对于输出N位的CORDIC算法,当k < N/3时可利用上式(3)建立第一阶段的小容量查找表.当N/3≤k < N/2时,利用tan(2-k)≈2-k进行第二阶段的蝶形运算,当k≥N/2时进行合并迭代.本文提出的免查找表CORDIC改进算法将第一阶段中tan(2-k)用二进制小数近似,对于输出为16位小数的CORDIC算法,第一阶段用到的近似如式(4)所示.
$\left\{ \begin{array}{l}\tan \frac{1}{8} \approx {2^{-3}} + {2^{-11}} + {2^{-13}} + {2^{ - 15}} + {2^{ - 17}}, \\\tan \frac{1}{{16}} \approx {2^{ - 4}} + {2^{ - 14}} + {2^{ - 16}}, \\\tan \frac{1}{{32}} \approx {2^{ - 5}} + {2^{ - 17}}, \\\tan \frac{1}{{64}} \approx {2^{ - 6}}.\end{array} \right.$ (4)
那么式(3)中乘以正切项就可视为移位相加运算,其中k=3对应的结构见图 2.
Figure 2
![点击查看原图](http://hit.alljournals.cn/html/hitxb_cn/2017/11/PIC/hebgydxxb-49-11-109-2.jpg)
图 2中(a)和(b)分别代表式(3)中的两个子式.通过这种近似方法,将查找表替换为移位相加的蝶形运算结构,从而减少寄存器消耗.
对于输出为N位小数的CORDIC算法,当迭代次数k≥N/2时,可作tan(2-k)≈2-k的近似,那么上式(3)所示的迭代可写为
2.3 区间角度折叠及映射关系对于(π/8, π/4]内的角度,存在式(5)所示的三角函数关系式
$\left\{ \begin{array}{l}\sin \left( {\frac{\pi }{4}-\theta } \right) = \frac{{\sqrt 2 }}{2}\left( {\cos \theta-\sin \theta } \right), \\\cos \left( {\frac{\pi }{4}-\theta } \right) = \frac{{\sqrt 2 }}{2}\left( {\cos \theta + \sin \theta } \right).\end{array} \right.$ (5)
通过上式(5)可将(π/8, π/4]内的角度折叠到[0, π/8]内,有
$\left\{ \begin{array}{l}\cos \theta = \frac{{\sqrt 2 }}{2}\left[{\cos \left( {\frac{\pi }{4}-\theta } \right) + \sin \left( {\frac{\pi }{4}-\theta } \right)} \right], \\\sin \theta = \frac{{\sqrt 2 }}{2}\left[{\cos \left( {\frac{\pi }{4}-\theta } \right)-\sin \left( {\frac{\pi }{4}-\theta } \right)} \right].\end{array} \right.$ (6)
从式(6)看出,只要得到[0, π/8]内角度的正余弦值,进行一次加减法运算和
表 1
![点击查看表格内容](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/table-icon.gif)
[0, π/8] θ cos θ′ sin θ′
(π/8, π/4] π/4-θ
(π/4,3π/8] θ-π/4
(3π/8,π/2] π/2-θ sin θ′ cos θ′
(π/2,5π/8] θ-π/2 -sin θ′ cos θ′
(5π/8,3π/4] 3π/4-θ -
(3π/4,7π/8] θ-3π/4 -
(7π/8,π] π-θ -cos θ′ sinθ′
(π,9π/8] θ-π -cos θ′ -sin θ′
(9π/8,5π/4] 5π/4-θ -
(5π/4,11π/8] θ-5π/4 -
(11π/8,3π/2] 3π/2-θ -sin θ′ -cos θ′
(3π/2,13π/8] θ-3π/2 sin θ′ -cos θ′
(13π/8, 7π/4] 7π/4-θ
(7π/4, 15π/8] θ-7π/4
(15π/8, 2π] 2π-θ cos θ′ -sin θ′
表 1 角度映射和正余弦转换关系 Table 1 Angle mapping and sine/cosine transition
将角度折叠到[0, π/8]可以省掉三阶段算法中第二阶段的蝶形运算过程,只需要进行第一阶段的移位相加迭代和第三阶段的合并迭代,随后根据角度映射和转换关系即可还原输出正余弦值.
3 算法实现对于三阶段算法,第一阶段是建立小容量查找表,将经过校模因子缩放后的横纵坐标值存放起来[15].向量旋转中初始坐标为(x0, y0)=(K, 0),其中K为校模因子且有:K=cos(φ0)·cos(2-3)·cos(2-4)·cos(2-5)···cos(2-N-1)那么经过逆时针旋转φ0后的坐标值为
Figure 3
![点击查看原图](http://hit.alljournals.cn/html/hitxb_cn/2017/11/PIC/hebgydxxb-49-11-109-3.jpg)
$\frac{{\sqrt 2 }}{2} \approx {2^{-1}} + {2^{-3}} + {2^{-4}} + {2^{ - 6}} + {2^{ - 8}} + {2^{ - 14}} + {2^{ - 16}}.$ (7)
因此
4 仿真结果及分析用Verilog HDL语言对传统流水线型CORDIC算法,三阶段CORDIC算法和免查找表CORDIC算法进行具体实现,在相同输出位宽的前提下,选用Xilinx公司的xc7k325t-2ffg900型号FPGA,利用ISE14.2自带的XST工具进行电路综合,得到寄存器和LUTs消耗情况以及最大输出时延见表 2.
表 2
![点击查看表格内容](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/table-icon.gif)
消耗的寄存器个数 消耗的LUTs个数 最大输出时延
流水线型CORDIC算法 778 836 16
三阶段CORDIC算法 351 679 6
免查找表CORDIC算法 199 696 5
表 2 三种算法的寄存器和LUTs消耗、最大输出时延 Table 2 Register and LUTs consumption, maximum output delay for three algorithms
寄存器的消耗主要取决于查找表的大小和迭代次数,最大输出时延与迭代次数有关.改进算法通过四次迭代替换查找表,又通过合并迭代减少大量的迭代,整体只需要5个时钟周期就能得到输出结果.比较三种算法使用的寄存器数量和最大输出时延可看出,改进算法使用的寄存器数量仅为流水线算法的25.58%,相比于三阶段算法节省了43.3%的寄存器消耗,最大输出时延相比于流水线型算法减少了68.75%.
利用MATLAB对三种算法进行建模和误差分析,输入角度以2-15分辨率遍历[0, π/2],计算得到绝对误差. 表 3、4分别列出三种算法正余弦误差的最大值、最小值以及平均绝对误差值,其中三种算法的余弦值绝对误差如图 4所示,其中红色点代表的是绝对误差的最大值与最小值.通过比较三种算法的平均绝对误差值,可看出改进算法与流水线型算法的平均绝对误差处于同一数量级,但改进算法的平均绝对误差相对较小.和三阶段算法相比,改进算法的平均绝对误差相差一个数量级,其主要原因是在中间数据位宽较少时式(4)的近似误差较大,这一误差可通过采用更大的中间数据位宽来减小.
表 3
![点击查看表格内容](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/table-icon.gif)
最大值 最小值 平均绝对误差
流水线型CORDIC算法 12.262 -18.964 6.925
三阶段CORDIC算法 1.192 -1.448 3.245×10-1
免查找表CORDIC算法 9.802 -6.872 2.496
表 3 三种算法的正弦值误差 Table 3 Sine errors of three algorithms
表 4
![点击查看表格内容](http://hit.alljournals.cn/html/hitxb_cn/2017/11/images/table-icon.gif)
最大值 最小值 平均绝对误差
流水线型CORDIC算法 22.526 -11.973 6.834
三阶段CORDIC算法 5.703×10-1 -1.178 3.549×10-1
免查找表CORDIC算法 9.699 -6.887 2.528
表 4 三种算法的余弦值误差 Table 4 Cosine errors of three algorithms
Figure 4
![点击查看原图](http://hit.alljournals.cn/html/hitxb_cn/2017/11/PIC/hebgydxxb-49-11-109-4.jpg)
5 结论针对传统流水线型CORDIC算法实现中存在的硬件资源消耗多、输出时延大等问题,结合角度二极化重编码、合并迭代以及角度区间折叠等技术提出了一种免查找表CORDIC算法.该算法将三阶段算法中的查找表替换为移位相加的迭代结构并省去了蝶形运算阶段,随后直接进行合并迭代,并根据角度映射关系还原输出结果.结果表明:与传统流水线型算法相比,免查找表算法的寄存器消耗减少了约74.42%,计算所需的时钟周期降低了68.75%.本文提出的免查找表CORDIC算法在实时性、输出精度、硬件资源消耗方面具有优势,适合高速实时的现代数字通信系统应用.
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